1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dce110/dce110_hwseq.h"
27 #include "dcn10/dcn10_hwseq.h"
28 #include "dcn20/dcn20_hwseq.h"
29 #include "dcn21/dcn21_hwseq.h"
30 #include "dcn30/dcn30_hwseq.h"
31 #include "dcn301/dcn301_hwseq.h"
32 #include "dcn31/dcn31_hwseq.h"
33 #include "dcn32/dcn32_hwseq.h"
34 #include "dcn35/dcn35_hwseq.h"
35 #include "dcn351/dcn351_hwseq.h"
36
37 #include "dcn351_init.h"
38
39 static const struct hw_sequencer_funcs dcn351_funcs = {
40 .program_gamut_remap = dcn30_program_gamut_remap,
41 .init_hw = dcn35_init_hw,
42 .power_down_on_boot = dcn35_power_down_on_boot,
43 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
44 .apply_ctx_for_surface = NULL,
45 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
46 .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
47 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
48 .update_plane_addr = dcn20_update_plane_addr,
49 .update_dchub = dcn10_update_dchub,
50 .update_pending_status = dcn10_update_pending_status,
51 .program_output_csc = dcn20_program_output_csc,
52 .enable_accelerated_mode = dce110_enable_accelerated_mode,
53 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
54 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
55 .update_info_frame = dcn31_update_info_frame,
56 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
57 .enable_stream = dcn20_enable_stream,
58 .disable_stream = dce110_disable_stream,
59 .unblank_stream = dcn32_unblank_stream,
60 .blank_stream = dce110_blank_stream,
61 .enable_audio_stream = dce110_enable_audio_stream,
62 .disable_audio_stream = dce110_disable_audio_stream,
63 .disable_plane = dcn35_disable_plane,
64 .disable_pixel_data = dcn20_disable_pixel_data,
65 .pipe_control_lock = dcn20_pipe_control_lock,
66 .interdependent_update_lock = dcn10_lock_all_pipes,
67 .cursor_lock = dcn10_cursor_lock,
68 .prepare_bandwidth = dcn35_prepare_bandwidth,
69 .optimize_bandwidth = dcn35_optimize_bandwidth,
70 .update_bandwidth = dcn20_update_bandwidth,
71 .set_drr = dcn35_set_drr,
72 .get_position = dcn10_get_position,
73 .set_static_screen_control = dcn35_set_static_screen_control,
74 .setup_stereo = dcn10_setup_stereo,
75 .set_avmute = dcn30_set_avmute,
76 .log_hw_state = dcn10_log_hw_state,
77 .get_hw_state = dcn10_get_hw_state,
78 .clear_status_bits = dcn10_clear_status_bits,
79 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
80 .edp_backlight_control = dce110_edp_backlight_control,
81 .edp_power_control = dce110_edp_power_control,
82 .edp_wait_for_T12 = dce110_edp_wait_for_T12,
83 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
84 .set_cursor_position = dcn10_set_cursor_position,
85 .set_cursor_attribute = dcn10_set_cursor_attribute,
86 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
87 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
88 .set_clock = dcn10_set_clock,
89 .get_clock = dcn10_get_clock,
90 .program_triplebuffer = dcn20_program_triple_buffer,
91 .enable_writeback = dcn30_enable_writeback,
92 .disable_writeback = dcn30_disable_writeback,
93 .update_writeback = dcn30_update_writeback,
94 .mmhubbub_warmup = dcn30_mmhubbub_warmup,
95 .dmdata_status_done = dcn20_dmdata_status_done,
96 .program_dmdata_engine = dcn30_program_dmdata_engine,
97 .set_dmdata_attributes = dcn20_set_dmdata_attributes,
98 .init_sys_ctx = dcn31_init_sys_ctx,
99 .init_vm_ctx = dcn20_init_vm_ctx,
100 .set_flip_control_gsl = dcn20_set_flip_control_gsl,
101 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
102 .calc_vupdate_position = dcn10_calc_vupdate_position,
103 .set_backlight_level = dcn21_set_backlight_level,
104 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
105 .set_pipe = dcn21_set_pipe,
106 .enable_lvds_link_output = dce110_enable_lvds_link_output,
107 .enable_tmds_link_output = dce110_enable_tmds_link_output,
108 .enable_dp_link_output = dce110_enable_dp_link_output,
109 .disable_link_output = dcn32_disable_link_output,
110 .z10_restore = dcn35_z10_restore,
111 .z10_save_init = dcn31_z10_save_init,
112 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
113 .optimize_pwr_state = dcn21_optimize_pwr_state,
114 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
115 .update_visual_confirm_color = dcn10_update_visual_confirm_color,
116 .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
117 .update_dsc_pg = dcn32_update_dsc_pg,
118 .calc_blocks_to_gate = dcn351_calc_blocks_to_gate,
119 .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,
120 .hw_block_power_up = dcn351_hw_block_power_up,
121 .hw_block_power_down = dcn351_hw_block_power_down,
122 .root_clock_control = dcn35_root_clock_control,
123 .set_long_vtotal = dcn35_set_long_vblank,
124 .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
125 .program_outstanding_updates = dcn32_program_outstanding_updates,
126 .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
127 };
128
129 static const struct hwseq_private_funcs dcn351_private_funcs = {
130 .init_pipes = dcn35_init_pipes,
131 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
132 .update_mpcc = dcn20_update_mpcc,
133 .set_input_transfer_func = dcn32_set_input_transfer_func,
134 .set_output_transfer_func = dcn32_set_output_transfer_func,
135 .power_down = dce110_power_down,
136 .enable_display_power_gating = dcn10_dummy_display_power_gating,
137 .blank_pixel_data = dcn20_blank_pixel_data,
138 .reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
139 .enable_stream_timing = dcn20_enable_stream_timing,
140 .edp_backlight_control = dce110_edp_backlight_control,
141 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
142 .did_underflow_occur = dcn10_did_underflow_occur,
143 .init_blank = dcn20_init_blank,
144 .disable_vga = NULL,
145 .bios_golden_init = dcn10_bios_golden_init,
146 .plane_atomic_disable = dcn35_plane_atomic_disable,
147 //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/
148 //.hubp_pg_control = dcn35_hubp_pg_control,
149 .enable_power_gating_plane = dcn35_enable_power_gating_plane,
150 .dpp_root_clock_control = dcn35_dpp_root_clock_control,
151 .dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
152 .physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
153 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
154 .update_odm = dcn35_update_odm,
155 .set_hdr_multiplier = dcn10_set_hdr_multiplier,
156 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
157 .wait_for_blank_complete = dcn20_wait_for_blank_complete,
158 .dccg_init = dcn20_dccg_init,
159 .set_mcm_luts = dcn32_set_mcm_luts,
160 .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
161 .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
162 .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
163 .dsc_pg_control = dcn35_dsc_pg_control,
164 .dsc_pg_status = dcn32_dsc_pg_status,
165 .enable_plane = dcn35_enable_plane,
166 };
167
dcn351_hw_sequencer_construct(struct dc * dc)168 void dcn351_hw_sequencer_construct(struct dc *dc)
169 {
170 dc->hwss = dcn351_funcs;
171 dc->hwseq->funcs = dcn351_private_funcs;
172
173 }
174