1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2025 Advanced Micro Devices, Inc. 4 5 #include "dm_services.h" 6 #include "dce_calcs.h" 7 #include "reg_helper.h" 8 #include "basics/conversion.h" 9 #include "dcn60_hubp.h" 10 11 #define REG(reg)\ 12 hubp2->hubp_regs->reg 13 14 #define CTX \ 15 hubp2->base.ctx 16 17 #undef FN 18 #define FN(reg_name, field_name) \ 19 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 20 21 static void hubp60_program_deadline( 22 struct hubp *hubp, 23 struct dml2_display_dlg_regs *dlg_attr, 24 struct dml2_display_ttu_regs *ttu_attr) 25 { 26 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 27 28 /* DLG - Per hubp */ 29 REG_SET_2(BLANK_OFFSET_0, 0, 30 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 31 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 32 33 REG_SET(BLANK_OFFSET_1, 0, 34 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 35 36 REG_SET(DST_DIMENSIONS, 0, 37 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 38 39 REG_SET_2(DST_AFTER_SCALER, 0, 40 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 41 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 42 43 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 44 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 45 46 /* DLG - Per luma/chroma */ 47 REG_SET(VBLANK_PARAMETERS_1, 0, 48 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 49 50 if (REG(NOM_PARAMETERS_0)) 51 REG_SET(NOM_PARAMETERS_0, 0, 52 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 53 54 if (REG(NOM_PARAMETERS_1)) 55 REG_SET(NOM_PARAMETERS_1, 0, 56 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 57 58 REG_SET(NOM_PARAMETERS_4, 0, 59 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 60 61 REG_SET(NOM_PARAMETERS_5, 0, 62 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 63 64 REG_SET_2(PER_LINE_DELIVERY, 0, 65 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 66 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 67 68 REG_SET(VBLANK_PARAMETERS_2, 0, 69 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 70 71 if (REG(NOM_PARAMETERS_2)) 72 REG_SET(NOM_PARAMETERS_2, 0, 73 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 74 75 if (REG(NOM_PARAMETERS_3)) 76 REG_SET(NOM_PARAMETERS_3, 0, 77 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 78 79 REG_SET(NOM_PARAMETERS_6, 0, 80 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 81 82 REG_SET(NOM_PARAMETERS_7, 0, 83 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 84 85 /* TTU - per luma/chroma */ 86 /* TO DO: Set URGENT_FORCE_x fields with values from DML if/when available */ 87 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 88 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 89 URGENT_FORCE_VALUE, 0, 90 URGENT_FORCE_EN, 0); 91 92 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 93 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 94 URGENT_FORCE_VALUE, 0, 95 URGENT_FORCE_EN, 0); 96 97 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 98 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 99 URGENT_FORCE_VALUE, 0, 100 URGENT_FORCE_EN, 0); 101 102 REG_SET(FLIP_PARAMETERS_1, 0, 103 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 104 REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group); 105 106 REG_UPDATE(DCN_DMDATA_VM_CNTL, 107 REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata); 108 } 109 110 void hubp60_setup( 111 struct hubp *hubp, 112 struct dml2_dchub_per_pipe_register_set *pipe_regs, 113 union dml2_global_sync_programming *pipe_global_sync, 114 struct dc_crtc_timing *timing) 115 { 116 /* otg is locked when this func is called. Register are double buffered. 117 * disable the requestors is not needed 118 */ 119 hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing); 120 hubp401_program_requestor(hubp, &pipe_regs->rq_regs); 121 hubp60_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); 122 } 123 124 void hubp60_setup_interdependent( 125 struct hubp *hubp, 126 struct dml2_dchub_per_pipe_register_set *pipe_regs) 127 { 128 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 129 130 REG_SET_3(PREFETCH_SETTINGS, 0, 131 DST_Y_PREFETCH, pipe_regs->dlg_regs.dst_y_prefetch, 132 VRATIO_PREFETCH, pipe_regs->dlg_regs.vratio_prefetch, 133 FORCE_DISP_PREF_TO_VBLANK, pipe_regs->dlg_regs.force_prefetch_to_vblank); 134 135 REG_SET(PREFETCH_SETTINGS_C, 0, 136 VRATIO_PREFETCH_C, pipe_regs->dlg_regs.vratio_prefetch_c); 137 138 REG_SET_2(VBLANK_PARAMETERS_0, 0, 139 DST_Y_PER_VM_VBLANK, pipe_regs->dlg_regs.dst_y_per_vm_vblank, 140 DST_Y_PER_ROW_VBLANK, pipe_regs->dlg_regs.dst_y_per_row_vblank); 141 142 REG_SET_2(FLIP_PARAMETERS_0, 0, 143 DST_Y_PER_VM_FLIP, pipe_regs->dlg_regs.dst_y_per_vm_flip, 144 DST_Y_PER_ROW_FLIP, pipe_regs->dlg_regs.dst_y_per_row_flip); 145 146 REG_SET(VBLANK_PARAMETERS_3, 0, 147 REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_l); 148 149 REG_SET(VBLANK_PARAMETERS_4, 0, 150 REFCYC_PER_META_CHUNK_VBLANK_C, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_c); 151 152 REG_SET(FLIP_PARAMETERS_2, 0, 153 REFCYC_PER_META_CHUNK_FLIP_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_flip_l); 154 155 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 156 REFCYC_PER_LINE_DELIVERY_PRE_L, pipe_regs->dlg_regs.refcyc_per_line_delivery_pre_l, 157 REFCYC_PER_LINE_DELIVERY_PRE_C, pipe_regs->dlg_regs.refcyc_per_line_delivery_pre_c); 158 159 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 160 REFCYC_PER_REQ_DELIVERY_PRE, 161 pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_l); 162 163 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 164 REFCYC_PER_REQ_DELIVERY_PRE, 165 pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_c); 166 167 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 168 REFCYC_PER_REQ_DELIVERY_PRE, pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_cur0); 169 170 REG_SET(DCN_GLOBAL_TTU_CNTL, 0, 171 MIN_TTU_VBLANK, pipe_regs->ttu_regs.min_ttu_vblank); 172 173 REG_SET(DST_Y_DELTA_DRQ_LIMIT, 0, 174 DST_Y_DELTA_DRQ_LIMIT, pipe_regs->dlg_regs.dst_y_delta_drq_limit); 175 176 REG_SET(DST_Y_ALT_CH_DRQ_LIMIT, 0, 177 DST_Y_ALT_CH_DRQ_LIMIT, pipe_regs->dlg_regs.dst_y_svp_drq_limit); 178 } 179 180 void hubp60_cursor_set_attributes( 181 struct hubp *hubp, 182 const struct dc_cursor_attributes *attr) 183 { 184 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 185 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 186 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 187 attr->width, attr->color_format); 188 189 //Round cursor width up to next multiple of 64 190 uint32_t cursor_width = ((attr->width + 63) / 64) * 64; 191 192 hubp->curs_attr = *attr; 193 194 if (!hubp->cursor_offload) { 195 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 196 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 197 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 198 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 199 200 REG_UPDATE_2(CURSOR_SIZE, 201 CURSOR_WIDTH, cursor_width, 202 CURSOR_HEIGHT, attr->height); 203 204 REG_UPDATE_4(CURSOR_CONTROL, 205 CURSOR_MODE, attr->color_format, 206 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 207 CURSOR_PITCH, hw_pitch, 208 CURSOR_LINES_PER_CHUNK, lpc); 209 210 REG_SET_3(CURSOR_SETTINGS, 0, 211 /* no shift of the cursor HDL schedule */ 212 CURSOR0_DST_Y_OFFSET, 0, 213 /* used to shift the cursor chunk request deadline */ 214 CURSOR0_CHUNK_HDL_ADJUST, 3, 215 FORCE_CURSOR_TO_DISP_PREF, attr->force_cursor_to_disp_pref); 216 } 217 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; 218 hubp->att.SURFACE_ADDR = attr->address.low_part; 219 hubp->att.size.bits.width = attr->width; 220 hubp->att.size.bits.height = attr->height; 221 hubp->att.cur_ctl.bits.mode = attr->color_format; 222 223 hubp->cur_rect.w = attr->width; 224 hubp->cur_rect.h = attr->height; 225 226 hubp->att.cur_ctl.bits.pitch = hw_pitch; 227 hubp->att.cur_ctl.bits.line_per_chunk = lpc; 228 hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION; 229 hubp->att.settings.bits.dst_y_offset = 0; 230 hubp->att.settings.bits.chunk_hdl_adjust = 3; 231 hubp->att.settings.bits.force_cursor_to_disp_pref = attr->force_cursor_to_disp_pref; 232 } 233 234 void hubp60_read_state(struct hubp *hubp) 235 { 236 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 237 struct dcn_hubp_state *s = &hubp2->state; 238 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 239 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 240 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 241 242 /* Requester */ 243 REG_GET(HUBPRET_CONTROL, 244 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 245 REG_GET_4(DCN_EXPANSION_MODE, 246 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 247 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 248 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 249 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 250 251 REG_GET_5(DCHUBP_REQ_SIZE_CONFIG, 252 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 253 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 254 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 255 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 256 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 257 258 REG_GET_5(DCHUBP_REQ_SIZE_CONFIG_C, 259 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 260 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 261 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 262 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 263 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 264 265 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 266 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 267 268 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 269 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 270 271 /* DLG - Per hubp */ 272 REG_GET_2(BLANK_OFFSET_0, 273 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 274 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 275 276 REG_GET(BLANK_OFFSET_1, 277 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 278 279 REG_GET(DST_DIMENSIONS, 280 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 281 282 REG_GET_2(DST_AFTER_SCALER, 283 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 284 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 285 286 REG_GET_2(PREFETCH_SETTINGS, 287 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 288 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 289 290 REG_GET_2(VBLANK_PARAMETERS_0, 291 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 292 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 293 294 REG_GET(REF_FREQ_TO_PIX_FREQ, 295 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 296 297 /* DLG - Per luma/chroma */ 298 REG_GET(VBLANK_PARAMETERS_1, 299 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 300 301 REG_GET(VBLANK_PARAMETERS_3, 302 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 303 304 REG_GET(NOM_PARAMETERS_0, 305 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 306 307 REG_GET(NOM_PARAMETERS_1, 308 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 309 310 REG_GET(NOM_PARAMETERS_4, 311 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 312 313 REG_GET(NOM_PARAMETERS_5, 314 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 315 316 REG_GET_2(PER_LINE_DELIVERY_PRE, 317 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 318 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 319 320 REG_GET_2(PER_LINE_DELIVERY, 321 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 322 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 323 324 REG_GET(PREFETCH_SETTINGS_C, 325 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 326 327 REG_GET(VBLANK_PARAMETERS_2, 328 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 329 330 REG_GET(VBLANK_PARAMETERS_4, 331 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 332 333 REG_GET(NOM_PARAMETERS_2, 334 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 335 336 REG_GET(NOM_PARAMETERS_3, 337 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 338 339 REG_GET(NOM_PARAMETERS_6, 340 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 341 342 REG_GET(NOM_PARAMETERS_7, 343 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 344 345 REG_GET(DCN_GLOBAL_TTU_CNTL, 346 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank); 347 348 /* TTU - per luma/chroma */ 349 /* Assumed surf0 is luma and 1 is chroma */ 350 351 REG_GET(DCN_SURF0_TTU_CNTL0, 352 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l); 353 354 REG_GET(DCN_SURF0_TTU_CNTL1, 355 REFCYC_PER_REQ_DELIVERY_PRE, 356 &ttu_attr->refcyc_per_req_delivery_pre_l); 357 358 REG_GET(DCN_SURF1_TTU_CNTL0, 359 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c); 360 361 REG_GET(DCN_SURF1_TTU_CNTL1, 362 REFCYC_PER_REQ_DELIVERY_PRE, 363 &ttu_attr->refcyc_per_req_delivery_pre_c); 364 365 /* Rest of hubp */ 366 REG_GET(DCSURF_SURFACE_CONFIG, 367 SURFACE_PIXEL_FORMAT, &s->pixel_format); 368 369 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 370 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 371 372 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 373 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 374 375 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 376 PRI_VIEWPORT_WIDTH, &s->viewport_width, 377 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 378 379 REG_GET_2(DCSURF_SURFACE_CONFIG, 380 ROTATION_ANGLE, &s->rotation_angle, 381 H_MIRROR_EN, &s->h_mirror_en); 382 383 REG_GET(DCSURF_TILING_CONFIG, 384 SW_MODE, &s->sw_mode); 385 386 REG_GET(DCSURF_SURFACE_CONTROL, 387 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 388 389 REG_GET_3(DCHUBP_CNTL, 390 HUBP_BLANK_EN, &s->blank_en, 391 HUBP_TTU_DISABLE, &s->ttu_disable, 392 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 393 394 REG_GET(HUBP_CLK_CNTL, 395 HUBP_CLOCK_ENABLE, &s->clock_en); 396 397 REG_GET(DCN_GLOBAL_TTU_CNTL, 398 MIN_TTU_VBLANK, &s->min_ttu_vblank); 399 400 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 401 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 402 403 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 404 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 405 406 s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE); 407 408 s->hubp_cntl = REG_READ(DCHUBP_CNTL); 409 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL); 410 } 411 412 static struct hubp_funcs dcn60_hubp_funcs = { 413 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 414 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 415 .hubp_program_surface_flip_and_addr = hubp50_program_surface_flip_and_addr, 416 .hubp_program_surface_config = hubp50_program_surface_config, 417 .hubp_is_flip_pending = hubp2_is_flip_pending, 418 .hubp_setup2 = hubp60_setup, 419 .hubp_setup_interdependent2 = hubp60_setup_interdependent, 420 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, 421 .set_blank = hubp2_set_blank, 422 .set_blank_regs = hubp2_set_blank_regs, 423 .hubp_reset = hubp_reset, 424 .mem_program_viewport = hubp401_set_viewport, 425 .set_cursor_attributes = hubp60_cursor_set_attributes, 426 .set_cursor_position = hubp401_cursor_set_position, 427 .hubp_clk_cntl = hubp2_clk_cntl, 428 .hubp_vtg_sel = hubp2_vtg_sel, 429 .dmdata_set_attributes = hubp3_dmdata_set_attributes, 430 .dmdata_load = hubp2_dmdata_load, 431 .dmdata_status_done = hubp2_dmdata_status_done, 432 .hubp_read_state = hubp60_read_state, 433 .hubp_clear_underflow = hubp2_clear_underflow, 434 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 435 .hubp_init = hubp401_init, 436 .set_unbounded_requesting = hubp401_set_unbounded_requesting, 437 .hubp_soft_reset = hubp31_soft_reset, 438 .hubp_set_flip_int = hubp401_set_flip_int, 439 .hubp_in_blank = hubp401_in_blank, 440 .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable, 441 .hubp_update_mall_sel = NULL, 442 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, 443 .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, 444 .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, 445 .hubp_program_3dlut_fl_config = hubp42_program_3dlut_fl_config, 446 .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, 447 .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, 448 .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, 449 .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, 450 .hubp_clear_tiling = hubp401_clear_tiling, 451 .hubp_read_reg_state = hubp3_read_reg_state 452 }; 453 454 bool hubp60_construct( 455 struct dcn20_hubp *hubp2, 456 struct dc_context *ctx, 457 uint32_t inst, 458 const struct dcn_hubp2_registers *hubp_regs, 459 const struct dcn_hubp2_shift *hubp_shift, 460 const struct dcn_hubp2_mask *hubp_mask) 461 { 462 hubp2->base.funcs = &dcn60_hubp_funcs; 463 hubp2->base.ctx = ctx; 464 hubp2->hubp_regs = hubp_regs; 465 hubp2->hubp_shift = hubp_shift; 466 hubp2->hubp_mask = hubp_mask; 467 hubp2->base.inst = inst; 468 hubp2->base.opp_id = OPP_ID_INVALID; 469 hubp2->base.mpcc_id = 0xf; 470 471 return true; 472 } 473