1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2025 Advanced Micro Devices, Inc. 4 5 #include "dm_services.h" 6 #include "dce_calcs.h" 7 #include "reg_helper.h" 8 #include "basics/conversion.h" 9 #include "dcn50_hubp.h" 10 #include "dcn42/dcn42_hubp.h" 11 12 #define REG(reg)\ 13 hubp2->hubp_regs->reg 14 15 #define CTX \ 16 hubp2->base.ctx 17 18 #undef FN 19 #define FN(reg_name, field_name) \ 20 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 21 22 bool hubp50_program_surface_flip_and_addr( 23 struct hubp *hubp, 24 const struct dc_plane_address *address, 25 bool flip_immediate) 26 { 27 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 28 29 //program flip type 30 REG_UPDATE(DCSURF_FLIP_CONTROL, 31 SURFACE_FLIP_TYPE, flip_immediate); 32 33 // Program VMID reg 34 if (flip_immediate == 0) 35 REG_UPDATE(VMID_SETTINGS_0, 36 VMID, address->vmid); 37 38 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 39 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0); 40 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 41 42 } else { 43 // turn off stereo if not in stereo 44 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 45 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 46 } 47 48 /* HW automatically latch rest of address register on write to 49 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 50 * 51 * program high first and then the low addr, order matters! 52 */ 53 switch (address->type) { 54 case PLN_ADDR_TYPE_GRAPHICS: 55 if (address->grph.addr.quad_part == 0) 56 break; 57 58 REG_UPDATE(DCSURF_SURFACE_CONTROL, 59 PRIMARY_SURFACE_TMZ, address->tmz_surface); 60 61 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 62 PRIMARY_SURFACE_ADDRESS_HIGH, 63 address->grph.addr.high_part); 64 65 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 66 PRIMARY_SURFACE_ADDRESS, 67 address->grph.addr.low_part); 68 break; 69 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 70 if (address->video_progressive.luma_addr.quad_part == 0 71 || address->video_progressive.chroma_addr.quad_part == 0) 72 break; 73 74 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 75 PRIMARY_SURFACE_TMZ, address->tmz_surface, 76 PRIMARY_SURFACE_TMZ_C, address->tmz_surface); 77 78 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 79 PRIMARY_SURFACE_ADDRESS_HIGH_C, 80 address->video_progressive.chroma_addr.high_part); 81 82 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 83 PRIMARY_SURFACE_ADDRESS_C, 84 address->video_progressive.chroma_addr.low_part); 85 86 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 87 PRIMARY_SURFACE_ADDRESS_HIGH, 88 address->video_progressive.luma_addr.high_part); 89 90 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 91 PRIMARY_SURFACE_ADDRESS, 92 address->video_progressive.luma_addr.low_part); 93 break; 94 case PLN_ADDR_TYPE_GRPH_STEREO: 95 if (address->grph_stereo.left_addr.quad_part == 0 96 || address->grph_stereo.right_addr.quad_part == 0) 97 break; 98 99 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 100 PRIMARY_SURFACE_TMZ, address->tmz_surface, 101 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 102 SECONDARY_SURFACE_TMZ, address->tmz_surface, 103 SECONDARY_SURFACE_TMZ_C, address->tmz_surface); 104 105 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0, 106 SECONDARY_SURFACE_ADDRESS_HIGH_C, 107 address->grph_stereo.right_alpha_addr.high_part); 108 109 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0, 110 SECONDARY_SURFACE_ADDRESS_C, 111 address->grph_stereo.right_alpha_addr.low_part); 112 113 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 114 SECONDARY_SURFACE_ADDRESS_HIGH, 115 address->grph_stereo.right_addr.high_part); 116 117 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 118 SECONDARY_SURFACE_ADDRESS, 119 address->grph_stereo.right_addr.low_part); 120 121 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 122 PRIMARY_SURFACE_ADDRESS_HIGH_C, 123 address->grph_stereo.left_alpha_addr.high_part); 124 125 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 126 PRIMARY_SURFACE_ADDRESS_C, 127 address->grph_stereo.left_alpha_addr.low_part); 128 129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 130 PRIMARY_SURFACE_ADDRESS_HIGH, 131 address->grph_stereo.left_addr.high_part); 132 133 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 134 PRIMARY_SURFACE_ADDRESS, 135 address->grph_stereo.left_addr.low_part); 136 break; 137 case PLN_ADDR_TYPE_RGBEA: 138 if (address->rgbea.addr.quad_part == 0 139 || address->rgbea.alpha_addr.quad_part == 0) 140 break; 141 142 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 143 PRIMARY_SURFACE_TMZ, address->tmz_surface, 144 PRIMARY_SURFACE_TMZ_C, address->tmz_surface); 145 146 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 147 PRIMARY_SURFACE_ADDRESS_HIGH_C, 148 address->rgbea.alpha_addr.high_part); 149 150 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 151 PRIMARY_SURFACE_ADDRESS_C, 152 address->rgbea.alpha_addr.low_part); 153 154 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 155 PRIMARY_SURFACE_ADDRESS_HIGH, 156 address->rgbea.addr.high_part); 157 158 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 159 PRIMARY_SURFACE_ADDRESS, 160 address->rgbea.addr.low_part); 161 break; 162 default: 163 BREAK_TO_DEBUGGER(); 164 break; 165 } 166 167 hubp->request_address = *address; 168 169 return true; 170 } 171 172 static enum swizzle_mode_values hubp50_addr3_to_swizzle_mode_mapping(enum swizzle_mode_addr3_values addr3_swizzle_mode) 173 { 174 enum swizzle_mode_values swizzle_mode = DC_SW_UNKNOWN; 175 176 switch (addr3_swizzle_mode) { 177 case DC_ADDR3_SW_LINEAR: 178 swizzle_mode = DC_SW_LINEAR; 179 break; 180 case DC_ADDR3_SW_256B_2D: 181 swizzle_mode = DC_SW_256_R; 182 break; 183 case DC_ADDR3_SW_4KB_2D: 184 swizzle_mode = DC_SW_4KB_R; 185 break; 186 case DC_ADDR3_SW_64KB_2D: 187 case DC_ADDR3_SW_64KB_2D_Z: 188 swizzle_mode = DC_SW_64KB_R; 189 break; 190 case DC_ADDR3_SW_256KB_2D: 191 case DC_ADDR3_SW_256KB_2D_Z: 192 swizzle_mode = DC_SW_VAR_R; 193 break; 194 case DC_ADDR3_SW_4KB_3D: 195 case DC_ADDR3_SW_64KB_3D: 196 case DC_ADDR3_SW_256KB_3D: 197 default: 198 BREAK_TO_DEBUGGER(); 199 break; 200 } 201 202 return swizzle_mode; 203 } 204 205 static void hubp50_program_tiling( 206 struct dcn20_hubp *hubp2, 207 const struct dc_tiling_info *info, 208 const enum surface_pixel_format pixel_format) 209 { 210 (void)pixel_format; 211 /* Tiling address-generation compatibility level programmed into the 212 * DCSURF_TILING_CONFIG.COMPAT_LEVEL register field: 213 * 0 - gfx8 bank_height == 1 214 * 1 - gfx8 bank_height == 2 215 * 2 - gfx9/10/11 216 * 5 - gfx addr3 217 */ 218 unsigned int compat_level = 0; 219 enum swizzle_mode_values swizzle_mode; 220 221 switch (info->gfxversion) { 222 case DcGfxVersion7: 223 case DcGfxVersion8: 224 225 REG_UPDATE_8(DCSURF_LEGACY_ADDR_CONFIG, 226 LEGACY_NUM_BANKS, info->gfx8.num_banks, 227 BANK_WIDTH, info->gfx8.bank_width, 228 BANK_HEIGHT, info->gfx8.bank_height, 229 MACRO_TILE_ASPECT, info->gfx8.tile_aspect, 230 TILE_SPLIT, info->gfx8.tile_split, 231 MICRO_TILE_MODE_NEW, info->gfx8.tile_mode, 232 PIPE_CONFIG, info->gfx8.pipe_config, 233 ARRAY_MODE, info->gfx8.array_mode); 234 if (info->gfx8.bank_height == 1) { 235 compat_level = 0; 236 } else if (info->gfx8.bank_height == 2) { 237 compat_level = 1; 238 } 239 break; 240 241 case DcGfxVersion9: 242 case DcGfxVersion10: 243 case DcGfxVersion11: 244 REG_UPDATE_4(DCSURF_ADDR_CONFIG, 245 NUM_PIPES, log_2(info->gfx9.num_pipes), 246 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 247 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), 248 NUM_PKRS, log_2(info->gfx9.num_pkrs)); 249 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx9.swizzle); 250 compat_level = 2; 251 252 break; 253 case DcGfxAddr3: 254 swizzle_mode = hubp50_addr3_to_swizzle_mode_mapping(info->gfx_addr3.swizzle); 255 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, swizzle_mode); 256 compat_level = 5; 257 break; 258 } 259 260 REG_UPDATE(DCSURF_TILING_CONFIG, COMPAT_LEVEL, compat_level); 261 } 262 static void hubp50_program_pixel_format( 263 struct hubp *hubp, 264 enum surface_pixel_format format) 265 { 266 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 267 uint32_t red_bar = 3; 268 uint32_t blue_bar = 2; 269 270 /* swap for ABGR format */ 271 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 272 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 273 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 274 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 275 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 276 red_bar = 2; 277 blue_bar = 3; 278 } 279 280 REG_UPDATE_2(HUBPRET_CONTROL, 281 CROSSBAR_SRC_CB_B, blue_bar, 282 CROSSBAR_SRC_CR_R, red_bar); 283 284 /* Mapping is same as ipp programming (cnvc) */ 285 286 switch (format) { 287 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 288 REG_UPDATE(DCSURF_SURFACE_CONFIG, 289 SURFACE_PIXEL_FORMAT, 1); 290 break; 291 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 292 REG_UPDATE(DCSURF_SURFACE_CONFIG, 293 SURFACE_PIXEL_FORMAT, 3); 294 break; 295 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 296 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 297 REG_UPDATE(DCSURF_SURFACE_CONFIG, 298 SURFACE_PIXEL_FORMAT, 8); 299 break; 300 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 301 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 302 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 303 REG_UPDATE(DCSURF_SURFACE_CONFIG, 304 SURFACE_PIXEL_FORMAT, 10); 305 break; 306 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 307 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */ 308 REG_UPDATE(DCSURF_SURFACE_CONFIG, 309 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 310 break; 311 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 312 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 313 REG_UPDATE(DCSURF_SURFACE_CONFIG, 314 SURFACE_PIXEL_FORMAT, 24); 315 break; 316 317 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 318 REG_UPDATE(DCSURF_SURFACE_CONFIG, 319 SURFACE_PIXEL_FORMAT, 65); 320 break; 321 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 322 REG_UPDATE(DCSURF_SURFACE_CONFIG, 323 SURFACE_PIXEL_FORMAT, 64); 324 break; 325 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 326 REG_UPDATE(DCSURF_SURFACE_CONFIG, 327 SURFACE_PIXEL_FORMAT, 67); 328 break; 329 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 330 REG_UPDATE(DCSURF_SURFACE_CONFIG, 331 SURFACE_PIXEL_FORMAT, 66); 332 break; 333 /* Planar 422 formats*/ 334 case SURFACE_PIXEL_FORMAT_VIDEO_422_CrCb_P208: 335 REG_UPDATE(DCSURF_SURFACE_CONFIG, 336 SURFACE_PIXEL_FORMAT, 64); 337 break; 338 case SURFACE_PIXEL_FORMAT_VIDEO_422_CbCr_P208: 339 REG_UPDATE(DCSURF_SURFACE_CONFIG, 340 SURFACE_PIXEL_FORMAT, 65); 341 break; 342 case SURFACE_PIXEL_FORMAT_VIDEO_422_CrCb_P210: 343 REG_UPDATE(DCSURF_SURFACE_CONFIG, 344 SURFACE_PIXEL_FORMAT, 66); 345 break; 346 case SURFACE_PIXEL_FORMAT_VIDEO_422_CbCr_P210: 347 REG_UPDATE(DCSURF_SURFACE_CONFIG, 348 SURFACE_PIXEL_FORMAT, 67); 349 break; 350 case SURFACE_PIXEL_FORMAT_VIDEO_422_CrCb_P212: 351 REG_UPDATE(DCSURF_SURFACE_CONFIG, 352 SURFACE_PIXEL_FORMAT, 68); 353 break; 354 case SURFACE_PIXEL_FORMAT_VIDEO_422_CbCr_P212: 355 REG_UPDATE(DCSURF_SURFACE_CONFIG, 356 SURFACE_PIXEL_FORMAT, 69); 357 break; 358 /* Packed 422 formats*/ 359 case SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: 360 REG_UPDATE(DCSURF_SURFACE_CONFIG, 361 SURFACE_PIXEL_FORMAT, 72); 362 break; 363 case SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: 364 REG_UPDATE(DCSURF_SURFACE_CONFIG, 365 SURFACE_PIXEL_FORMAT, 73); 366 break; 367 case SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: 368 REG_UPDATE(DCSURF_SURFACE_CONFIG, 369 SURFACE_PIXEL_FORMAT, 74); 370 break; 371 case SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: 372 REG_UPDATE(DCSURF_SURFACE_CONFIG, 373 SURFACE_PIXEL_FORMAT, 75); 374 break; 375 case SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: 376 REG_UPDATE(DCSURF_SURFACE_CONFIG, 377 SURFACE_PIXEL_FORMAT, 76); 378 break; 379 case SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: 380 REG_UPDATE(DCSURF_SURFACE_CONFIG, 381 SURFACE_PIXEL_FORMAT, 77); 382 break; 383 case SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: 384 REG_UPDATE(DCSURF_SURFACE_CONFIG, 385 SURFACE_PIXEL_FORMAT, 78); 386 break; 387 case SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: 388 REG_UPDATE(DCSURF_SURFACE_CONFIG, 389 SURFACE_PIXEL_FORMAT, 79); 390 break; 391 case SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: 392 REG_UPDATE(DCSURF_SURFACE_CONFIG, 393 SURFACE_PIXEL_FORMAT, 80); 394 break; 395 case SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: 396 REG_UPDATE(DCSURF_SURFACE_CONFIG, 397 SURFACE_PIXEL_FORMAT, 81); 398 break; 399 case SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: 400 REG_UPDATE(DCSURF_SURFACE_CONFIG, 401 SURFACE_PIXEL_FORMAT, 82); 402 break; 403 case SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: 404 REG_UPDATE(DCSURF_SURFACE_CONFIG, 405 SURFACE_PIXEL_FORMAT, 83); 406 break; 407 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 408 REG_UPDATE(DCSURF_SURFACE_CONFIG, 409 SURFACE_PIXEL_FORMAT, 12); 410 break; 411 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 412 REG_UPDATE(DCSURF_SURFACE_CONFIG, 413 SURFACE_PIXEL_FORMAT, 112); 414 break; 415 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 416 REG_UPDATE(DCSURF_SURFACE_CONFIG, 417 SURFACE_PIXEL_FORMAT, 113); 418 break; 419 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 420 REG_UPDATE(DCSURF_SURFACE_CONFIG, 421 SURFACE_PIXEL_FORMAT, 114); 422 break; 423 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 424 REG_UPDATE(DCSURF_SURFACE_CONFIG, 425 SURFACE_PIXEL_FORMAT, 118); 426 break; 427 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 428 REG_UPDATE(DCSURF_SURFACE_CONFIG, 429 SURFACE_PIXEL_FORMAT, 119); 430 break; 431 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 432 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 433 SURFACE_PIXEL_FORMAT, 116, 434 ALPHA_PLANE_EN, 0); 435 break; 436 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 437 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 438 SURFACE_PIXEL_FORMAT, 116, 439 ALPHA_PLANE_EN, 1); 440 break; 441 default: 442 BREAK_TO_DEBUGGER(); 443 break; 444 } 445 } 446 447 void hubp50_program_surface_config( 448 struct hubp *hubp, 449 enum surface_pixel_format format, 450 struct dc_tiling_info *tiling_info, 451 struct plane_size *plane_size, 452 enum dc_rotation_angle rotation, 453 struct dc_plane_dcc_param *dcc, 454 bool horizontal_mirror, 455 unsigned int compat_level) 456 { 457 (void)compat_level; 458 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 459 460 hubp401_dcc_control(hubp, dcc); 461 hubp50_program_tiling(hubp2, tiling_info, format); 462 hubp401_program_size(hubp, format, plane_size, dcc); 463 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 464 hubp50_program_pixel_format(hubp, format); 465 } 466 467 void hubp50_read_state(struct hubp *hubp) 468 { 469 hubp401_read_state(hubp); 470 } 471 472 static struct hubp_funcs dcn50_hubp_funcs = { 473 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 474 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 475 .hubp_program_surface_flip_and_addr = hubp50_program_surface_flip_and_addr, 476 .hubp_program_surface_config = hubp50_program_surface_config, 477 .hubp_is_flip_pending = hubp2_is_flip_pending, 478 .hubp_setup2 = hubp401_setup, 479 .hubp_setup_interdependent2 = hubp401_setup_interdependent, 480 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, 481 .set_blank = hubp2_set_blank, 482 .set_blank_regs = hubp2_set_blank_regs, 483 .hubp_reset = hubp_reset, 484 .mem_program_viewport = hubp401_set_viewport, 485 .set_cursor_attributes = hubp32_cursor_set_attributes, 486 .set_cursor_position = hubp401_cursor_set_position, 487 .hubp_clk_cntl = hubp2_clk_cntl, 488 .hubp_vtg_sel = hubp2_vtg_sel, 489 .dmdata_set_attributes = hubp3_dmdata_set_attributes, 490 .dmdata_load = hubp2_dmdata_load, 491 .dmdata_status_done = hubp2_dmdata_status_done, 492 .hubp_read_state = hubp50_read_state, 493 .hubp_clear_underflow = hubp2_clear_underflow, 494 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 495 .hubp_init = hubp401_init, 496 .set_unbounded_requesting = hubp401_set_unbounded_requesting, 497 .hubp_soft_reset = hubp31_soft_reset, 498 .hubp_set_flip_int = hubp401_set_flip_int, 499 .hubp_in_blank = hubp401_in_blank, 500 .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable, 501 .hubp_update_mall_sel = hubp401_update_mall_sel, 502 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, 503 .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, 504 .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, 505 .hubp_program_3dlut_fl_config = hubp42_program_3dlut_fl_config, 506 .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, 507 .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, 508 .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, 509 .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, 510 .hubp_clear_tiling = hubp401_clear_tiling, 511 .hubp_read_reg_state = hubp3_read_reg_state 512 }; 513 514 bool hubp50_construct( 515 struct dcn20_hubp *hubp2, 516 struct dc_context *ctx, 517 uint32_t inst, 518 const struct dcn_hubp2_registers *hubp_regs, 519 const struct dcn_hubp2_shift *hubp_shift, 520 const struct dcn_hubp2_mask *hubp_mask) 521 { 522 hubp2->base.funcs = &dcn50_hubp_funcs; 523 hubp2->base.ctx = ctx; 524 hubp2->hubp_regs = hubp_regs; 525 hubp2->hubp_shift = hubp_shift; 526 hubp2->hubp_mask = hubp_mask; 527 hubp2->base.inst = inst; 528 hubp2->base.opp_id = OPP_ID_INVALID; 529 hubp2->base.mpcc_id = 0xf; 530 531 return true; 532 } 533