1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2025 Advanced Micro Devices, Inc. 4 5 #include "hw_translate_dcn60.h" 6 7 #include "dm_services.h" 8 #include "include/gpio_types.h" 9 #include "../hw_translate.h" 10 11 #include "dcn/dcn_6_0_0_offset.h" 12 #include "dcn/dcn_6_0_0_sh_mask.h" 13 #include "dpcs/dpcs_6_0_0_offset.h" 14 #include "dpcs/dpcs_6_0_0_sh_mask.h" 15 16 #define DCN_BASE__INST0_SEG2 0x000034C0 17 18 /* begin ********************* 19 * macros to expend register list macro defined in HW object header file */ 20 21 /* DCN */ 22 #define block HPD 23 #define reg_num 0 24 25 #undef BASE_INNER 26 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 27 28 #define BASE(seg) BASE_INNER(seg) 29 30 #undef REG 31 #define REG(reg_name)\ 32 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name 33 #define SF_HPD(reg_name, field_name, post_fix)\ 34 .field_name = reg_name ## __ ## field_name ## post_fix 35 36 /* macros to expend register list macro defined in HW object header file 37 * end *********************/ 38 39 static bool dcn60_offset_to_id( 40 uint32_t offset, 41 uint32_t mask, 42 enum gpio_id *id, 43 uint32_t *en) 44 { 45 (void)mask; 46 switch (offset) { 47 /* HPD */ 48 case REG(HPD0_DC_HPD_INT_STATUS): 49 *id = GPIO_ID_HPD; 50 *en = GPIO_HPD_1; 51 return true; 52 case REG(HPD1_DC_HPD_INT_STATUS): 53 *id = GPIO_ID_HPD; 54 *en = GPIO_HPD_2; 55 return true; 56 case REG(HPD2_DC_HPD_INT_STATUS): 57 *id = GPIO_ID_HPD; 58 *en = GPIO_HPD_3; 59 return true; 60 case REG(HPD3_DC_HPD_INT_STATUS): 61 *id = GPIO_ID_HPD; 62 *en = GPIO_HPD_4; 63 return true; 64 /* DDC */ 65 /* we don't care about the GPIO_ID for DDC 66 * it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK 67 * directly in the create method 68 */ 69 case REG(DC_I3C0_DC_I3CPAD_CONTROL0): 70 *en = GPIO_DDC_LINE_DDC1; 71 return true; 72 case REG(DC_I3C1_DC_I3CPAD_CONTROL0): 73 *en = GPIO_DDC_LINE_DDC2; 74 return true; 75 76 /* UNEXPECTED */ 77 default: 78 ASSERT_CRITICAL(false); 79 return false; 80 } 81 } 82 83 static bool dcn60_id_to_offset( 84 enum gpio_id id, 85 uint32_t en, 86 struct gpio_pin_info *info) 87 { 88 bool result = true; 89 90 switch (id) { 91 case GPIO_ID_DDC_DATA: 92 switch (en) { 93 case GPIO_DDC_LINE_DDC1: 94 info->offset = REG(DC_I3C0_DC_I3CPAD_CONTROL0); 95 break; 96 case GPIO_DDC_LINE_DDC2: 97 info->offset = REG(DC_I3C1_DC_I3CPAD_CONTROL0); 98 break; 99 default: 100 ASSERT_CRITICAL(false); 101 result = false; 102 } 103 break; 104 case GPIO_ID_DDC_CLOCK: 105 switch (en) { 106 case GPIO_DDC_LINE_DDC1: 107 info->offset = REG(DC_I3C0_DC_I3CPAD_CONTROL0); 108 break; 109 case GPIO_DDC_LINE_DDC2: 110 info->offset = REG(DC_I3C1_DC_I3CPAD_CONTROL0); 111 break; 112 default: 113 ASSERT_CRITICAL(false); 114 result = false; 115 } 116 break; 117 case GPIO_ID_HPD: 118 switch (en) { 119 case GPIO_HPD_1: 120 info->offset = REG(HPD0_DC_HPD_INT_STATUS); 121 info->mask = HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK; 122 break; 123 case GPIO_HPD_2: 124 info->offset = REG(HPD1_DC_HPD_INT_STATUS); 125 info->mask = HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK; 126 break; 127 case GPIO_HPD_3: 128 info->offset = REG(HPD2_DC_HPD_INT_STATUS); 129 info->mask = HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK; 130 break; 131 case GPIO_HPD_4: 132 info->offset = REG(HPD3_DC_HPD_INT_STATUS); 133 info->mask = HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK; 134 break; 135 default: 136 ASSERT_CRITICAL(false); 137 result = false; 138 } 139 break; 140 default: 141 ASSERT_CRITICAL(false); 142 result = false; 143 } 144 145 return result; 146 } 147 148 /* function table */ 149 static const struct hw_translate_funcs funcs = { 150 .offset_to_id = dcn60_offset_to_id, 151 .id_to_offset = dcn60_id_to_offset, 152 }; 153 154 /* 155 * dal_hw_translate_dcn60_init 156 * 157 * @brief 158 * Initialize Hw translate function pointers. 159 * 160 * @param 161 * struct hw_translate *tr - [out] struct of function pointers 162 * 163 */ 164 void dal_hw_translate_dcn60_init(struct hw_translate *tr) 165 { 166 tr->funcs = &funcs; 167 } 168 169