xref: /linux/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright 2023 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #ifndef __DCN35_DWB_H
28 #define __DCN35_DWB_H
29 
30 #include "resource.h"
31 #include "dwb.h"
32 #include "dcn30/dcn30_dwb.h"
33 
34 #define DWBC_COMMON_MASK_SH_LIST_DCN35(mask_sh) \
35 	DWBC_COMMON_MASK_SH_LIST_DCN30(mask_sh), \
36 	SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_FGCG_REP_DIS, mask_sh)
37 
38 #define DWBC_REG_FIELD_LIST_DCN3_5(type)          \
39 	struct {                                  \
40 		DWBC_REG_FIELD_LIST_DCN3_0(type); \
41 		type DWB_FGCG_REP_DIS;            \
42 	}
43 
44 struct dcn35_dwbc_mask {
45 	DWBC_REG_FIELD_LIST_DCN3_5(uint32_t);
46 };
47 
48 struct dcn35_dwbc_shift {
49 	DWBC_REG_FIELD_LIST_DCN3_5(uint8_t);
50 };
51 
52 void dcn35_dwbc_construct(struct dcn30_dwbc *dwbc30,
53 	struct dc_context *ctx,
54 	const struct dcn30_dwbc_registers *dwbc_regs,
55 	const struct dcn35_dwbc_shift *dwbc_shift,
56 	const struct dcn35_dwbc_mask *dwbc_mask,
57 	int inst);
58 
59 void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable);
60 
61 #endif
62