1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. 5 */ 6 7 #ifndef __DCN50_DPP_H__ 8 #define __DCN50_DPP_H__ 9 10 #include "dcn20/dcn20_dpp.h" 11 #include "dcn30/dcn30_dpp.h" 12 #include "dcn32/dcn32_dpp.h" 13 #include "dcn401/dcn401_dpp.h" 14 15 16 #define TO_DCN50_DPP(dpp)\ 17 container_of(dpp, struct dcn50_dpp, base) 18 19 #define DPP_REG_LIST_SH_MASK_DCN50_COMMON(mask_sh)\ 20 DPP_REG_LIST_SH_MASK_DCN401_COMMON(mask_sh), \ 21 TF_SF(CNVC_CFG0_PRE_GAM, PRE_GAM_MODE, mask_sh), \ 22 TF_SF(CNVC_CFG0_PRE_GAM, PRE_DEGAM_SELECT, mask_sh), \ 23 TF_SF(CNVC_CFG0_PRE_GAM, PRE_REGAM_SELECT, mask_sh) 24 25 #define DPP_REG_FIELD_LIST_DCN50(type) \ 26 DPP_REG_FIELD_LIST_DCN401(type); \ 27 type PRE_GAM_MODE; \ 28 type PRE_REGAM_SELECT 29 30 #define DPP_REG_VARIABLE_LIST_DCN50 \ 31 DPP_REG_VARIABLE_LIST_DCN401; \ 32 uint32_t PRE_GAM; 33 34 struct dcn50_dpp_registers { 35 DPP_REG_VARIABLE_LIST_DCN50 36 }; 37 38 struct dcn50_dpp_shift { 39 DPP_REG_FIELD_LIST_DCN50(uint8_t); 40 }; 41 42 struct dcn50_dpp_mask { 43 DPP_REG_FIELD_LIST_DCN50(uint32_t); 44 }; 45 46 struct dcn50_dpp { 47 struct dpp base; 48 49 const struct dcn50_dpp_registers *tf_regs; 50 const struct dcn50_dpp_shift *tf_shift; 51 const struct dcn50_dpp_mask *tf_mask; 52 53 const uint16_t *filter_v; 54 const uint16_t *filter_h; 55 const uint16_t *filter_v_c; 56 const uint16_t *filter_h_c; 57 int lb_pixel_depth_supported; 58 int lb_memory_size; 59 int lb_bits_per_entry; 60 bool is_write_to_ram_a_safe; 61 struct scaler_data scl_data; 62 struct pwl_params pwl_data; 63 }; 64 65 bool dpp50_construct( 66 struct dcn50_dpp *dpp50, 67 struct dc_context *ctx, 68 uint32_t inst, 69 const struct dcn50_dpp_registers *tf_regs, 70 const struct dcn50_dpp_shift *tf_shift, 71 const struct dcn50_dpp_mask *tf_mask); 72 73 void dpp50_dpp_setup( 74 struct dpp *dpp_base, 75 enum surface_pixel_format format, 76 enum expansion_mode mode, 77 struct dc_csc_transform input_csc_color_matrix, 78 enum dc_color_space input_color_space, 79 struct cnv_alpha_2bit_lut *alpha_2bit_lut); 80 81 void dpp50_set_pregam_state( 82 struct dpp *dpp_base, 83 enum dc_transfer_func_predefined tr, 84 enum dc_scaling_linearity scaling); 85 86 #endif /* __DCN50_DPP_H__ */ 87