1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 6 #ifndef _DML21_WRAPPER_H_ 7 #define _DML21_WRAPPER_H_ 8 9 #include "os_types.h" 10 #include "dml_top_soc_parameter_types.h" 11 #include "dml_top_display_cfg_types.h" 12 13 struct dc; 14 struct dc_state; 15 struct dml2_configuration_options; 16 struct dml2_context; 17 enum dc_validate_mode; 18 19 /** 20 * dml21_create - Creates dml21_context. 21 * @in_dc: dc. 22 * @dml_ctx: Created dml21 context. 23 * @config: dml21 configuration options. 24 * 25 * Create of DML21 is done as part of dc_state creation. 26 * DML21 IP, SOC and STATES are initialized at 27 * creation time. 28 * 29 * Return: True if dml2 is successfully created, false otherwise. 30 */ 31 bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config); 32 void dml21_destroy(struct dml2_context *dml2); 33 void dml21_copy(struct dml2_context *dst_dml_ctx, 34 struct dml2_context *src_dml_ctx); 35 bool dml21_create_copy(struct dml2_context **dst_dml_ctx, 36 struct dml2_context *src_dml_ctx); 37 38 /* Structure for inputting external SOCBB and DCNIP values for tool based debugging. */ 39 struct socbb_ip_params_external { 40 struct dml2_ip_capabilities ip_params; 41 struct dml2_soc_bb soc_bb; 42 }; 43 44 /*mcache parameters decided by dml*/ 45 struct dc_mcache_params { 46 bool valid; 47 /* 48 * For iMALL, dedicated mall mcaches are required (sharing of last 49 * slice possible), for legacy phantom or phantom without return 50 * the only mall mcaches need to be valid. 51 */ 52 bool requires_dedicated_mall_mcache; 53 unsigned int num_mcaches_plane0; 54 unsigned int num_mcaches_plane1; 55 /* 56 * Generally, plane0/1 slices must use a disjoint set of caches 57 * but in some cases the final segement of the two planes can 58 * use the same cache. If plane0_plane1 is set, then this is 59 * allowed. 60 * 61 * Similarly, the caches allocated to MALL prefetcher are generally 62 * disjoint, but if mall_prefetch is set, then the final segment 63 * between the main and the mall pixel requestor can use the same 64 * cache. 65 * 66 * Note that both bits may be set at the same time. 67 */ 68 struct { 69 bool mall_comb_mcache_p0; 70 bool mall_comb_mcache_p1; 71 bool plane0_plane1; 72 } last_slice_sharing; 73 /* 74 * A plane is divided into vertical slices of mcaches, 75 * which wrap on the surface width. 76 * 77 * For example, if the surface width is 7680, and split into 78 * three slices of equal width, the boundary array would contain 79 * [2560, 5120, 7680] 80 * 81 * The assignments are 82 * 0 = [0 .. 2559] 83 * 1 = [2560 .. 5119] 84 * 2 = [5120 .. 7679] 85 * 0 = [7680 .. INF] 86 * The final element implicitly is the same as the first, and 87 * at first seems invalid since it is never referenced (since) 88 * it is outside the surface. However, its useful when shifting 89 * (see below). 90 * 91 * For any given valid mcache assignment, a shifted version, wrapped 92 * on the surface width boundary is also assumed to be valid. 93 * 94 * For example, shifting [2560, 5120, 7680] by -50 results in 95 * [2510, 5170, 7630]. 96 * 97 * The assignments are now: 98 * 0 = [0 .. 2509] 99 * 1 = [2510 .. 5169] 100 * 2 = [5170 .. 7629] 101 * 0 = [7630 .. INF] 102 */ 103 int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1]; 104 int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1]; 105 }; 106 #endif 107