1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DML1_FRL_CAP_CHK_H__ 28 #define __DML1_FRL_CAP_CHK_H__ 29 30 #include "os_types.h" 31 32 #define TB_BORROWED_MAX 400 33 #define C_FRL_CB 510 34 #define TOLERANCE_FRL_BIT 300 /* ppm */ 35 #define ACR_RATE_MAX 1500 36 37 enum hdmi_frl_pixel_encoding { 38 HDMI_FRL_PIXEL_ENCODING_444, 39 HDMI_FRL_PIXEL_ENCODING_422, 40 HDMI_FRL_PIXEL_ENCODING_420 41 }; 42 43 enum frl_cap_chk_result { 44 FRL_CAP_CHK_OK = 0, 45 46 FRL_CAP_CHK_ERROR_AUDIO_BW = -1, 47 FRL_CAP_CHK_ERROR_BORROW = -2, 48 FRL_CAP_CHK_ERROR_MAX_BORROW = -3, 49 FRL_CAP_CHK_ERROR_MARGIN = -4, 50 51 FRL_CAP_CHK_ERROR_UNSUPPORTED_AUDIO = -1000 52 }; 53 54 enum frl_borrow_mode { 55 FRL_BORROW_MODE_NONE, 56 FRL_BORROW_MODE_FROM_ACTIVE, 57 FRL_BORROW_MODE_FROM_BLANK 58 }; 59 60 enum frl_link_rate { 61 FRL_LINK_RATE_DISABLE = 0, 62 FRL_LINK_RATE_3GBPS, 63 FRL_LINK_RATE_6GBPS, 64 FRL_LINK_RATE_6GBPS_4LANE, 65 FRL_LINK_RATE_8GBPS, 66 FRL_LINK_RATE_10GBPS, 67 FRL_LINK_RATE_12GBPS, 68 FRL_LINK_RATE_16GBPS, 69 FRL_LINK_RATE_20GBPS, 70 FRL_LINK_RATE_24GBPS 71 }; 72 73 struct frl_dml_borrow_params { 74 int audio_packets_line; 75 int hc_active_target; 76 int hc_blank_target; 77 enum frl_borrow_mode borrow_mode; 78 }; 79 80 struct frl_primary_format { 81 uint32_t vic; 82 uint32_t frl_rate; 83 uint32_t frl_lanes; 84 uint32_t hc_active; 85 uint32_t hc_blank; 86 }; 87 88 struct frl_cap_chk_intermediates { 89 int c_frl_sb; 90 double overhead_sb; 91 double overhead_rs; 92 double overhead_map; 93 double overhead_min; 94 double overhead_max; 95 double f_pixel_clock_max; 96 double t_line; 97 double r_bit_min; 98 double r_frl_char_min; 99 double c_frl_line; 100 double ap; 101 double r_ap; 102 double avg_audio_packets_line; 103 int audio_packets_line; 104 int blank_audio_min; 105 }; 106 107 struct frl_cap_chk_params { 108 int lanes; 109 double f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ 110 double r_bit_nominal; /* FRL bitrate (bps) */ 111 int audio_packet_type; 112 double f_audio; /* Audio rate (Hz) */ 113 int h_active; /* Active pixels per line */ 114 int h_blank; /* Blanking pixels per line */ 115 int bpc; /* Bits per component */ 116 int vic; /* Video Identification Code */ 117 118 enum hdmi_frl_pixel_encoding pixel_encoding; 119 120 bool compressed; /* set to true if DSC is enabled */ 121 bool bypass_hc_target_calc; /* debug only */ 122 bool allow_all_bpp; /* dsc_all_bpp */ 123 124 /* DSC parameters */ 125 int slices; 126 int slice_width; 127 double bpp_target; 128 bool is_ovt; 129 int layout; 130 int acat; /* not supported */ 131 132 /* outputs */ 133 struct frl_dml_borrow_params borrow_params; 134 int average_tribyte_rate; 135 }; 136 137 enum frl_cap_chk_result dml1_frl_cap_chk(struct frl_cap_chk_params *params); 138 139 enum frl_cap_chk_result dml1_frl_cap_chk_inter(struct frl_cap_chk_params *params, 140 struct frl_cap_chk_intermediates *inter); 141 142 enum frl_cap_chk_result dml1_frl_cap_chk_common(struct frl_cap_chk_intermediates *inter, 143 struct frl_cap_chk_params *params); 144 145 enum frl_cap_chk_result dml1_frl_cap_chk_uncompressed(struct frl_cap_chk_params *params, 146 struct frl_cap_chk_intermediates *inter); 147 148 enum frl_cap_chk_result dml1_frl_cap_chk_compressed(struct frl_cap_chk_params *params, 149 struct frl_cap_chk_intermediates *inter); 150 #endif 151 152 void frl_modified_pix_clock_for_dsc_padding(const int hc_active_target, 153 const int hc_blank_target, 154 const uint8_t frl_num_lanes, 155 const uint32_t pix_clk_100hz, 156 const int frl_link_rate, 157 const uint32_t h_addressable, 158 const uint32_t h_border_left, 159 const uint32_t h_border_right, 160 const uint32_t h_total, 161 const uint32_t h_addressable_otg, 162 uint32_t *pix_clk_100hz_otg, 163 uint32_t *h_total_otg); 164 165 int frl_modify_borrow_mode_for_dsc_padding(const uint32_t pix_clk_100hz, 166 const uint32_t h_active, 167 const uint32_t h_active_padded, 168 const uint32_t h_blank, 169 const uint32_t h_blank_padded, 170 const int hc_active, 171 const int hc_blank, 172 const uint8_t frl_num_lanes, 173 const int frl_link_rate); 174