1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef __AMDGPU_DM_PP_SMU_H__ 7 #define __AMDGPU_DM_PP_SMU_H__ 8 9 #include "dm_pp_interface.h" 10 11 struct amd_pp_display_configuration; 12 struct pp_smu_wm_range_sets; 13 struct dm_pp_wm_sets_with_clock_ranges_soc15; 14 struct amdgpu_device; 15 16 int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev); 17 18 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 19 void build_pm_display_cfg(struct amd_pp_display_configuration *pm_display_cfg, 20 const struct dm_pp_display_configuration *pp_display_cfg); 21 void build_wm_clock_ranges_soc15(const struct pp_smu_wm_range_sets *ranges, 22 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); 23 void get_default_clock_levels(enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels *clks); 24 enum amd_pp_clock_type dc_to_pp_clock_type(enum dm_pp_clock_type dm_pp_clk_type); 25 void pp_to_dc_clock_levels(const struct amd_pp_clocks *pp_clks, 26 struct dm_pp_clock_levels *dc_clks, 27 enum dm_pp_clock_type dc_clk_type); 28 void pp_to_dc_clock_levels_with_latency(const struct pp_clock_levels_with_latency *pp_clks, 29 struct dm_pp_clock_levels_with_latency *clk_level_info, 30 enum dm_pp_clock_type dc_clk_type); 31 void pp_to_dc_clock_levels_with_voltage(const struct pp_clock_levels_with_voltage *pp_clks, 32 struct dm_pp_clock_levels_with_voltage *clk_level_info, 33 enum dm_pp_clock_type dc_clk_type); 34 void cap_clock_levels_to_validation(struct dm_pp_clock_levels *dc_clks, 35 enum dm_pp_clock_type clk_type, 36 const struct amd_pp_simple_clock_info *validation_clks); 37 bool pp_smu_nv_clock_id_to_pp(enum pp_smu_nv_clock_id clock_id, 38 enum amd_pp_clock_type *clock_type); 39 void pp_rv_set_wm_ranges(struct pp_smu *pp, struct pp_smu_wm_range_sets *ranges); 40 void pp_rv_set_pme_wa_enable(struct pp_smu *pp); 41 void pp_rv_set_active_display_count(struct pp_smu *pp, int count); 42 void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock); 43 void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock); 44 void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz); 45 enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, 46 struct pp_smu_wm_range_sets *ranges); 47 enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count); 48 enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz); 49 enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int mhz); 50 enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz); 51 enum pp_smu_status pp_nv_set_pstate_handshake_support(struct pp_smu *pp, 52 bool pstate_handshake_supported); 53 enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, 54 enum pp_smu_nv_clock_id clock_id, int mhz); 55 enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(struct pp_smu *pp, 56 struct pp_smu_nv_clock_table *max_clocks); 57 enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, 58 unsigned int *clock_values_in_khz, 59 unsigned int *num_states); 60 enum pp_smu_status pp_rn_get_dpm_clock_table(struct pp_smu *pp, 61 struct dpm_clocks *clock_table); 62 #endif 63 64 #endif /* __AMDGPU_DM_PP_SMU_H__ */ 65