1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef __AMDGPU_DM_HELPERS_H__ 7 #define __AMDGPU_DM_HELPERS_H__ 8 9 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 10 #include <drm/drm_edid.h> 11 12 struct amdgpu_dm_connector; 13 struct dc_link; 14 struct dc_context; 15 struct dc_stream_state; 16 struct dc_edid_caps; 17 struct dc_dp_mst_stream_allocation_table; 18 struct drm_dp_aux; 19 struct drm_dp_mst_atomic_payload; 20 struct drm_dp_mst_topology_mgr; 21 struct drm_dp_mst_topology_state; 22 23 /* Exported for KUnit testing */ 24 u32 edid_extract_panel_id(struct edid *edid); 25 void apply_edid_quirks(struct dc_link *link, struct edid *edid, 26 struct dc_edid_caps *edid_caps); 27 uint8_t get_max_frl_rate(uint8_t max_lanes, uint8_t max_rate_per_lane); 28 uint8_t get_dsc_max_slices(uint8_t max_slices, int clk_per_slice); 29 bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id); 30 extern const uint32_t dm_freesync_pcon_whitelist[]; 31 uint32_t dm_freesync_pcon_whitelist_count(void); 32 void fill_dc_mst_payload_table_from_drm(struct dc_link *link, 33 bool enable, 34 struct drm_dp_mst_atomic_payload *target_payload, 35 struct dc_dp_mst_stream_allocation_table *table); 36 void dm_helpers_construct_old_payload(struct drm_dp_mst_topology_mgr *mgr, 37 struct drm_dp_mst_topology_state *mst_state, 38 struct drm_dp_mst_atomic_payload *new_payload, 39 struct drm_dp_mst_atomic_payload *old_payload); 40 bool dm_helpers_dp_write_dsc_enable(struct dc_context *ctx, 41 const struct dc_stream_state *stream, 42 bool enable); 43 uint dm_helpers_get_dc_debug_mask(void); 44 void dm_helpers_set_dc_debug_mask(uint debug_mask); 45 int dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len); 46 const struct drm_edid *dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector); 47 const struct drm_edid *dm_helpers_read_vbios_hardcoded_edid(struct dc_link *link, 48 struct amdgpu_dm_connector *aconnector); 49 bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 50 bool is_write_cmd, 51 unsigned char cmd, 52 unsigned int length, 53 unsigned int offset, 54 unsigned char *data); 55 void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux); 56 uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(struct drm_dp_aux *aux, 57 const struct dc_stream_state *stream, 58 bool enable); 59 #endif /* CONFIG_DRM_AMD_DC_KUNIT_TEST */ 60 61 #endif /* __AMDGPU_DM_HELPERS_H__ */ 62