1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef AMDGPU_DM_AMDGPU_DM_DMUB_H_ 28 #define AMDGPU_DM_AMDGPU_DM_DMUB_H_ 29 30 #include "amdgpu.h" 31 32 void dm_dmub_aux_setconfig_callback(struct amdgpu_device *adev, 33 struct dmub_notification *notify); 34 void dm_dmub_aux_fused_io_callback(struct amdgpu_device *adev, 35 struct dmub_notification *notify); 36 bool dm_register_dmub_notify_callback(struct amdgpu_device *adev, 37 enum dmub_notification_type type, 38 dmub_notify_interrupt_callback_t callback, 39 bool dmub_int_thread_offload); 40 int dm_dmub_hw_init(struct amdgpu_device *adev); 41 void dm_dmub_hw_resume(struct amdgpu_device *adev); 42 enum dmub_ips_disable_type dm_get_default_ips_mode(struct amdgpu_device *adev); 43 int dm_dmub_sw_init(struct amdgpu_device *adev); 44 int dm_init_microcode(struct amdgpu_device *adev); 45 46 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 47 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 48 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 49 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 50 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 51 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 52 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 53 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 54 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 55 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 56 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 57 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 58 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 59 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" 60 #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" 61 #define FIRMWARE_DCN_36_DMUB "amdgpu/dcn_3_6_dmcub.bin" 62 #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" 63 #define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin" 64 #define FIRMWARE_DCN_42B_DMUB "amdgpu/dcn_4_2_1_dmcub.bin" 65 #define FIRMWARE_DCN_60_DMUB "amdgpu/dcn_6_0_0_dmcub.bin" 66 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 67 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 68 69 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 70 struct dc_context; 71 struct dmub_cmd_fused_request; 72 73 void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev); 74 void abort_fused_io(struct dc_context *ctx, 75 const struct dmub_cmd_fused_request *request); 76 #endif 77 78 #endif /* AMDGPU_DM_AMDGPU_DM_DMUB_H_ */ 79