1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_CONNECTOR_H__ 28 #define __AMDGPU_DM_CONNECTOR_H__ 29 30 struct amdgpu_device; 31 struct amdgpu_dm_connector; 32 struct amdgpu_display_manager; 33 struct amdgpu_encoder; 34 struct amdgpu_i2c_adapter; 35 struct dc_crtc_timing; 36 struct dc_link; 37 enum signal_type; 38 struct dc_state; 39 struct dc_stream_state; 40 struct ddc_service; 41 struct dm_connector_state; 42 struct drm_atomic_commit; 43 struct drm_device; 44 struct drm_encoder_helper_funcs; 45 struct drm_connector; 46 struct drm_connector_state; 47 struct drm_crtc; 48 struct drm_device; 49 struct drm_display_mode; 50 struct drm_edid; 51 struct drm_property; 52 53 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 54 55 struct drm_connector_state * 56 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 57 58 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 59 struct drm_connector_state *connector_state, 60 struct drm_property *property, 61 uint64_t val); 62 63 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 64 const struct drm_connector_state *state, 65 struct drm_property *property, 66 uint64_t *val); 67 68 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 69 struct amdgpu_dm_connector *aconnector, 70 int connector_type, 71 struct dc_link *link, 72 int link_index); 73 74 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 75 const struct drm_display_mode *mode); 76 77 void dm_restore_drm_connector_state(struct drm_device *dev, 78 struct drm_connector *connector); 79 80 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 81 const struct drm_edid *drm_edid, 82 bool do_mccs); 83 84 void amdgpu_dm_update_connector_after_detect( 85 struct amdgpu_dm_connector *aconnector); 86 87 void amdgpu_dm_hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 88 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 89 90 struct drm_connector * 91 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, 92 struct drm_crtc *crtc); 93 94 int amdgpu_dm_convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 95 96 struct dc_stream_state * 97 amdgpu_dm_create_validate_stream_for_sink(struct drm_connector *connector, 98 const struct drm_display_mode *drm_mode, 99 const struct dm_connector_state *dm_state, 100 const struct dc_stream_state *old_stream); 101 102 int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 103 struct amdgpu_dm_connector *amdgpu_dm_connector, 104 u32 link_index, 105 struct amdgpu_encoder *amdgpu_encoder); 106 107 void amdgpu_dm_s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend); 108 109 int amdgpu_dm_detect_mst_link_for_all_connectors(struct drm_device *dev); 110 111 void amdgpu_set_panel_orientation(struct drm_connector *connector); 112 113 enum dc_color_depth 114 amdgpu_dm_convert_color_depth_from_display_info(const struct drm_connector *connector, 115 bool is_y420, int requested_bpc); 116 117 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 118 const struct drm_display_mode *mode, 119 const struct dm_connector_state *dm_state, 120 struct dc_stream_state *stream); 121 122 bool amdgpu_dm_is_freesync_video_mode(const struct drm_display_mode *mode, 123 struct amdgpu_dm_connector *aconnector); 124 125 int amdgpu_dm_fill_hdr_info_packet(const struct drm_connector_state *state, 126 struct dc_info_packet *out); 127 128 enum dc_color_space 129 amdgpu_dm_get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 130 const struct drm_connector_state *connector_state); 131 132 struct drm_display_mode * 133 amdgpu_dm_get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 134 bool use_probed_modes); 135 136 struct amdgpu_i2c_adapter * 137 amdgpu_dm_create_i2c(struct ddc_service *ddc_service, bool oem); 138 139 #define DDC_MANUFACTURERNAME_SAMSUNG 0x2D4C 140 141 /* Encoder functions */ 142 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 143 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 144 int amdgpu_dm_encoder_init(struct drm_device *dev, 145 struct amdgpu_encoder *aencoder, 146 uint32_t link_index); 147 148 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 149 int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 150 struct i2c_msg *msgs, int num); 151 u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap); 152 void parse_edid_displayid_vrr(struct drm_connector *connector, 153 const struct edid *edid); 154 int get_amd_vsdb(struct amdgpu_dm_connector *aconnector, 155 struct amdgpu_hdmi_vsdb_info *vsdb_info); 156 int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 157 const struct edid *edid, 158 struct amdgpu_hdmi_vsdb_info *vsdb_info); 159 void amdgpu_dm_connector_funcs_force(struct drm_connector *connector); 160 enum dc_status dm_validate_stream_and_context(struct dc *dc, 161 struct dc_stream_state *stream); 162 struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector); 163 void amdgpu_dm_get_native_mode(struct drm_connector *connector); 164 struct drm_display_mode *amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 165 const char *name, 166 int hdisplay, int vdisplay); 167 void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 168 struct drm_connector *connector); 169 void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 170 const struct drm_edid *drm_edid); 171 uint add_fs_modes(struct amdgpu_dm_connector *aconnector); 172 void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 173 const struct drm_edid *drm_edid); 174 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 175 void create_eml_sink(struct amdgpu_dm_connector *aconnector); 176 void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector); 177 void dm_encoder_helper_disable(struct drm_encoder *encoder); 178 int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 179 struct drm_crtc_state *crtc_state, 180 struct drm_connector_state *conn_state); 181 enum drm_mode_subconnector get_subconnector_type(struct dc_link *link); 182 void update_subconnector_property(struct amdgpu_dm_connector *aconnector); 183 void amdgpu_dm_fbc_init(struct drm_connector *connector); 184 void amdgpu_dm_set_panel_type(struct amdgpu_dm_connector *aconnector); 185 void amdgpu_dm_update_cacp_caps(struct amdgpu_dm_connector *aconnector); 186 void fill_stream_properties_from_drm_display_mode( 187 struct dc_stream_state *stream, 188 const struct drm_display_mode *mode_in, 189 const struct drm_connector *connector, 190 const struct drm_connector_state *connector_state, 191 const struct dc_stream_state *old_stream, 192 int requested_bpc, 193 enum dc_pixel_encoding requested_encoding, 194 bool is_hdmi_ep); 195 struct dc_stream_state * 196 create_stream_for_sink(struct drm_connector *connector, 197 const struct drm_display_mode *drm_mode, 198 const struct dm_connector_state *dm_state, 199 const struct dc_stream_state *old_stream, 200 int requested_bpc, 201 enum dc_pixel_encoding requested_encoding, 202 bool is_hdmi_ep); 203 enum drm_connector_status 204 amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force); 205 enum drm_connector_status 206 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force); 207 void amdgpu_dm_connector_unregister(struct drm_connector *connector); 208 int amdgpu_dm_connector_late_register(struct drm_connector *connector); 209 void amdgpu_dm_connector_destroy(struct drm_connector *connector); 210 enum display_content_type 211 get_output_content_type(const struct drm_connector_state *connector_state); 212 bool adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 213 const struct drm_display_info *info); 214 215 int to_drm_connector_type(enum signal_type st, uint32_t connector_id); 216 bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, struct drm_display_mode *mode); 217 enum dc_aspect_ratio get_aspect_ratio(const struct drm_display_mode *mode_in); 218 void copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 219 struct drm_display_mode *dst_mode); 220 void decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 221 const struct drm_display_mode *native_mode, 222 bool scale_enabled); 223 void amdgpu_dm_set_panel_type(struct amdgpu_dm_connector *aconnector); 224 void amdgpu_dm_update_cacp_caps(struct amdgpu_dm_connector *aconnector); 225 #endif 226 #endif /* __AMDGPU_DM_CONNECTOR_H__ */ 227