1297b0cebSHawking Zhang /* 2297b0cebSHawking Zhang * Copyright 2025 Advanced Micro Devices, Inc. 3297b0cebSHawking Zhang * 4297b0cebSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5297b0cebSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6297b0cebSHawking Zhang * to deal in the Software without restriction, including without limitation 7297b0cebSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8297b0cebSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9297b0cebSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10297b0cebSHawking Zhang * 11297b0cebSHawking Zhang * The above copyright notice and this permission notice shall be included in 12297b0cebSHawking Zhang * all copies or substantial portions of the Software. 13297b0cebSHawking Zhang * 14297b0cebSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15297b0cebSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16297b0cebSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17297b0cebSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18297b0cebSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19297b0cebSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20297b0cebSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21297b0cebSHawking Zhang * 22297b0cebSHawking Zhang */ 23297b0cebSHawking Zhang #ifndef __SOC_V1_0_H__ 24297b0cebSHawking Zhang #define __SOC_V1_0_H__ 25297b0cebSHawking Zhang 26297b0cebSHawking Zhang extern const struct amdgpu_ip_block_version soc_v1_0_common_ip_block; 27297b0cebSHawking Zhang 28297b0cebSHawking Zhang void soc_v1_0_grbm_select(struct amdgpu_device *adev, 29297b0cebSHawking Zhang u32 me, u32 pipe, 30297b0cebSHawking Zhang u32 queue, u32 vmid, 31297b0cebSHawking Zhang int xcc_id); 32fe1c48e9SLikun Gao int soc_v1_0_init_soc_config(struct amdgpu_device *adev); 33fcc4fc75SLikun Gao bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg); 34fcc4fc75SLikun Gao uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg); 35*21677982SLe Ma u64 soc_v1_0_encode_ext_smn_addressing(int ext_id); 36297b0cebSHawking Zhang 37297b0cebSHawking Zhang #endif 38