1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v15_0.h" 30 31 #include "mp/mp_15_0_0_offset.h" 32 #include "mp/mp_15_0_0_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin"); 35 MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta.bin"); 36 37 static int psp_v15_0_0_init_microcode(struct psp_context *psp) 38 { 39 struct amdgpu_device *adev = psp->adev; 40 char ucode_prefix[30]; 41 int err = 0; 42 43 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 44 45 err = psp_init_toc_microcode(psp, ucode_prefix); 46 if (err) 47 return err; 48 49 err = psp_init_ta_microcode(psp, ucode_prefix); 50 if (err) 51 return err; 52 53 return 0; 54 } 55 56 static int psp_v15_0_0_ring_stop(struct psp_context *psp, 57 enum psp_ring_type ring_type) 58 { 59 int ret = 0; 60 struct amdgpu_device *adev = psp->adev; 61 62 if (amdgpu_sriov_vf(adev)) { 63 /* Write the ring destroy command*/ 64 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 65 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 66 /* there might be handshake issue with hardware which needs delay */ 67 mdelay(20); 68 /* Wait for response flag (bit 31) */ 69 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 70 0x80000000, 0x80000000, false); 71 } else { 72 /* Write the ring destroy command*/ 73 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, 74 GFX_CTRL_CMD_ID_DESTROY_RINGS); 75 /* there might be handshake issue with hardware which needs delay */ 76 mdelay(20); 77 /* Wait for response flag (bit 31) */ 78 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 79 0x80000000, 0x80000000, false); 80 } 81 82 return ret; 83 } 84 85 static int psp_v15_0_0_ring_create(struct psp_context *psp, 86 enum psp_ring_type ring_type) 87 { 88 int ret = 0; 89 unsigned int psp_ring_reg = 0; 90 struct psp_ring *ring = &psp->km_ring; 91 struct amdgpu_device *adev = psp->adev; 92 93 if (amdgpu_sriov_vf(adev)) { 94 ret = psp_v15_0_0_ring_stop(psp, ring_type); 95 if (ret) { 96 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); 97 return ret; 98 } 99 100 /* Write low address of the ring to C2PMSG_102 */ 101 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 102 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); 103 /* Write high address of the ring to C2PMSG_103 */ 104 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 105 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); 106 107 /* Write the ring initialization command to C2PMSG_101 */ 108 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 109 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 110 111 /* there might be handshake issue with hardware which needs delay */ 112 mdelay(20); 113 114 /* Wait for response flag (bit 31) in C2PMSG_101 */ 115 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 116 0x80000000, 0x8000FFFF, false); 117 118 } else { 119 /* Wait for sOS ready for ring creation */ 120 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 121 0x80000000, 0x80000000, false); 122 if (ret) { 123 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 124 return ret; 125 } 126 127 /* Write low address of the ring to C2PMSG_69 */ 128 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 129 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg); 130 /* Write high address of the ring to C2PMSG_70 */ 131 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 132 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg); 133 /* Write size of ring to C2PMSG_71 */ 134 psp_ring_reg = ring->ring_size; 135 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg); 136 /* Write the ring initialization command to C2PMSG_64 */ 137 psp_ring_reg = ring_type; 138 psp_ring_reg = psp_ring_reg << 16; 139 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg); 140 141 /* there might be handshake issue with hardware which needs delay */ 142 mdelay(20); 143 144 /* Wait for response flag (bit 31) in C2PMSG_64 */ 145 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 146 0x80000000, 0x8000FFFF, false); 147 } 148 149 return ret; 150 } 151 152 static int psp_v15_0_0_ring_destroy(struct psp_context *psp, 153 enum psp_ring_type ring_type) 154 { 155 int ret = 0; 156 struct psp_ring *ring = &psp->km_ring; 157 struct amdgpu_device *adev = psp->adev; 158 159 ret = psp_v15_0_0_ring_stop(psp, ring_type); 160 if (ret) 161 DRM_ERROR("Fail to stop psp ring\n"); 162 163 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 164 &ring->ring_mem_mc_addr, 165 (void **)&ring->ring_mem); 166 167 return ret; 168 } 169 170 static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp) 171 { 172 uint32_t data; 173 struct amdgpu_device *adev = psp->adev; 174 175 if (amdgpu_sriov_vf(adev)) 176 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 177 else 178 data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67); 179 180 return data; 181 } 182 183 static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 184 { 185 struct amdgpu_device *adev = psp->adev; 186 187 if (amdgpu_sriov_vf(adev)) { 188 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); 189 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 190 GFX_CTRL_CMD_ID_CONSUME_CMD); 191 } else 192 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value); 193 } 194 195 static const struct psp_funcs psp_v15_0_0_funcs = { 196 .init_microcode = psp_v15_0_0_init_microcode, 197 .ring_create = psp_v15_0_0_ring_create, 198 .ring_stop = psp_v15_0_0_ring_stop, 199 .ring_destroy = psp_v15_0_0_ring_destroy, 200 .ring_get_wptr = psp_v15_0_0_ring_get_wptr, 201 .ring_set_wptr = psp_v15_0_0_ring_set_wptr, 202 }; 203 204 void psp_v15_0_0_set_psp_funcs(struct psp_context *psp) 205 { 206 psp->funcs = &psp_v15_0_0_funcs; 207 } 208