1 /*
2 * Copyright 2025 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v15_0.h"
30
31 #include "mp/mp_15_0_0_offset.h"
32 #include "mp/mp_15_0_0_sh_mask.h"
33
34 MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin");
35
psp_v15_0_0_init_microcode(struct psp_context * psp)36 static int psp_v15_0_0_init_microcode(struct psp_context *psp)
37 {
38 struct amdgpu_device *adev = psp->adev;
39 char ucode_prefix[30];
40 int err = 0;
41
42 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
43
44 err = psp_init_toc_microcode(psp, ucode_prefix);
45 if (err)
46 return err;
47
48 err = psp_init_ta_microcode(psp, ucode_prefix);
49 if (err)
50 return err;
51
52 return 0;
53 }
54
psp_v15_0_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)55 static int psp_v15_0_0_ring_stop(struct psp_context *psp,
56 enum psp_ring_type ring_type)
57 {
58 int ret = 0;
59 struct amdgpu_device *adev = psp->adev;
60
61 if (amdgpu_sriov_vf(adev)) {
62 /* Write the ring destroy command*/
63 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
64 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
65 /* there might be handshake issue with hardware which needs delay */
66 mdelay(20);
67 /* Wait for response flag (bit 31) */
68 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
69 0x80000000, 0x80000000, false);
70 } else {
71 /* Write the ring destroy command*/
72 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
73 GFX_CTRL_CMD_ID_DESTROY_RINGS);
74 /* there might be handshake issue with hardware which needs delay */
75 mdelay(20);
76 /* Wait for response flag (bit 31) */
77 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
78 0x80000000, 0x80000000, false);
79 }
80
81 return ret;
82 }
83
psp_v15_0_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)84 static int psp_v15_0_0_ring_create(struct psp_context *psp,
85 enum psp_ring_type ring_type)
86 {
87 int ret = 0;
88 unsigned int psp_ring_reg = 0;
89 struct psp_ring *ring = &psp->km_ring;
90 struct amdgpu_device *adev = psp->adev;
91
92 if (amdgpu_sriov_vf(adev)) {
93 ret = psp_v15_0_0_ring_stop(psp, ring_type);
94 if (ret) {
95 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
96 return ret;
97 }
98
99 /* Write low address of the ring to C2PMSG_102 */
100 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
101 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
102 /* Write high address of the ring to C2PMSG_103 */
103 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
104 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
105
106 /* Write the ring initialization command to C2PMSG_101 */
107 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
108 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
109
110 /* there might be handshake issue with hardware which needs delay */
111 mdelay(20);
112
113 /* Wait for response flag (bit 31) in C2PMSG_101 */
114 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
115 0x80000000, 0x8000FFFF, false);
116
117 } else {
118 /* Wait for sOS ready for ring creation */
119 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
120 0x80000000, 0x80000000, false);
121 if (ret) {
122 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
123 return ret;
124 }
125
126 /* Write low address of the ring to C2PMSG_69 */
127 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
128 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
129 /* Write high address of the ring to C2PMSG_70 */
130 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
131 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
132 /* Write size of ring to C2PMSG_71 */
133 psp_ring_reg = ring->ring_size;
134 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
135 /* Write the ring initialization command to C2PMSG_64 */
136 psp_ring_reg = ring_type;
137 psp_ring_reg = psp_ring_reg << 16;
138 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
139
140 /* there might be handshake issue with hardware which needs delay */
141 mdelay(20);
142
143 /* Wait for response flag (bit 31) in C2PMSG_64 */
144 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
145 0x80000000, 0x8000FFFF, false);
146 }
147
148 return ret;
149 }
150
psp_v15_0_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)151 static int psp_v15_0_0_ring_destroy(struct psp_context *psp,
152 enum psp_ring_type ring_type)
153 {
154 int ret = 0;
155 struct psp_ring *ring = &psp->km_ring;
156 struct amdgpu_device *adev = psp->adev;
157
158 ret = psp_v15_0_0_ring_stop(psp, ring_type);
159 if (ret)
160 DRM_ERROR("Fail to stop psp ring\n");
161
162 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
163 &ring->ring_mem_mc_addr,
164 (void **)&ring->ring_mem);
165
166 return ret;
167 }
168
psp_v15_0_0_ring_get_wptr(struct psp_context * psp)169 static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp)
170 {
171 uint32_t data;
172 struct amdgpu_device *adev = psp->adev;
173
174 if (amdgpu_sriov_vf(adev))
175 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
176 else
177 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
178
179 return data;
180 }
181
psp_v15_0_0_ring_set_wptr(struct psp_context * psp,uint32_t value)182 static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
183 {
184 struct amdgpu_device *adev = psp->adev;
185
186 if (amdgpu_sriov_vf(adev)) {
187 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
188 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
189 GFX_CTRL_CMD_ID_CONSUME_CMD);
190 } else
191 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
192 }
193
194 static const struct psp_funcs psp_v15_0_0_funcs = {
195 .init_microcode = psp_v15_0_0_init_microcode,
196 .ring_create = psp_v15_0_0_ring_create,
197 .ring_stop = psp_v15_0_0_ring_stop,
198 .ring_destroy = psp_v15_0_0_ring_destroy,
199 .ring_get_wptr = psp_v15_0_0_ring_get_wptr,
200 .ring_set_wptr = psp_v15_0_0_ring_set_wptr,
201 };
202
psp_v15_0_0_set_psp_funcs(struct psp_context * psp)203 void psp_v15_0_0_set_psp_funcs(struct psp_context *psp)
204 {
205 psp->funcs = &psp_v15_0_0_funcs;
206 }
207