1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v15_0.h" 30 31 #include "mp/mp_15_0_0_offset.h" 32 #include "mp/mp_15_0_0_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin"); 35 MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc.bin"); 37 MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta.bin"); 38 39 static int psp_v15_0_0_init_microcode(struct psp_context *psp) 40 { 41 struct amdgpu_device *adev = psp->adev; 42 char ucode_prefix[30]; 43 int err = 0; 44 45 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 46 47 err = psp_init_toc_microcode(psp, ucode_prefix); 48 if (err) 49 return err; 50 51 err = psp_init_ta_microcode(psp, ucode_prefix); 52 if (err) 53 return err; 54 55 return 0; 56 } 57 58 static int psp_v15_0_0_ring_stop(struct psp_context *psp, 59 enum psp_ring_type ring_type) 60 { 61 int ret = 0; 62 struct amdgpu_device *adev = psp->adev; 63 64 if (amdgpu_sriov_vf(adev)) { 65 /* Write the ring destroy command*/ 66 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 67 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 68 /* there might be handshake issue with hardware which needs delay */ 69 mdelay(20); 70 /* Wait for response flag (bit 31) */ 71 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 72 0x80000000, 0x80000000, false); 73 } else { 74 /* Write the ring destroy command*/ 75 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, 76 GFX_CTRL_CMD_ID_DESTROY_RINGS); 77 /* there might be handshake issue with hardware which needs delay */ 78 mdelay(20); 79 /* Wait for response flag (bit 31) */ 80 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 81 0x80000000, 0x80000000, false); 82 } 83 84 return ret; 85 } 86 87 static int psp_v15_0_0_ring_create(struct psp_context *psp, 88 enum psp_ring_type ring_type) 89 { 90 int ret = 0; 91 unsigned int psp_ring_reg = 0; 92 struct psp_ring *ring = &psp->km_ring; 93 struct amdgpu_device *adev = psp->adev; 94 95 if (amdgpu_sriov_vf(adev)) { 96 ret = psp_v15_0_0_ring_stop(psp, ring_type); 97 if (ret) { 98 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); 99 return ret; 100 } 101 102 /* Write low address of the ring to C2PMSG_102 */ 103 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 104 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); 105 /* Write high address of the ring to C2PMSG_103 */ 106 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 107 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); 108 109 /* Write the ring initialization command to C2PMSG_101 */ 110 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 111 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 112 113 /* there might be handshake issue with hardware which needs delay */ 114 mdelay(20); 115 116 /* Wait for response flag (bit 31) in C2PMSG_101 */ 117 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 118 0x80000000, 0x8000FFFF, false); 119 120 } else { 121 /* Wait for sOS ready for ring creation */ 122 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 123 0x80000000, 0x80000000, false); 124 if (ret) { 125 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 126 return ret; 127 } 128 129 /* Write low address of the ring to C2PMSG_69 */ 130 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 131 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg); 132 /* Write high address of the ring to C2PMSG_70 */ 133 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 134 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg); 135 /* Write size of ring to C2PMSG_71 */ 136 psp_ring_reg = ring->ring_size; 137 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg); 138 /* Write the ring initialization command to C2PMSG_64 */ 139 psp_ring_reg = ring_type; 140 psp_ring_reg = psp_ring_reg << 16; 141 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg); 142 143 /* there might be handshake issue with hardware which needs delay */ 144 mdelay(20); 145 146 /* Wait for response flag (bit 31) in C2PMSG_64 */ 147 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 148 0x80000000, 0x8000FFFF, false); 149 } 150 151 return ret; 152 } 153 154 static int psp_v15_0_0_ring_destroy(struct psp_context *psp, 155 enum psp_ring_type ring_type) 156 { 157 int ret = 0; 158 struct psp_ring *ring = &psp->km_ring; 159 struct amdgpu_device *adev = psp->adev; 160 161 ret = psp_v15_0_0_ring_stop(psp, ring_type); 162 if (ret) 163 DRM_ERROR("Fail to stop psp ring\n"); 164 165 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 166 &ring->ring_mem_mc_addr, 167 (void **)&ring->ring_mem); 168 169 return ret; 170 } 171 172 static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp) 173 { 174 uint32_t data; 175 struct amdgpu_device *adev = psp->adev; 176 177 if (amdgpu_sriov_vf(adev)) 178 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 179 else 180 data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67); 181 182 return data; 183 } 184 185 static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 186 { 187 struct amdgpu_device *adev = psp->adev; 188 189 if (amdgpu_sriov_vf(adev)) { 190 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); 191 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 192 GFX_CTRL_CMD_ID_CONSUME_CMD); 193 } else 194 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value); 195 } 196 197 static const struct psp_funcs psp_v15_0_0_funcs = { 198 .init_microcode = psp_v15_0_0_init_microcode, 199 .ring_create = psp_v15_0_0_ring_create, 200 .ring_stop = psp_v15_0_0_ring_stop, 201 .ring_destroy = psp_v15_0_0_ring_destroy, 202 .ring_get_wptr = psp_v15_0_0_ring_get_wptr, 203 .ring_set_wptr = psp_v15_0_0_ring_set_wptr, 204 }; 205 206 void psp_v15_0_0_set_psp_funcs(struct psp_context *psp) 207 { 208 psp->funcs = &psp_v15_0_0_funcs; 209 } 210