1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros below represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 10): 162 return true; 163 case IP_VERSION(13, 0, 6): 164 case IP_VERSION(13, 0, 12): 165 case IP_VERSION(13, 0, 14): 166 return (adev->gmc.is_app_apu) ? false : true; 167 default: 168 return false; 169 } 170 } 171 172 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 173 struct amdgpu_ras_eeprom_control *control) 174 { 175 struct atom_context *atom_ctx = adev->mode_info.atom_context; 176 u8 i2c_addr; 177 178 if (!control) 179 return false; 180 181 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 182 /* The address given by VBIOS is an 8-bit, wire-format 183 * address, i.e. the most significant byte. 184 * 185 * Normalize it to a 19-bit EEPROM address. Remove the 186 * device type identifier and make it a 7-bit address; 187 * then make it a 19-bit EEPROM address. See top of 188 * amdgpu_eeprom.c. 189 */ 190 i2c_addr = (i2c_addr & 0x0F) >> 1; 191 control->i2c_address = ((u32) i2c_addr) << 16; 192 193 return true; 194 } 195 196 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 197 case IP_VERSION(11, 0, 2): 198 /* VEGA20 and ARCTURUS */ 199 if (adev->asic_type == CHIP_VEGA20) 200 control->i2c_address = EEPROM_I2C_MADDR_0; 201 else if (strnstr(atom_ctx->vbios_pn, 202 "D342", 203 sizeof(atom_ctx->vbios_pn))) 204 control->i2c_address = EEPROM_I2C_MADDR_0; 205 else 206 control->i2c_address = EEPROM_I2C_MADDR_4; 207 return true; 208 case IP_VERSION(11, 0, 7): 209 control->i2c_address = EEPROM_I2C_MADDR_0; 210 return true; 211 case IP_VERSION(13, 0, 2): 212 if (strnstr(atom_ctx->vbios_pn, "D673", 213 sizeof(atom_ctx->vbios_pn))) 214 control->i2c_address = EEPROM_I2C_MADDR_4; 215 else 216 control->i2c_address = EEPROM_I2C_MADDR_0; 217 return true; 218 case IP_VERSION(13, 0, 0): 219 if (strnstr(atom_ctx->vbios_pn, "D707", 220 sizeof(atom_ctx->vbios_pn))) 221 control->i2c_address = EEPROM_I2C_MADDR_0; 222 else 223 control->i2c_address = EEPROM_I2C_MADDR_4; 224 return true; 225 case IP_VERSION(13, 0, 6): 226 case IP_VERSION(13, 0, 10): 227 case IP_VERSION(13, 0, 12): 228 case IP_VERSION(13, 0, 14): 229 control->i2c_address = EEPROM_I2C_MADDR_4; 230 return true; 231 default: 232 return false; 233 } 234 } 235 236 static void 237 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 238 unsigned char *buf) 239 { 240 u32 *pp = (uint32_t *)buf; 241 242 pp[0] = cpu_to_le32(hdr->header); 243 pp[1] = cpu_to_le32(hdr->version); 244 pp[2] = cpu_to_le32(hdr->first_rec_offset); 245 pp[3] = cpu_to_le32(hdr->tbl_size); 246 pp[4] = cpu_to_le32(hdr->checksum); 247 } 248 249 static void 250 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 251 unsigned char *buf) 252 { 253 u32 *pp = (uint32_t *)buf; 254 255 hdr->header = le32_to_cpu(pp[0]); 256 hdr->version = le32_to_cpu(pp[1]); 257 hdr->first_rec_offset = le32_to_cpu(pp[2]); 258 hdr->tbl_size = le32_to_cpu(pp[3]); 259 hdr->checksum = le32_to_cpu(pp[4]); 260 } 261 262 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 263 { 264 u8 buf[RAS_TABLE_HEADER_SIZE]; 265 struct amdgpu_device *adev = to_amdgpu_device(control); 266 int res; 267 268 memset(buf, 0, sizeof(buf)); 269 __encode_table_header_to_buf(&control->tbl_hdr, buf); 270 271 /* i2c may be unstable in gpu reset */ 272 down_read(&adev->reset_domain->sem); 273 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 274 control->i2c_address + 275 control->ras_header_offset, 276 buf, RAS_TABLE_HEADER_SIZE); 277 up_read(&adev->reset_domain->sem); 278 279 if (res < 0) { 280 DRM_ERROR("Failed to write EEPROM table header:%d", res); 281 } else if (res < RAS_TABLE_HEADER_SIZE) { 282 DRM_ERROR("Short write:%d out of %d\n", 283 res, RAS_TABLE_HEADER_SIZE); 284 res = -EIO; 285 } else { 286 res = 0; 287 } 288 289 return res; 290 } 291 292 static void 293 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 294 unsigned char *buf) 295 { 296 u32 *pp = (uint32_t *)buf; 297 u32 tmp; 298 299 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 300 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 301 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 302 pp[0] = cpu_to_le32(tmp); 303 } 304 305 static void 306 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 307 unsigned char *buf) 308 { 309 u32 *pp = (uint32_t *)buf; 310 u32 tmp; 311 312 tmp = le32_to_cpu(pp[0]); 313 rai->rma_status = tmp & 0xFF; 314 rai->health_percent = (tmp >> 8) & 0xFF; 315 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 316 } 317 318 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 319 { 320 struct amdgpu_device *adev = to_amdgpu_device(control); 321 u8 *buf; 322 int res; 323 324 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 325 if (!buf) { 326 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 327 return -ENOMEM; 328 } 329 330 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 331 332 /* i2c may be unstable in gpu reset */ 333 down_read(&adev->reset_domain->sem); 334 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 335 control->i2c_address + 336 control->ras_info_offset, 337 buf, RAS_TABLE_V2_1_INFO_SIZE); 338 up_read(&adev->reset_domain->sem); 339 340 if (res < 0) { 341 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 342 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 343 DRM_ERROR("Short write:%d out of %d\n", 344 res, RAS_TABLE_V2_1_INFO_SIZE); 345 res = -EIO; 346 } else { 347 res = 0; 348 } 349 350 kfree(buf); 351 352 return res; 353 } 354 355 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 356 { 357 int ii; 358 u8 *pp, csum; 359 size_t sz; 360 361 /* Header checksum, skip checksum field in the calculation */ 362 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 363 pp = (u8 *) &control->tbl_hdr; 364 csum = 0; 365 for (ii = 0; ii < sz; ii++, pp++) 366 csum += *pp; 367 368 return csum; 369 } 370 371 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 372 { 373 int ii; 374 u8 *pp, csum; 375 size_t sz; 376 377 sz = sizeof(control->tbl_rai); 378 pp = (u8 *) &control->tbl_rai; 379 csum = 0; 380 for (ii = 0; ii < sz; ii++, pp++) 381 csum += *pp; 382 383 return csum; 384 } 385 386 static int amdgpu_ras_eeprom_correct_header_tag( 387 struct amdgpu_ras_eeprom_control *control, 388 uint32_t header) 389 { 390 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 391 u8 *hh; 392 int res; 393 u8 csum; 394 395 csum = -hdr->checksum; 396 397 hh = (void *) &hdr->header; 398 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 399 hh = (void *) &header; 400 csum += hh[0] + hh[1] + hh[2] + hh[3]; 401 csum = -csum; 402 mutex_lock(&control->ras_tbl_mutex); 403 hdr->header = header; 404 hdr->checksum = csum; 405 res = __write_table_header(control); 406 mutex_unlock(&control->ras_tbl_mutex); 407 408 return res; 409 } 410 411 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 412 { 413 struct amdgpu_device *adev = to_amdgpu_device(control); 414 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 415 416 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 417 case IP_VERSION(8, 10, 0): 418 hdr->version = RAS_TABLE_VER_V2_1; 419 return; 420 case IP_VERSION(12, 0, 0): 421 case IP_VERSION(12, 5, 0): 422 hdr->version = RAS_TABLE_VER_V3; 423 return; 424 default: 425 hdr->version = RAS_TABLE_VER_V1; 426 return; 427 } 428 } 429 430 /** 431 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 432 * @control: pointer to control structure 433 * 434 * Reset the contents of the header of the RAS EEPROM table. 435 * Return 0 on success, -errno on error. 436 */ 437 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 438 { 439 struct amdgpu_device *adev = to_amdgpu_device(control); 440 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 441 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 442 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 443 u8 csum; 444 int res; 445 446 mutex_lock(&control->ras_tbl_mutex); 447 448 hdr->header = RAS_TABLE_HDR_VAL; 449 amdgpu_ras_set_eeprom_table_version(control); 450 451 if (hdr->version >= RAS_TABLE_VER_V2_1) { 452 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 453 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 454 RAS_TABLE_V2_1_INFO_SIZE; 455 rai->rma_status = GPU_HEALTH_USABLE; 456 /** 457 * GPU health represented as a percentage. 458 * 0 means worst health, 100 means fully health. 459 */ 460 rai->health_percent = 100; 461 /* ecc_page_threshold = 0 means disable bad page retirement */ 462 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 463 } else { 464 hdr->first_rec_offset = RAS_RECORD_START; 465 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 466 } 467 468 csum = __calc_hdr_byte_sum(control); 469 if (hdr->version >= RAS_TABLE_VER_V2_1) 470 csum += __calc_ras_info_byte_sum(control); 471 csum = -csum; 472 hdr->checksum = csum; 473 res = __write_table_header(control); 474 if (!res && hdr->version > RAS_TABLE_VER_V1) 475 res = __write_table_ras_info(control); 476 477 control->ras_num_recs = 0; 478 control->ras_num_bad_pages = 0; 479 control->ras_num_mca_recs = 0; 480 control->ras_num_pa_recs = 0; 481 control->ras_fri = 0; 482 483 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); 484 485 control->bad_channel_bitmap = 0; 486 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 487 con->update_channel_flag = false; 488 489 amdgpu_ras_debugfs_set_ret_size(control); 490 491 mutex_unlock(&control->ras_tbl_mutex); 492 493 return res; 494 } 495 496 static void 497 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 498 struct eeprom_table_record *record, 499 unsigned char *buf) 500 { 501 __le64 tmp = 0; 502 int i = 0; 503 504 /* Next are all record fields according to EEPROM page spec in LE foramt */ 505 buf[i++] = record->err_type; 506 507 buf[i++] = record->bank; 508 509 tmp = cpu_to_le64(record->ts); 510 memcpy(buf + i, &tmp, 8); 511 i += 8; 512 513 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 514 memcpy(buf + i, &tmp, 6); 515 i += 6; 516 517 buf[i++] = record->mem_channel; 518 buf[i++] = record->mcumc_id; 519 520 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 521 memcpy(buf + i, &tmp, 6); 522 } 523 524 static void 525 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 526 struct eeprom_table_record *record, 527 unsigned char *buf) 528 { 529 __le64 tmp = 0; 530 int i = 0; 531 532 /* Next are all record fields according to EEPROM page spec in LE foramt */ 533 record->err_type = buf[i++]; 534 535 record->bank = buf[i++]; 536 537 memcpy(&tmp, buf + i, 8); 538 record->ts = le64_to_cpu(tmp); 539 i += 8; 540 541 memcpy(&tmp, buf + i, 6); 542 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 543 i += 6; 544 545 record->mem_channel = buf[i++]; 546 record->mcumc_id = buf[i++]; 547 548 memcpy(&tmp, buf + i, 6); 549 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 550 } 551 552 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 553 { 554 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 555 556 if (!__is_ras_eeprom_supported(adev) || 557 !amdgpu_bad_page_threshold) 558 return false; 559 560 /* skip check eeprom table for VEGA20 Gaming */ 561 if (!con) 562 return false; 563 else 564 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 565 return false; 566 567 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 568 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold) 569 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 570 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold); 571 if ((amdgpu_bad_page_threshold == -1) || 572 (amdgpu_bad_page_threshold == -2)) { 573 dev_warn(adev->dev, 574 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 575 return false; 576 } else { 577 dev_warn(adev->dev, 578 "Please consider adjusting the customized threshold.\n"); 579 return true; 580 } 581 } 582 583 return false; 584 } 585 586 /** 587 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 588 * @control: pointer to control structure 589 * @buf: pointer to buffer containing data to write 590 * @fri: start writing at this index 591 * @num: number of records to write 592 * 593 * The caller must hold the table mutex in @control. 594 * Return 0 on success, -errno otherwise. 595 */ 596 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 597 u8 *buf, const u32 fri, const u32 num) 598 { 599 struct amdgpu_device *adev = to_amdgpu_device(control); 600 u32 buf_size; 601 int res; 602 603 /* i2c may be unstable in gpu reset */ 604 down_read(&adev->reset_domain->sem); 605 buf_size = num * RAS_TABLE_RECORD_SIZE; 606 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 607 control->i2c_address + 608 RAS_INDEX_TO_OFFSET(control, fri), 609 buf, buf_size); 610 up_read(&adev->reset_domain->sem); 611 if (res < 0) { 612 DRM_ERROR("Writing %d EEPROM table records error:%d", 613 num, res); 614 } else if (res < buf_size) { 615 /* Short write, return error. 616 */ 617 DRM_ERROR("Wrote %d records out of %d", 618 res / RAS_TABLE_RECORD_SIZE, num); 619 res = -EIO; 620 } else { 621 res = 0; 622 } 623 624 return res; 625 } 626 627 static int 628 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 629 struct eeprom_table_record *record, 630 const u32 num) 631 { 632 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 633 struct amdgpu_device *adev = to_amdgpu_device(control); 634 u32 a, b, i; 635 u8 *buf, *pp; 636 int res; 637 638 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 639 if (!buf) 640 return -ENOMEM; 641 642 /* Encode all of them in one go. 643 */ 644 pp = buf; 645 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 646 __encode_table_record_to_buf(control, &record[i], pp); 647 648 /* update bad channel bitmap */ 649 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 650 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 651 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 652 con->update_channel_flag = true; 653 } 654 } 655 656 /* a, first record index to write into. 657 * b, last record index to write into. 658 * a = first index to read (fri) + number of records in the table, 659 * b = a + @num - 1. 660 * Let N = control->ras_max_num_record_count, then we have, 661 * case 0: 0 <= a <= b < N, 662 * just append @num records starting at a; 663 * case 1: 0 <= a < N <= b, 664 * append (N - a) records starting at a, and 665 * append the remainder, b % N + 1, starting at 0. 666 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 667 * case 2a: 0 <= a <= b < N 668 * append num records starting at a; and fix fri if b overwrote it, 669 * and since a <= b, if b overwrote it then a must've also, 670 * and if b didn't overwrite it, then a didn't also. 671 * case 2b: 0 <= b < a < N 672 * write num records starting at a, which wraps around 0=N 673 * and overwrite fri unconditionally. Now from case 2a, 674 * this means that b eclipsed fri to overwrite it and wrap 675 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 676 * set fri = b + 1 (mod N). 677 * Now, since fri is updated in every case, except the trivial case 0, 678 * the number of records present in the table after writing, is, 679 * num_recs - 1 = b - fri (mod N), and we take the positive value, 680 * by adding an arbitrary multiple of N before taking the modulo N 681 * as shown below. 682 */ 683 a = control->ras_fri + control->ras_num_recs; 684 b = a + num - 1; 685 if (b < control->ras_max_record_count) { 686 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 687 } else if (a < control->ras_max_record_count) { 688 u32 g0, g1; 689 690 g0 = control->ras_max_record_count - a; 691 g1 = b % control->ras_max_record_count + 1; 692 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 693 if (res) 694 goto Out; 695 res = __amdgpu_ras_eeprom_write(control, 696 buf + g0 * RAS_TABLE_RECORD_SIZE, 697 0, g1); 698 if (res) 699 goto Out; 700 if (g1 > control->ras_fri) 701 control->ras_fri = g1 % control->ras_max_record_count; 702 } else { 703 a %= control->ras_max_record_count; 704 b %= control->ras_max_record_count; 705 706 if (a <= b) { 707 /* Note that, b - a + 1 = num. */ 708 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 709 if (res) 710 goto Out; 711 if (b >= control->ras_fri) 712 control->ras_fri = (b + 1) % control->ras_max_record_count; 713 } else { 714 u32 g0, g1; 715 716 /* b < a, which means, we write from 717 * a to the end of the table, and from 718 * the start of the table to b. 719 */ 720 g0 = control->ras_max_record_count - a; 721 g1 = b + 1; 722 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 723 if (res) 724 goto Out; 725 res = __amdgpu_ras_eeprom_write(control, 726 buf + g0 * RAS_TABLE_RECORD_SIZE, 727 0, g1); 728 if (res) 729 goto Out; 730 control->ras_fri = g1 % control->ras_max_record_count; 731 } 732 } 733 control->ras_num_recs = 1 + (control->ras_max_record_count + b 734 - control->ras_fri) 735 % control->ras_max_record_count; 736 737 /*old asics only save pa to eeprom like before*/ 738 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) 739 control->ras_num_pa_recs += num; 740 else 741 control->ras_num_mca_recs += num; 742 743 control->ras_num_bad_pages = control->ras_num_pa_recs + 744 control->ras_num_mca_recs * adev->umc.retire_unit; 745 Out: 746 kfree(buf); 747 return res; 748 } 749 750 static int 751 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 752 { 753 struct amdgpu_device *adev = to_amdgpu_device(control); 754 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 755 u8 *buf, *pp, csum; 756 u32 buf_size; 757 int res; 758 759 /* Modify the header if it exceeds. 760 */ 761 if (amdgpu_bad_page_threshold != 0 && 762 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 763 dev_warn(adev->dev, 764 "Saved bad pages %d reaches threshold value %d\n", 765 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 766 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 767 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 768 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 769 control->tbl_rai.health_percent = 0; 770 } 771 772 if ((amdgpu_bad_page_threshold != -1) && 773 (amdgpu_bad_page_threshold != -2)) 774 ras->is_rma = true; 775 776 /* ignore the -ENOTSUPP return value */ 777 amdgpu_dpm_send_rma_reason(adev); 778 } 779 780 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 781 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 782 RAS_TABLE_V2_1_INFO_SIZE + 783 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 784 else 785 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 786 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 787 control->tbl_hdr.checksum = 0; 788 789 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 790 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 791 if (!buf) { 792 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 793 control->tbl_hdr.tbl_size); 794 res = -ENOMEM; 795 goto Out; 796 } 797 798 down_read(&adev->reset_domain->sem); 799 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 800 control->i2c_address + 801 control->ras_record_offset, 802 buf, buf_size); 803 up_read(&adev->reset_domain->sem); 804 if (res < 0) { 805 DRM_ERROR("EEPROM failed reading records:%d\n", 806 res); 807 goto Out; 808 } else if (res < buf_size) { 809 DRM_ERROR("EEPROM read %d out of %d bytes\n", 810 res, buf_size); 811 res = -EIO; 812 goto Out; 813 } 814 815 /** 816 * bad page records have been stored in eeprom, 817 * now calculate gpu health percent 818 */ 819 if (amdgpu_bad_page_threshold != 0 && 820 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 821 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) 822 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 823 control->ras_num_bad_pages) * 100) / 824 ras->bad_page_cnt_threshold; 825 826 /* Recalc the checksum. 827 */ 828 csum = 0; 829 for (pp = buf; pp < buf + buf_size; pp++) 830 csum += *pp; 831 832 csum += __calc_hdr_byte_sum(control); 833 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 834 csum += __calc_ras_info_byte_sum(control); 835 /* avoid sign extension when assigning to "checksum" */ 836 csum = -csum; 837 control->tbl_hdr.checksum = csum; 838 res = __write_table_header(control); 839 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 840 res = __write_table_ras_info(control); 841 Out: 842 kfree(buf); 843 return res; 844 } 845 846 /** 847 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 848 * @control: pointer to control structure 849 * @record: array of records to append 850 * @num: number of records in @record array 851 * 852 * Append @num records to the table, calculate the checksum and write 853 * the table back to EEPROM. The maximum number of records that 854 * can be appended is between 1 and control->ras_max_record_count, 855 * regardless of how many records are already stored in the table. 856 * 857 * Return 0 on success or if EEPROM is not supported, -errno on error. 858 */ 859 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 860 struct eeprom_table_record *record, 861 const u32 num) 862 { 863 struct amdgpu_device *adev = to_amdgpu_device(control); 864 int res, i; 865 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 866 867 if (!__is_ras_eeprom_supported(adev)) 868 return 0; 869 870 if (num == 0) { 871 DRM_ERROR("will not append 0 records\n"); 872 return -EINVAL; 873 } else if (num > control->ras_max_record_count) { 874 DRM_ERROR("cannot append %d records than the size of table %d\n", 875 num, control->ras_max_record_count); 876 return -EINVAL; 877 } 878 879 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 880 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 881 882 /* set the new channel index flag */ 883 for (i = 0; i < num; i++) 884 record[i].retired_page |= (nps << UMC_NPS_SHIFT); 885 886 mutex_lock(&control->ras_tbl_mutex); 887 888 res = amdgpu_ras_eeprom_append_table(control, record, num); 889 if (!res) 890 res = amdgpu_ras_eeprom_update_header(control); 891 if (!res) 892 amdgpu_ras_debugfs_set_ret_size(control); 893 894 mutex_unlock(&control->ras_tbl_mutex); 895 896 /* clear channel index flag, the flag is only saved on eeprom */ 897 for (i = 0; i < num; i++) 898 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT); 899 900 return res; 901 } 902 903 /** 904 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 905 * @control: pointer to control structure 906 * @buf: pointer to buffer to read into 907 * @fri: first record index, start reading at this index, absolute index 908 * @num: number of records to read 909 * 910 * The caller must hold the table mutex in @control. 911 * Return 0 on success, -errno otherwise. 912 */ 913 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 914 u8 *buf, const u32 fri, const u32 num) 915 { 916 struct amdgpu_device *adev = to_amdgpu_device(control); 917 u32 buf_size; 918 int res; 919 920 /* i2c may be unstable in gpu reset */ 921 down_read(&adev->reset_domain->sem); 922 buf_size = num * RAS_TABLE_RECORD_SIZE; 923 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 924 control->i2c_address + 925 RAS_INDEX_TO_OFFSET(control, fri), 926 buf, buf_size); 927 up_read(&adev->reset_domain->sem); 928 if (res < 0) { 929 DRM_ERROR("Reading %d EEPROM table records error:%d", 930 num, res); 931 } else if (res < buf_size) { 932 /* Short read, return error. 933 */ 934 DRM_ERROR("Read %d records out of %d", 935 res / RAS_TABLE_RECORD_SIZE, num); 936 res = -EIO; 937 } else { 938 res = 0; 939 } 940 941 return res; 942 } 943 944 /** 945 * amdgpu_ras_eeprom_read -- read EEPROM 946 * @control: pointer to control structure 947 * @record: array of records to read into 948 * @num: number of records in @record 949 * 950 * Reads num records from the RAS table in EEPROM and 951 * writes the data into @record array. 952 * 953 * Returns 0 on success, -errno on error. 954 */ 955 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 956 struct eeprom_table_record *record, 957 const u32 num) 958 { 959 struct amdgpu_device *adev = to_amdgpu_device(control); 960 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 961 int i, res; 962 u8 *buf, *pp; 963 u32 g0, g1; 964 965 if (!__is_ras_eeprom_supported(adev)) 966 return 0; 967 968 if (num == 0) { 969 DRM_ERROR("will not read 0 records\n"); 970 return -EINVAL; 971 } else if (num > control->ras_num_recs) { 972 DRM_ERROR("too many records to read:%d available:%d\n", 973 num, control->ras_num_recs); 974 return -EINVAL; 975 } 976 977 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 978 if (!buf) 979 return -ENOMEM; 980 981 /* Determine how many records to read, from the first record 982 * index, fri, to the end of the table, and from the beginning 983 * of the table, such that the total number of records is 984 * @num, and we handle wrap around when fri > 0 and 985 * fri + num > RAS_MAX_RECORD_COUNT. 986 * 987 * First we compute the index of the last element 988 * which would be fetched from each region, 989 * g0 is in [fri, fri + num - 1], and 990 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 991 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 992 * the last element to fetch, we set g0 to _the number_ 993 * of elements to fetch, @num, since we know that the last 994 * indexed to be fetched does not exceed the table. 995 * 996 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 997 * we set g0 to the number of elements to read 998 * until the end of the table, and g1 to the number of 999 * elements to read from the beginning of the table. 1000 */ 1001 g0 = control->ras_fri + num - 1; 1002 g1 = g0 % control->ras_max_record_count; 1003 if (g0 < control->ras_max_record_count) { 1004 g0 = num; 1005 g1 = 0; 1006 } else { 1007 g0 = control->ras_max_record_count - control->ras_fri; 1008 g1 += 1; 1009 } 1010 1011 mutex_lock(&control->ras_tbl_mutex); 1012 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 1013 if (res) 1014 goto Out; 1015 if (g1) { 1016 res = __amdgpu_ras_eeprom_read(control, 1017 buf + g0 * RAS_TABLE_RECORD_SIZE, 1018 0, g1); 1019 if (res) 1020 goto Out; 1021 } 1022 1023 res = 0; 1024 1025 /* Read up everything? Then transform. 1026 */ 1027 pp = buf; 1028 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 1029 __decode_table_record_from_buf(control, &record[i], pp); 1030 1031 /* update bad channel bitmap */ 1032 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1033 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1034 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1035 con->update_channel_flag = true; 1036 } 1037 } 1038 Out: 1039 kfree(buf); 1040 mutex_unlock(&control->ras_tbl_mutex); 1041 1042 return res; 1043 } 1044 1045 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1046 { 1047 /* get available eeprom table version first before eeprom table init */ 1048 amdgpu_ras_set_eeprom_table_version(control); 1049 1050 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1051 return RAS_MAX_RECORD_COUNT_V2_1; 1052 else 1053 return RAS_MAX_RECORD_COUNT; 1054 } 1055 1056 static ssize_t 1057 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1058 size_t size, loff_t *pos) 1059 { 1060 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1061 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1062 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1063 u8 data[50]; 1064 int res; 1065 1066 if (!size) 1067 return size; 1068 1069 if (!ras || !control) { 1070 res = snprintf(data, sizeof(data), "Not supported\n"); 1071 } else { 1072 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1073 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1074 } 1075 1076 if (*pos >= res) 1077 return 0; 1078 1079 res -= *pos; 1080 res = min_t(size_t, res, size); 1081 1082 if (copy_to_user(buf, &data[*pos], res)) 1083 return -EFAULT; 1084 1085 *pos += res; 1086 1087 return res; 1088 } 1089 1090 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1091 .owner = THIS_MODULE, 1092 .read = amdgpu_ras_debugfs_eeprom_size_read, 1093 .write = NULL, 1094 .llseek = default_llseek, 1095 }; 1096 1097 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1098 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1099 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1100 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1101 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1102 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1103 1104 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1105 "ignore", 1106 "re", 1107 "ue", 1108 }; 1109 1110 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1111 { 1112 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1113 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1114 } 1115 1116 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1117 { 1118 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1119 eeprom_control); 1120 struct dentry *de = ras->de_ras_eeprom_table; 1121 1122 if (de) 1123 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1124 } 1125 1126 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1127 size_t size, loff_t *pos) 1128 { 1129 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1130 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1131 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1132 const size_t orig_size = size; 1133 int res = -EFAULT; 1134 size_t data_len; 1135 1136 mutex_lock(&control->ras_tbl_mutex); 1137 1138 /* We want *pos - data_len > 0, which means there's 1139 * bytes to be printed from data. 1140 */ 1141 data_len = strlen(tbl_hdr_str); 1142 if (*pos < data_len) { 1143 data_len -= *pos; 1144 data_len = min_t(size_t, data_len, size); 1145 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1146 goto Out; 1147 buf += data_len; 1148 size -= data_len; 1149 *pos += data_len; 1150 } 1151 1152 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1153 if (*pos < data_len && size > 0) { 1154 u8 data[tbl_hdr_fmt_size + 1]; 1155 loff_t lpos; 1156 1157 snprintf(data, sizeof(data), tbl_hdr_fmt, 1158 control->tbl_hdr.header, 1159 control->tbl_hdr.version, 1160 control->tbl_hdr.first_rec_offset, 1161 control->tbl_hdr.tbl_size, 1162 control->tbl_hdr.checksum); 1163 1164 data_len -= *pos; 1165 data_len = min_t(size_t, data_len, size); 1166 lpos = *pos - strlen(tbl_hdr_str); 1167 if (copy_to_user(buf, &data[lpos], data_len)) 1168 goto Out; 1169 buf += data_len; 1170 size -= data_len; 1171 *pos += data_len; 1172 } 1173 1174 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1175 if (*pos < data_len && size > 0) { 1176 loff_t lpos; 1177 1178 data_len -= *pos; 1179 data_len = min_t(size_t, data_len, size); 1180 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1181 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1182 goto Out; 1183 buf += data_len; 1184 size -= data_len; 1185 *pos += data_len; 1186 } 1187 1188 data_len = amdgpu_ras_debugfs_table_size(control); 1189 if (*pos < data_len && size > 0) { 1190 u8 dare[RAS_TABLE_RECORD_SIZE]; 1191 u8 data[rec_hdr_fmt_size + 1]; 1192 struct eeprom_table_record record; 1193 int s, r; 1194 1195 /* Find the starting record index 1196 */ 1197 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1198 strlen(rec_hdr_str); 1199 s = s / rec_hdr_fmt_size; 1200 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1201 strlen(rec_hdr_str); 1202 r = r % rec_hdr_fmt_size; 1203 1204 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1205 u32 ai = RAS_RI_TO_AI(control, s); 1206 /* Read a single record 1207 */ 1208 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1209 if (res) 1210 goto Out; 1211 __decode_table_record_from_buf(control, &record, dare); 1212 snprintf(data, sizeof(data), rec_hdr_fmt, 1213 s, 1214 RAS_INDEX_TO_OFFSET(control, ai), 1215 record_err_type_str[record.err_type], 1216 record.bank, 1217 record.ts, 1218 record.offset, 1219 record.mem_channel, 1220 record.mcumc_id, 1221 record.retired_page); 1222 1223 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1224 if (copy_to_user(buf, &data[r], data_len)) { 1225 res = -EFAULT; 1226 goto Out; 1227 } 1228 buf += data_len; 1229 size -= data_len; 1230 *pos += data_len; 1231 r = 0; 1232 } 1233 } 1234 res = 0; 1235 Out: 1236 mutex_unlock(&control->ras_tbl_mutex); 1237 return res < 0 ? res : orig_size - size; 1238 } 1239 1240 static ssize_t 1241 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1242 size_t size, loff_t *pos) 1243 { 1244 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1245 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1246 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1247 u8 data[81]; 1248 int res; 1249 1250 if (!size) 1251 return size; 1252 1253 if (!ras || !control) { 1254 res = snprintf(data, sizeof(data), "Not supported\n"); 1255 if (*pos >= res) 1256 return 0; 1257 1258 res -= *pos; 1259 res = min_t(size_t, res, size); 1260 1261 if (copy_to_user(buf, &data[*pos], res)) 1262 return -EFAULT; 1263 1264 *pos += res; 1265 1266 return res; 1267 } else { 1268 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1269 } 1270 } 1271 1272 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1273 .owner = THIS_MODULE, 1274 .read = amdgpu_ras_debugfs_eeprom_table_read, 1275 .write = NULL, 1276 .llseek = default_llseek, 1277 }; 1278 1279 /** 1280 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1281 * @control: pointer to control structure 1282 * 1283 * Check the checksum of the stored in EEPROM RAS table. 1284 * 1285 * Return 0 if the checksum is correct, 1286 * positive if it is not correct, and 1287 * -errno on I/O error. 1288 */ 1289 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1290 { 1291 struct amdgpu_device *adev = to_amdgpu_device(control); 1292 int buf_size, res; 1293 u8 csum, *buf, *pp; 1294 1295 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1296 buf_size = RAS_TABLE_HEADER_SIZE + 1297 RAS_TABLE_V2_1_INFO_SIZE + 1298 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1299 else 1300 buf_size = RAS_TABLE_HEADER_SIZE + 1301 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1302 1303 buf = kzalloc(buf_size, GFP_KERNEL); 1304 if (!buf) { 1305 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1306 return -ENOMEM; 1307 } 1308 1309 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1310 control->i2c_address + 1311 control->ras_header_offset, 1312 buf, buf_size); 1313 if (res < buf_size) { 1314 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1315 /* On partial reads, return -EIO. 1316 */ 1317 if (res >= 0) 1318 res = -EIO; 1319 goto Out; 1320 } 1321 1322 csum = 0; 1323 for (pp = buf; pp < buf + buf_size; pp++) 1324 csum += *pp; 1325 Out: 1326 kfree(buf); 1327 return res < 0 ? res : csum; 1328 } 1329 1330 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1331 { 1332 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1333 struct amdgpu_device *adev = to_amdgpu_device(control); 1334 unsigned char *buf; 1335 int res; 1336 1337 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1338 if (!buf) { 1339 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1340 return -ENOMEM; 1341 } 1342 1343 /** 1344 * EEPROM table V2_1 supports ras info, 1345 * read EEPROM table ras info 1346 */ 1347 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1348 control->i2c_address + control->ras_info_offset, 1349 buf, RAS_TABLE_V2_1_INFO_SIZE); 1350 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1351 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1352 res = res >= 0 ? -EIO : res; 1353 goto Out; 1354 } 1355 1356 __decode_table_ras_info_from_buf(rai, buf); 1357 1358 Out: 1359 kfree(buf); 1360 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1361 } 1362 1363 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1364 { 1365 struct amdgpu_device *adev = to_amdgpu_device(control); 1366 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1367 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1368 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1369 int res; 1370 1371 ras->is_rma = false; 1372 1373 if (!__is_ras_eeprom_supported(adev)) 1374 return 0; 1375 1376 /* Verify i2c adapter is initialized */ 1377 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1378 return -ENOENT; 1379 1380 if (!__get_eeprom_i2c_addr(adev, control)) 1381 return -EINVAL; 1382 1383 control->ras_header_offset = RAS_HDR_START; 1384 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1385 mutex_init(&control->ras_tbl_mutex); 1386 1387 /* Read the table header from EEPROM address */ 1388 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1389 control->i2c_address + control->ras_header_offset, 1390 buf, RAS_TABLE_HEADER_SIZE); 1391 if (res < RAS_TABLE_HEADER_SIZE) { 1392 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1393 return res >= 0 ? -EIO : res; 1394 } 1395 1396 __decode_table_header_from_buf(hdr, buf); 1397 1398 if (hdr->header != RAS_TABLE_HDR_VAL && 1399 hdr->header != RAS_TABLE_HDR_BAD) { 1400 dev_info(adev->dev, "Creating a new EEPROM table"); 1401 return amdgpu_ras_eeprom_reset_table(control); 1402 } 1403 1404 switch (hdr->version) { 1405 case RAS_TABLE_VER_V2_1: 1406 case RAS_TABLE_VER_V3: 1407 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1408 control->ras_record_offset = RAS_RECORD_START_V2_1; 1409 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1410 break; 1411 case RAS_TABLE_VER_V1: 1412 control->ras_num_recs = RAS_NUM_RECS(hdr); 1413 control->ras_record_offset = RAS_RECORD_START; 1414 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1415 break; 1416 default: 1417 dev_err(adev->dev, 1418 "RAS header invalid, unsupported version: %u", 1419 hdr->version); 1420 return -EINVAL; 1421 } 1422 1423 if (control->ras_num_recs > control->ras_max_record_count) { 1424 dev_err(adev->dev, 1425 "RAS header invalid, records in header: %u max allowed :%u", 1426 control->ras_num_recs, control->ras_max_record_count); 1427 return -EINVAL; 1428 } 1429 1430 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1431 control->ras_num_mca_recs = 0; 1432 control->ras_num_pa_recs = 0; 1433 return 0; 1434 } 1435 1436 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1437 { 1438 struct amdgpu_device *adev = to_amdgpu_device(control); 1439 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1440 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1441 int res = 0; 1442 1443 if (!__is_ras_eeprom_supported(adev)) 1444 return 0; 1445 1446 /* Verify i2c adapter is initialized */ 1447 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1448 return -ENOENT; 1449 1450 if (!__get_eeprom_i2c_addr(adev, control)) 1451 return -EINVAL; 1452 1453 control->ras_num_bad_pages = control->ras_num_pa_recs + 1454 control->ras_num_mca_recs * adev->umc.retire_unit; 1455 1456 if (hdr->header == RAS_TABLE_HDR_VAL) { 1457 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1458 control->ras_num_bad_pages); 1459 1460 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1461 res = __read_table_ras_info(control); 1462 if (res) 1463 return res; 1464 } 1465 1466 res = __verify_ras_table_checksum(control); 1467 if (res) 1468 dev_err(adev->dev, 1469 "RAS table incorrect checksum or error:%d\n", 1470 res); 1471 1472 /* Warn if we are at 90% of the threshold or above 1473 */ 1474 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1475 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1476 control->ras_num_bad_pages, 1477 ras->bad_page_cnt_threshold); 1478 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1479 amdgpu_bad_page_threshold != 0) { 1480 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1481 res = __read_table_ras_info(control); 1482 if (res) 1483 return res; 1484 } 1485 1486 res = __verify_ras_table_checksum(control); 1487 if (res) { 1488 dev_err(adev->dev, 1489 "RAS Table incorrect checksum or error:%d\n", 1490 res); 1491 return -EINVAL; 1492 } 1493 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { 1494 /* This means that, the threshold was increased since 1495 * the last time the system was booted, and now, 1496 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1497 * so that at least one more record can be saved, 1498 * before the page count threshold is reached. 1499 */ 1500 dev_info(adev->dev, 1501 "records:%d threshold:%d, resetting " 1502 "RAS table header signature", 1503 control->ras_num_bad_pages, 1504 ras->bad_page_cnt_threshold); 1505 res = amdgpu_ras_eeprom_correct_header_tag(control, 1506 RAS_TABLE_HDR_VAL); 1507 } else { 1508 dev_warn(adev->dev, 1509 "RAS records:%d exceed threshold:%d\n", 1510 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1511 if ((amdgpu_bad_page_threshold == -1) || 1512 (amdgpu_bad_page_threshold == -2)) { 1513 res = 0; 1514 dev_warn(adev->dev, 1515 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1516 } else { 1517 ras->is_rma = true; 1518 dev_warn(adev->dev, 1519 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1520 } 1521 } 1522 } 1523 1524 return res < 0 ? res : 0; 1525 } 1526