1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 10): 162 return true; 163 case IP_VERSION(13, 0, 6): 164 return (adev->gmc.is_app_apu) ? false : true; 165 default: 166 return false; 167 } 168 } 169 170 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 171 struct amdgpu_ras_eeprom_control *control) 172 { 173 struct atom_context *atom_ctx = adev->mode_info.atom_context; 174 u8 i2c_addr; 175 176 if (!control) 177 return false; 178 179 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 180 /* The address given by VBIOS is an 8-bit, wire-format 181 * address, i.e. the most significant byte. 182 * 183 * Normalize it to a 19-bit EEPROM address. Remove the 184 * device type identifier and make it a 7-bit address; 185 * then make it a 19-bit EEPROM address. See top of 186 * amdgpu_eeprom.c. 187 */ 188 i2c_addr = (i2c_addr & 0x0F) >> 1; 189 control->i2c_address = ((u32) i2c_addr) << 16; 190 191 return true; 192 } 193 194 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 195 case IP_VERSION(11, 0, 2): 196 /* VEGA20 and ARCTURUS */ 197 if (adev->asic_type == CHIP_VEGA20) 198 control->i2c_address = EEPROM_I2C_MADDR_0; 199 else if (strnstr(atom_ctx->vbios_pn, 200 "D342", 201 sizeof(atom_ctx->vbios_pn))) 202 control->i2c_address = EEPROM_I2C_MADDR_0; 203 else 204 control->i2c_address = EEPROM_I2C_MADDR_4; 205 return true; 206 case IP_VERSION(11, 0, 7): 207 control->i2c_address = EEPROM_I2C_MADDR_0; 208 return true; 209 case IP_VERSION(13, 0, 2): 210 if (strnstr(atom_ctx->vbios_pn, "D673", 211 sizeof(atom_ctx->vbios_pn))) 212 control->i2c_address = EEPROM_I2C_MADDR_4; 213 else 214 control->i2c_address = EEPROM_I2C_MADDR_0; 215 return true; 216 case IP_VERSION(13, 0, 0): 217 if (strnstr(atom_ctx->vbios_pn, "D707", 218 sizeof(atom_ctx->vbios_pn))) 219 control->i2c_address = EEPROM_I2C_MADDR_0; 220 else 221 control->i2c_address = EEPROM_I2C_MADDR_4; 222 return true; 223 case IP_VERSION(13, 0, 6): 224 case IP_VERSION(13, 0, 10): 225 control->i2c_address = EEPROM_I2C_MADDR_4; 226 return true; 227 default: 228 return false; 229 } 230 } 231 232 static void 233 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 234 unsigned char *buf) 235 { 236 u32 *pp = (uint32_t *)buf; 237 238 pp[0] = cpu_to_le32(hdr->header); 239 pp[1] = cpu_to_le32(hdr->version); 240 pp[2] = cpu_to_le32(hdr->first_rec_offset); 241 pp[3] = cpu_to_le32(hdr->tbl_size); 242 pp[4] = cpu_to_le32(hdr->checksum); 243 } 244 245 static void 246 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 247 unsigned char *buf) 248 { 249 u32 *pp = (uint32_t *)buf; 250 251 hdr->header = le32_to_cpu(pp[0]); 252 hdr->version = le32_to_cpu(pp[1]); 253 hdr->first_rec_offset = le32_to_cpu(pp[2]); 254 hdr->tbl_size = le32_to_cpu(pp[3]); 255 hdr->checksum = le32_to_cpu(pp[4]); 256 } 257 258 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 259 { 260 u8 buf[RAS_TABLE_HEADER_SIZE]; 261 struct amdgpu_device *adev = to_amdgpu_device(control); 262 int res; 263 264 memset(buf, 0, sizeof(buf)); 265 __encode_table_header_to_buf(&control->tbl_hdr, buf); 266 267 /* i2c may be unstable in gpu reset */ 268 down_read(&adev->reset_domain->sem); 269 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 270 control->i2c_address + 271 control->ras_header_offset, 272 buf, RAS_TABLE_HEADER_SIZE); 273 up_read(&adev->reset_domain->sem); 274 275 if (res < 0) { 276 DRM_ERROR("Failed to write EEPROM table header:%d", res); 277 } else if (res < RAS_TABLE_HEADER_SIZE) { 278 DRM_ERROR("Short write:%d out of %d\n", 279 res, RAS_TABLE_HEADER_SIZE); 280 res = -EIO; 281 } else { 282 res = 0; 283 } 284 285 return res; 286 } 287 288 static void 289 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 290 unsigned char *buf) 291 { 292 u32 *pp = (uint32_t *)buf; 293 u32 tmp; 294 295 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 296 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 297 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 298 pp[0] = cpu_to_le32(tmp); 299 } 300 301 static void 302 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 303 unsigned char *buf) 304 { 305 u32 *pp = (uint32_t *)buf; 306 u32 tmp; 307 308 tmp = le32_to_cpu(pp[0]); 309 rai->rma_status = tmp & 0xFF; 310 rai->health_percent = (tmp >> 8) & 0xFF; 311 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 312 } 313 314 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 315 { 316 struct amdgpu_device *adev = to_amdgpu_device(control); 317 u8 *buf; 318 int res; 319 320 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 321 if (!buf) { 322 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 323 return -ENOMEM; 324 } 325 326 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 327 328 /* i2c may be unstable in gpu reset */ 329 down_read(&adev->reset_domain->sem); 330 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 331 control->i2c_address + 332 control->ras_info_offset, 333 buf, RAS_TABLE_V2_1_INFO_SIZE); 334 up_read(&adev->reset_domain->sem); 335 336 if (res < 0) { 337 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 338 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 339 DRM_ERROR("Short write:%d out of %d\n", 340 res, RAS_TABLE_V2_1_INFO_SIZE); 341 res = -EIO; 342 } else { 343 res = 0; 344 } 345 346 kfree(buf); 347 348 return res; 349 } 350 351 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 352 { 353 int ii; 354 u8 *pp, csum; 355 size_t sz; 356 357 /* Header checksum, skip checksum field in the calculation */ 358 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 359 pp = (u8 *) &control->tbl_hdr; 360 csum = 0; 361 for (ii = 0; ii < sz; ii++, pp++) 362 csum += *pp; 363 364 return csum; 365 } 366 367 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 368 { 369 int ii; 370 u8 *pp, csum; 371 size_t sz; 372 373 sz = sizeof(control->tbl_rai); 374 pp = (u8 *) &control->tbl_rai; 375 csum = 0; 376 for (ii = 0; ii < sz; ii++, pp++) 377 csum += *pp; 378 379 return csum; 380 } 381 382 static int amdgpu_ras_eeprom_correct_header_tag( 383 struct amdgpu_ras_eeprom_control *control, 384 uint32_t header) 385 { 386 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 387 u8 *hh; 388 int res; 389 u8 csum; 390 391 csum = -hdr->checksum; 392 393 hh = (void *) &hdr->header; 394 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 395 hh = (void *) &header; 396 csum += hh[0] + hh[1] + hh[2] + hh[3]; 397 csum = -csum; 398 mutex_lock(&control->ras_tbl_mutex); 399 hdr->header = header; 400 hdr->checksum = csum; 401 res = __write_table_header(control); 402 mutex_unlock(&control->ras_tbl_mutex); 403 404 return res; 405 } 406 407 /** 408 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 409 * @control: pointer to control structure 410 * 411 * Reset the contents of the header of the RAS EEPROM table. 412 * Return 0 on success, -errno on error. 413 */ 414 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 415 { 416 struct amdgpu_device *adev = to_amdgpu_device(control); 417 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 418 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 419 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 420 u8 csum; 421 int res; 422 423 mutex_lock(&control->ras_tbl_mutex); 424 425 hdr->header = RAS_TABLE_HDR_VAL; 426 if (adev->umc.ras && 427 adev->umc.ras->set_eeprom_table_version) 428 adev->umc.ras->set_eeprom_table_version(hdr); 429 else 430 hdr->version = RAS_TABLE_VER_V1; 431 432 if (hdr->version == RAS_TABLE_VER_V2_1) { 433 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 434 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 435 RAS_TABLE_V2_1_INFO_SIZE; 436 rai->rma_status = GPU_HEALTH_USABLE; 437 /** 438 * GPU health represented as a percentage. 439 * 0 means worst health, 100 means fully health. 440 */ 441 rai->health_percent = 100; 442 /* ecc_page_threshold = 0 means disable bad page retirement */ 443 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 444 } else { 445 hdr->first_rec_offset = RAS_RECORD_START; 446 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 447 } 448 449 csum = __calc_hdr_byte_sum(control); 450 if (hdr->version == RAS_TABLE_VER_V2_1) 451 csum += __calc_ras_info_byte_sum(control); 452 csum = -csum; 453 hdr->checksum = csum; 454 res = __write_table_header(control); 455 if (!res && hdr->version > RAS_TABLE_VER_V1) 456 res = __write_table_ras_info(control); 457 458 control->ras_num_recs = 0; 459 control->ras_fri = 0; 460 461 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 462 463 control->bad_channel_bitmap = 0; 464 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 465 con->update_channel_flag = false; 466 467 amdgpu_ras_debugfs_set_ret_size(control); 468 469 mutex_unlock(&control->ras_tbl_mutex); 470 471 return res; 472 } 473 474 static void 475 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 476 struct eeprom_table_record *record, 477 unsigned char *buf) 478 { 479 __le64 tmp = 0; 480 int i = 0; 481 482 /* Next are all record fields according to EEPROM page spec in LE foramt */ 483 buf[i++] = record->err_type; 484 485 buf[i++] = record->bank; 486 487 tmp = cpu_to_le64(record->ts); 488 memcpy(buf + i, &tmp, 8); 489 i += 8; 490 491 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 492 memcpy(buf + i, &tmp, 6); 493 i += 6; 494 495 buf[i++] = record->mem_channel; 496 buf[i++] = record->mcumc_id; 497 498 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 499 memcpy(buf + i, &tmp, 6); 500 } 501 502 static void 503 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 504 struct eeprom_table_record *record, 505 unsigned char *buf) 506 { 507 __le64 tmp = 0; 508 int i = 0; 509 510 /* Next are all record fields according to EEPROM page spec in LE foramt */ 511 record->err_type = buf[i++]; 512 513 record->bank = buf[i++]; 514 515 memcpy(&tmp, buf + i, 8); 516 record->ts = le64_to_cpu(tmp); 517 i += 8; 518 519 memcpy(&tmp, buf + i, 6); 520 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 521 i += 6; 522 523 record->mem_channel = buf[i++]; 524 record->mcumc_id = buf[i++]; 525 526 memcpy(&tmp, buf + i, 6); 527 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 528 } 529 530 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 531 { 532 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 533 534 if (!__is_ras_eeprom_supported(adev) || 535 !amdgpu_bad_page_threshold) 536 return false; 537 538 /* skip check eeprom table for VEGA20 Gaming */ 539 if (!con) 540 return false; 541 else 542 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 543 return false; 544 545 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 546 if (amdgpu_bad_page_threshold == -1) { 547 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 548 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold); 549 dev_warn(adev->dev, 550 "But GPU can be operated due to bad_page_threshold = -1.\n"); 551 return false; 552 } else { 553 dev_warn(adev->dev, "This GPU is in BAD status."); 554 dev_warn(adev->dev, "Please retire it or set a larger " 555 "threshold value when reloading driver.\n"); 556 return true; 557 } 558 } 559 560 return false; 561 } 562 563 /** 564 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 565 * @control: pointer to control structure 566 * @buf: pointer to buffer containing data to write 567 * @fri: start writing at this index 568 * @num: number of records to write 569 * 570 * The caller must hold the table mutex in @control. 571 * Return 0 on success, -errno otherwise. 572 */ 573 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 574 u8 *buf, const u32 fri, const u32 num) 575 { 576 struct amdgpu_device *adev = to_amdgpu_device(control); 577 u32 buf_size; 578 int res; 579 580 /* i2c may be unstable in gpu reset */ 581 down_read(&adev->reset_domain->sem); 582 buf_size = num * RAS_TABLE_RECORD_SIZE; 583 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 584 control->i2c_address + 585 RAS_INDEX_TO_OFFSET(control, fri), 586 buf, buf_size); 587 up_read(&adev->reset_domain->sem); 588 if (res < 0) { 589 DRM_ERROR("Writing %d EEPROM table records error:%d", 590 num, res); 591 } else if (res < buf_size) { 592 /* Short write, return error. 593 */ 594 DRM_ERROR("Wrote %d records out of %d", 595 res / RAS_TABLE_RECORD_SIZE, num); 596 res = -EIO; 597 } else { 598 res = 0; 599 } 600 601 return res; 602 } 603 604 static int 605 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 606 struct eeprom_table_record *record, 607 const u32 num) 608 { 609 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 610 u32 a, b, i; 611 u8 *buf, *pp; 612 int res; 613 614 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 615 if (!buf) 616 return -ENOMEM; 617 618 /* Encode all of them in one go. 619 */ 620 pp = buf; 621 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 622 __encode_table_record_to_buf(control, &record[i], pp); 623 624 /* update bad channel bitmap */ 625 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 626 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 627 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 628 con->update_channel_flag = true; 629 } 630 } 631 632 /* a, first record index to write into. 633 * b, last record index to write into. 634 * a = first index to read (fri) + number of records in the table, 635 * b = a + @num - 1. 636 * Let N = control->ras_max_num_record_count, then we have, 637 * case 0: 0 <= a <= b < N, 638 * just append @num records starting at a; 639 * case 1: 0 <= a < N <= b, 640 * append (N - a) records starting at a, and 641 * append the remainder, b % N + 1, starting at 0. 642 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 643 * case 2a: 0 <= a <= b < N 644 * append num records starting at a; and fix fri if b overwrote it, 645 * and since a <= b, if b overwrote it then a must've also, 646 * and if b didn't overwrite it, then a didn't also. 647 * case 2b: 0 <= b < a < N 648 * write num records starting at a, which wraps around 0=N 649 * and overwrite fri unconditionally. Now from case 2a, 650 * this means that b eclipsed fri to overwrite it and wrap 651 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 652 * set fri = b + 1 (mod N). 653 * Now, since fri is updated in every case, except the trivial case 0, 654 * the number of records present in the table after writing, is, 655 * num_recs - 1 = b - fri (mod N), and we take the positive value, 656 * by adding an arbitrary multiple of N before taking the modulo N 657 * as shown below. 658 */ 659 a = control->ras_fri + control->ras_num_recs; 660 b = a + num - 1; 661 if (b < control->ras_max_record_count) { 662 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 663 } else if (a < control->ras_max_record_count) { 664 u32 g0, g1; 665 666 g0 = control->ras_max_record_count - a; 667 g1 = b % control->ras_max_record_count + 1; 668 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 669 if (res) 670 goto Out; 671 res = __amdgpu_ras_eeprom_write(control, 672 buf + g0 * RAS_TABLE_RECORD_SIZE, 673 0, g1); 674 if (res) 675 goto Out; 676 if (g1 > control->ras_fri) 677 control->ras_fri = g1 % control->ras_max_record_count; 678 } else { 679 a %= control->ras_max_record_count; 680 b %= control->ras_max_record_count; 681 682 if (a <= b) { 683 /* Note that, b - a + 1 = num. */ 684 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 685 if (res) 686 goto Out; 687 if (b >= control->ras_fri) 688 control->ras_fri = (b + 1) % control->ras_max_record_count; 689 } else { 690 u32 g0, g1; 691 692 /* b < a, which means, we write from 693 * a to the end of the table, and from 694 * the start of the table to b. 695 */ 696 g0 = control->ras_max_record_count - a; 697 g1 = b + 1; 698 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 699 if (res) 700 goto Out; 701 res = __amdgpu_ras_eeprom_write(control, 702 buf + g0 * RAS_TABLE_RECORD_SIZE, 703 0, g1); 704 if (res) 705 goto Out; 706 control->ras_fri = g1 % control->ras_max_record_count; 707 } 708 } 709 control->ras_num_recs = 1 + (control->ras_max_record_count + b 710 - control->ras_fri) 711 % control->ras_max_record_count; 712 Out: 713 kfree(buf); 714 return res; 715 } 716 717 static int 718 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 719 { 720 struct amdgpu_device *adev = to_amdgpu_device(control); 721 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 722 u8 *buf, *pp, csum; 723 u32 buf_size; 724 int res; 725 726 /* Modify the header if it exceeds. 727 */ 728 if (amdgpu_bad_page_threshold != 0 && 729 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 730 dev_warn(adev->dev, 731 "Saved bad pages %d reaches threshold value %d\n", 732 control->ras_num_recs, ras->bad_page_cnt_threshold); 733 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 734 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { 735 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 736 control->tbl_rai.health_percent = 0; 737 } 738 } 739 740 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 741 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 742 RAS_TABLE_V2_1_INFO_SIZE + 743 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 744 else 745 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 746 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 747 control->tbl_hdr.checksum = 0; 748 749 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 750 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 751 if (!buf) { 752 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 753 control->tbl_hdr.tbl_size); 754 res = -ENOMEM; 755 goto Out; 756 } 757 758 down_read(&adev->reset_domain->sem); 759 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 760 control->i2c_address + 761 control->ras_record_offset, 762 buf, buf_size); 763 up_read(&adev->reset_domain->sem); 764 if (res < 0) { 765 DRM_ERROR("EEPROM failed reading records:%d\n", 766 res); 767 goto Out; 768 } else if (res < buf_size) { 769 DRM_ERROR("EEPROM read %d out of %d bytes\n", 770 res, buf_size); 771 res = -EIO; 772 goto Out; 773 } 774 775 /** 776 * bad page records have been stored in eeprom, 777 * now calculate gpu health percent 778 */ 779 if (amdgpu_bad_page_threshold != 0 && 780 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && 781 control->ras_num_recs < ras->bad_page_cnt_threshold) 782 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 783 control->ras_num_recs) * 100) / 784 ras->bad_page_cnt_threshold; 785 786 /* Recalc the checksum. 787 */ 788 csum = 0; 789 for (pp = buf; pp < buf + buf_size; pp++) 790 csum += *pp; 791 792 csum += __calc_hdr_byte_sum(control); 793 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 794 csum += __calc_ras_info_byte_sum(control); 795 /* avoid sign extension when assigning to "checksum" */ 796 csum = -csum; 797 control->tbl_hdr.checksum = csum; 798 res = __write_table_header(control); 799 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 800 res = __write_table_ras_info(control); 801 Out: 802 kfree(buf); 803 return res; 804 } 805 806 /** 807 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 808 * @control: pointer to control structure 809 * @record: array of records to append 810 * @num: number of records in @record array 811 * 812 * Append @num records to the table, calculate the checksum and write 813 * the table back to EEPROM. The maximum number of records that 814 * can be appended is between 1 and control->ras_max_record_count, 815 * regardless of how many records are already stored in the table. 816 * 817 * Return 0 on success or if EEPROM is not supported, -errno on error. 818 */ 819 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 820 struct eeprom_table_record *record, 821 const u32 num) 822 { 823 struct amdgpu_device *adev = to_amdgpu_device(control); 824 int res; 825 826 if (!__is_ras_eeprom_supported(adev)) 827 return 0; 828 829 if (num == 0) { 830 DRM_ERROR("will not append 0 records\n"); 831 return -EINVAL; 832 } else if (num > control->ras_max_record_count) { 833 DRM_ERROR("cannot append %d records than the size of table %d\n", 834 num, control->ras_max_record_count); 835 return -EINVAL; 836 } 837 838 mutex_lock(&control->ras_tbl_mutex); 839 840 res = amdgpu_ras_eeprom_append_table(control, record, num); 841 if (!res) 842 res = amdgpu_ras_eeprom_update_header(control); 843 if (!res) 844 amdgpu_ras_debugfs_set_ret_size(control); 845 846 mutex_unlock(&control->ras_tbl_mutex); 847 return res; 848 } 849 850 /** 851 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 852 * @control: pointer to control structure 853 * @buf: pointer to buffer to read into 854 * @fri: first record index, start reading at this index, absolute index 855 * @num: number of records to read 856 * 857 * The caller must hold the table mutex in @control. 858 * Return 0 on success, -errno otherwise. 859 */ 860 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 861 u8 *buf, const u32 fri, const u32 num) 862 { 863 struct amdgpu_device *adev = to_amdgpu_device(control); 864 u32 buf_size; 865 int res; 866 867 /* i2c may be unstable in gpu reset */ 868 down_read(&adev->reset_domain->sem); 869 buf_size = num * RAS_TABLE_RECORD_SIZE; 870 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 871 control->i2c_address + 872 RAS_INDEX_TO_OFFSET(control, fri), 873 buf, buf_size); 874 up_read(&adev->reset_domain->sem); 875 if (res < 0) { 876 DRM_ERROR("Reading %d EEPROM table records error:%d", 877 num, res); 878 } else if (res < buf_size) { 879 /* Short read, return error. 880 */ 881 DRM_ERROR("Read %d records out of %d", 882 res / RAS_TABLE_RECORD_SIZE, num); 883 res = -EIO; 884 } else { 885 res = 0; 886 } 887 888 return res; 889 } 890 891 /** 892 * amdgpu_ras_eeprom_read -- read EEPROM 893 * @control: pointer to control structure 894 * @record: array of records to read into 895 * @num: number of records in @record 896 * 897 * Reads num records from the RAS table in EEPROM and 898 * writes the data into @record array. 899 * 900 * Returns 0 on success, -errno on error. 901 */ 902 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 903 struct eeprom_table_record *record, 904 const u32 num) 905 { 906 struct amdgpu_device *adev = to_amdgpu_device(control); 907 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 908 int i, res; 909 u8 *buf, *pp; 910 u32 g0, g1; 911 912 if (!__is_ras_eeprom_supported(adev)) 913 return 0; 914 915 if (num == 0) { 916 DRM_ERROR("will not read 0 records\n"); 917 return -EINVAL; 918 } else if (num > control->ras_num_recs) { 919 DRM_ERROR("too many records to read:%d available:%d\n", 920 num, control->ras_num_recs); 921 return -EINVAL; 922 } 923 924 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 925 if (!buf) 926 return -ENOMEM; 927 928 /* Determine how many records to read, from the first record 929 * index, fri, to the end of the table, and from the beginning 930 * of the table, such that the total number of records is 931 * @num, and we handle wrap around when fri > 0 and 932 * fri + num > RAS_MAX_RECORD_COUNT. 933 * 934 * First we compute the index of the last element 935 * which would be fetched from each region, 936 * g0 is in [fri, fri + num - 1], and 937 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 938 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 939 * the last element to fetch, we set g0 to _the number_ 940 * of elements to fetch, @num, since we know that the last 941 * indexed to be fetched does not exceed the table. 942 * 943 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 944 * we set g0 to the number of elements to read 945 * until the end of the table, and g1 to the number of 946 * elements to read from the beginning of the table. 947 */ 948 g0 = control->ras_fri + num - 1; 949 g1 = g0 % control->ras_max_record_count; 950 if (g0 < control->ras_max_record_count) { 951 g0 = num; 952 g1 = 0; 953 } else { 954 g0 = control->ras_max_record_count - control->ras_fri; 955 g1 += 1; 956 } 957 958 mutex_lock(&control->ras_tbl_mutex); 959 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 960 if (res) 961 goto Out; 962 if (g1) { 963 res = __amdgpu_ras_eeprom_read(control, 964 buf + g0 * RAS_TABLE_RECORD_SIZE, 965 0, g1); 966 if (res) 967 goto Out; 968 } 969 970 res = 0; 971 972 /* Read up everything? Then transform. 973 */ 974 pp = buf; 975 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 976 __decode_table_record_from_buf(control, &record[i], pp); 977 978 /* update bad channel bitmap */ 979 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 980 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 981 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 982 con->update_channel_flag = true; 983 } 984 } 985 Out: 986 kfree(buf); 987 mutex_unlock(&control->ras_tbl_mutex); 988 989 return res; 990 } 991 992 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 993 { 994 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 995 return RAS_MAX_RECORD_COUNT_V2_1; 996 else 997 return RAS_MAX_RECORD_COUNT; 998 } 999 1000 static ssize_t 1001 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1002 size_t size, loff_t *pos) 1003 { 1004 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1005 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1006 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1007 u8 data[50]; 1008 int res; 1009 1010 if (!size) 1011 return size; 1012 1013 if (!ras || !control) { 1014 res = snprintf(data, sizeof(data), "Not supported\n"); 1015 } else { 1016 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1017 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1018 } 1019 1020 if (*pos >= res) 1021 return 0; 1022 1023 res -= *pos; 1024 res = min_t(size_t, res, size); 1025 1026 if (copy_to_user(buf, &data[*pos], res)) 1027 return -EFAULT; 1028 1029 *pos += res; 1030 1031 return res; 1032 } 1033 1034 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1035 .owner = THIS_MODULE, 1036 .read = amdgpu_ras_debugfs_eeprom_size_read, 1037 .write = NULL, 1038 .llseek = default_llseek, 1039 }; 1040 1041 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1042 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1043 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1044 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1045 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1046 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1047 1048 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1049 "ignore", 1050 "re", 1051 "ue", 1052 }; 1053 1054 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1055 { 1056 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1057 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1058 } 1059 1060 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1061 { 1062 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1063 eeprom_control); 1064 struct dentry *de = ras->de_ras_eeprom_table; 1065 1066 if (de) 1067 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1068 } 1069 1070 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1071 size_t size, loff_t *pos) 1072 { 1073 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1074 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1075 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1076 const size_t orig_size = size; 1077 int res = -EFAULT; 1078 size_t data_len; 1079 1080 mutex_lock(&control->ras_tbl_mutex); 1081 1082 /* We want *pos - data_len > 0, which means there's 1083 * bytes to be printed from data. 1084 */ 1085 data_len = strlen(tbl_hdr_str); 1086 if (*pos < data_len) { 1087 data_len -= *pos; 1088 data_len = min_t(size_t, data_len, size); 1089 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1090 goto Out; 1091 buf += data_len; 1092 size -= data_len; 1093 *pos += data_len; 1094 } 1095 1096 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1097 if (*pos < data_len && size > 0) { 1098 u8 data[tbl_hdr_fmt_size + 1]; 1099 loff_t lpos; 1100 1101 snprintf(data, sizeof(data), tbl_hdr_fmt, 1102 control->tbl_hdr.header, 1103 control->tbl_hdr.version, 1104 control->tbl_hdr.first_rec_offset, 1105 control->tbl_hdr.tbl_size, 1106 control->tbl_hdr.checksum); 1107 1108 data_len -= *pos; 1109 data_len = min_t(size_t, data_len, size); 1110 lpos = *pos - strlen(tbl_hdr_str); 1111 if (copy_to_user(buf, &data[lpos], data_len)) 1112 goto Out; 1113 buf += data_len; 1114 size -= data_len; 1115 *pos += data_len; 1116 } 1117 1118 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1119 if (*pos < data_len && size > 0) { 1120 loff_t lpos; 1121 1122 data_len -= *pos; 1123 data_len = min_t(size_t, data_len, size); 1124 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1125 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1126 goto Out; 1127 buf += data_len; 1128 size -= data_len; 1129 *pos += data_len; 1130 } 1131 1132 data_len = amdgpu_ras_debugfs_table_size(control); 1133 if (*pos < data_len && size > 0) { 1134 u8 dare[RAS_TABLE_RECORD_SIZE]; 1135 u8 data[rec_hdr_fmt_size + 1]; 1136 struct eeprom_table_record record; 1137 int s, r; 1138 1139 /* Find the starting record index 1140 */ 1141 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1142 strlen(rec_hdr_str); 1143 s = s / rec_hdr_fmt_size; 1144 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1145 strlen(rec_hdr_str); 1146 r = r % rec_hdr_fmt_size; 1147 1148 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1149 u32 ai = RAS_RI_TO_AI(control, s); 1150 /* Read a single record 1151 */ 1152 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1153 if (res) 1154 goto Out; 1155 __decode_table_record_from_buf(control, &record, dare); 1156 snprintf(data, sizeof(data), rec_hdr_fmt, 1157 s, 1158 RAS_INDEX_TO_OFFSET(control, ai), 1159 record_err_type_str[record.err_type], 1160 record.bank, 1161 record.ts, 1162 record.offset, 1163 record.mem_channel, 1164 record.mcumc_id, 1165 record.retired_page); 1166 1167 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1168 if (copy_to_user(buf, &data[r], data_len)) { 1169 res = -EFAULT; 1170 goto Out; 1171 } 1172 buf += data_len; 1173 size -= data_len; 1174 *pos += data_len; 1175 r = 0; 1176 } 1177 } 1178 res = 0; 1179 Out: 1180 mutex_unlock(&control->ras_tbl_mutex); 1181 return res < 0 ? res : orig_size - size; 1182 } 1183 1184 static ssize_t 1185 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1186 size_t size, loff_t *pos) 1187 { 1188 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1189 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1190 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1191 u8 data[81]; 1192 int res; 1193 1194 if (!size) 1195 return size; 1196 1197 if (!ras || !control) { 1198 res = snprintf(data, sizeof(data), "Not supported\n"); 1199 if (*pos >= res) 1200 return 0; 1201 1202 res -= *pos; 1203 res = min_t(size_t, res, size); 1204 1205 if (copy_to_user(buf, &data[*pos], res)) 1206 return -EFAULT; 1207 1208 *pos += res; 1209 1210 return res; 1211 } else { 1212 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1213 } 1214 } 1215 1216 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1217 .owner = THIS_MODULE, 1218 .read = amdgpu_ras_debugfs_eeprom_table_read, 1219 .write = NULL, 1220 .llseek = default_llseek, 1221 }; 1222 1223 /** 1224 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1225 * @control: pointer to control structure 1226 * 1227 * Check the checksum of the stored in EEPROM RAS table. 1228 * 1229 * Return 0 if the checksum is correct, 1230 * positive if it is not correct, and 1231 * -errno on I/O error. 1232 */ 1233 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1234 { 1235 struct amdgpu_device *adev = to_amdgpu_device(control); 1236 int buf_size, res; 1237 u8 csum, *buf, *pp; 1238 1239 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1240 buf_size = RAS_TABLE_HEADER_SIZE + 1241 RAS_TABLE_V2_1_INFO_SIZE + 1242 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1243 else 1244 buf_size = RAS_TABLE_HEADER_SIZE + 1245 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1246 1247 buf = kzalloc(buf_size, GFP_KERNEL); 1248 if (!buf) { 1249 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1250 return -ENOMEM; 1251 } 1252 1253 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1254 control->i2c_address + 1255 control->ras_header_offset, 1256 buf, buf_size); 1257 if (res < buf_size) { 1258 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1259 /* On partial reads, return -EIO. 1260 */ 1261 if (res >= 0) 1262 res = -EIO; 1263 goto Out; 1264 } 1265 1266 csum = 0; 1267 for (pp = buf; pp < buf + buf_size; pp++) 1268 csum += *pp; 1269 Out: 1270 kfree(buf); 1271 return res < 0 ? res : csum; 1272 } 1273 1274 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1275 { 1276 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1277 struct amdgpu_device *adev = to_amdgpu_device(control); 1278 unsigned char *buf; 1279 int res; 1280 1281 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1282 if (!buf) { 1283 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1284 return -ENOMEM; 1285 } 1286 1287 /** 1288 * EEPROM table V2_1 supports ras info, 1289 * read EEPROM table ras info 1290 */ 1291 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1292 control->i2c_address + control->ras_info_offset, 1293 buf, RAS_TABLE_V2_1_INFO_SIZE); 1294 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1295 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1296 res = res >= 0 ? -EIO : res; 1297 goto Out; 1298 } 1299 1300 __decode_table_ras_info_from_buf(rai, buf); 1301 1302 Out: 1303 kfree(buf); 1304 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1305 } 1306 1307 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 1308 bool *exceed_err_limit) 1309 { 1310 struct amdgpu_device *adev = to_amdgpu_device(control); 1311 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1312 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1313 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1314 int res; 1315 1316 *exceed_err_limit = false; 1317 1318 if (!__is_ras_eeprom_supported(adev)) 1319 return 0; 1320 1321 /* Verify i2c adapter is initialized */ 1322 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1323 return -ENOENT; 1324 1325 if (!__get_eeprom_i2c_addr(adev, control)) 1326 return -EINVAL; 1327 1328 control->ras_header_offset = RAS_HDR_START; 1329 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1330 mutex_init(&control->ras_tbl_mutex); 1331 1332 /* Read the table header from EEPROM address */ 1333 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1334 control->i2c_address + control->ras_header_offset, 1335 buf, RAS_TABLE_HEADER_SIZE); 1336 if (res < RAS_TABLE_HEADER_SIZE) { 1337 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1338 return res >= 0 ? -EIO : res; 1339 } 1340 1341 __decode_table_header_from_buf(hdr, buf); 1342 1343 if (hdr->version == RAS_TABLE_VER_V2_1) { 1344 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1345 control->ras_record_offset = RAS_RECORD_START_V2_1; 1346 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1347 } else { 1348 control->ras_num_recs = RAS_NUM_RECS(hdr); 1349 control->ras_record_offset = RAS_RECORD_START; 1350 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1351 } 1352 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1353 1354 if (hdr->header == RAS_TABLE_HDR_VAL) { 1355 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1356 control->ras_num_recs); 1357 1358 if (hdr->version == RAS_TABLE_VER_V2_1) { 1359 res = __read_table_ras_info(control); 1360 if (res) 1361 return res; 1362 } 1363 1364 res = __verify_ras_table_checksum(control); 1365 if (res) 1366 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1367 res); 1368 1369 /* Warn if we are at 90% of the threshold or above 1370 */ 1371 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1372 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1373 control->ras_num_recs, 1374 ras->bad_page_cnt_threshold); 1375 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1376 amdgpu_bad_page_threshold != 0) { 1377 if (hdr->version == RAS_TABLE_VER_V2_1) { 1378 res = __read_table_ras_info(control); 1379 if (res) 1380 return res; 1381 } 1382 1383 res = __verify_ras_table_checksum(control); 1384 if (res) 1385 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1386 res); 1387 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1388 /* This means that, the threshold was increased since 1389 * the last time the system was booted, and now, 1390 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1391 * so that at least one more record can be saved, 1392 * before the page count threshold is reached. 1393 */ 1394 dev_info(adev->dev, 1395 "records:%d threshold:%d, resetting " 1396 "RAS table header signature", 1397 control->ras_num_recs, 1398 ras->bad_page_cnt_threshold); 1399 res = amdgpu_ras_eeprom_correct_header_tag(control, 1400 RAS_TABLE_HDR_VAL); 1401 } else { 1402 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1403 control->ras_num_recs, ras->bad_page_cnt_threshold); 1404 if (amdgpu_bad_page_threshold == -1) { 1405 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1."); 1406 res = 0; 1407 } else { 1408 *exceed_err_limit = true; 1409 dev_err(adev->dev, 1410 "RAS records:%d exceed threshold:%d, " 1411 "GPU will not be initialized. Replace this GPU or increase the threshold", 1412 control->ras_num_recs, ras->bad_page_cnt_threshold); 1413 } 1414 } 1415 } else { 1416 DRM_INFO("Creating a new EEPROM table"); 1417 1418 res = amdgpu_ras_eeprom_reset_table(control); 1419 } 1420 1421 return res < 0 ? res : 0; 1422 } 1423