1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 #include "amdgpu_ras_mgr.h" 36 37 /* These are memory addresses as would be seen by one or more EEPROM 38 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 39 * set of EEPROM devices. They form a continuous memory space. 40 * 41 * The I2C device address includes the device type identifier, 1010b, 42 * which is a reserved value and indicates that this is an I2C EEPROM 43 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 44 * address, namely bits 18, 17, and 16. This makes up the 7 bit 45 * address sent on the I2C bus with bit 0 being the direction bit, 46 * which is not represented here, and sent by the hardware directly. 47 * 48 * For instance, 49 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 50 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 51 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 52 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 53 * address memory in a device or a device on the I2C bus, depending on 54 * the status of pins 1-3. See top of amdgpu_eeprom.c. 55 * 56 * The RAS table lives either at address 0 or address 40000h of EEPROM. 57 */ 58 #define EEPROM_I2C_MADDR_0 0x0 59 #define EEPROM_I2C_MADDR_4 0x40000 60 61 /* 62 * The 2 macros below represent the actual size in bytes that 63 * those entities occupy in the EEPROM memory. 64 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 65 * uses uint64 to store 6b fields such as retired_page. 66 */ 67 #define RAS_TABLE_HEADER_SIZE 20 68 #define RAS_TABLE_RECORD_SIZE 24 69 70 /* Table hdr is 'AMDR' */ 71 #define RAS_TABLE_HDR_VAL 0x414d4452 72 73 /* Bad GPU tag ‘BADG’ */ 74 #define RAS_TABLE_HDR_BAD 0x42414447 75 76 /* 77 * EEPROM Table structure v1 78 * --------------------------------- 79 * | | 80 * | EEPROM TABLE HEADER | 81 * | ( size 20 Bytes ) | 82 * | | 83 * --------------------------------- 84 * | | 85 * | BAD PAGE RECORD AREA | 86 * | | 87 * --------------------------------- 88 */ 89 90 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 91 #define RAS_TBL_SIZE_BYTES (256 * 1024) 92 #define RAS_TABLE_START 0 93 #define RAS_HDR_START RAS_TABLE_START 94 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 95 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 96 / RAS_TABLE_RECORD_SIZE) 97 98 /* 99 * EEPROM Table structrue v2.1 100 * --------------------------------- 101 * | | 102 * | EEPROM TABLE HEADER | 103 * | ( size 20 Bytes ) | 104 * | | 105 * --------------------------------- 106 * | | 107 * | EEPROM TABLE RAS INFO | 108 * | (available info size 4 Bytes) | 109 * | ( reserved size 252 Bytes ) | 110 * | | 111 * --------------------------------- 112 * | | 113 * | BAD PAGE RECORD AREA | 114 * | | 115 * --------------------------------- 116 */ 117 118 /* EEPROM Table V2_1 */ 119 #define RAS_TABLE_V2_1_INFO_SIZE 256 120 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 121 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 122 RAS_TABLE_V2_1_INFO_SIZE) 123 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 124 RAS_TABLE_V2_1_INFO_SIZE) \ 125 / RAS_TABLE_RECORD_SIZE) 126 127 #define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */ 128 129 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 130 * offset off of RAS_TABLE_START. That is, this is something you can 131 * add to control->i2c_address, and then tell I2C layer to read 132 * from/write to there. _N is the so called absolute index, 133 * because it starts right after the table header. 134 */ 135 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 136 (_N) * RAS_TABLE_RECORD_SIZE) 137 138 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 139 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 140 141 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 142 * of "fri", return the absolute record index off of the end of 143 * the table header. 144 */ 145 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 146 (_C)->ras_max_record_count) 147 148 #define RAS_NUM_RECS(_tbl_hdr) \ 149 (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE) ? 0u : \ 150 (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)) 151 152 #define RAS_NUM_RECS_V2_1(_tbl_hdr) \ 153 (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE + \ 154 RAS_TABLE_V2_1_INFO_SIZE) ? 0u : \ 155 (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE - \ 156 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)) 157 158 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 159 160 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 161 { 162 if (amdgpu_sriov_vf(adev)) 163 return false; 164 165 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 166 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 167 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 168 case IP_VERSION(13, 0, 0): 169 case IP_VERSION(13, 0, 2): /* Aldebaran */ 170 case IP_VERSION(13, 0, 10): 171 return true; 172 case IP_VERSION(13, 0, 6): 173 case IP_VERSION(13, 0, 12): 174 case IP_VERSION(13, 0, 14): 175 return (adev->gmc.is_app_apu) ? false : true; 176 default: 177 return false; 178 } 179 } 180 181 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 182 struct amdgpu_ras_eeprom_control *control) 183 { 184 struct atom_context *atom_ctx = adev->mode_info.atom_context; 185 u8 i2c_addr; 186 187 if (!control) 188 return false; 189 190 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 191 /* The address given by VBIOS is an 8-bit, wire-format 192 * address, i.e. the most significant byte. 193 * 194 * Normalize it to a 19-bit EEPROM address. Remove the 195 * device type identifier and make it a 7-bit address; 196 * then make it a 19-bit EEPROM address. See top of 197 * amdgpu_eeprom.c. 198 */ 199 i2c_addr = (i2c_addr & 0x0F) >> 1; 200 control->i2c_address = ((u32) i2c_addr) << 16; 201 202 return true; 203 } 204 205 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 206 case IP_VERSION(11, 0, 2): 207 /* VEGA20 and ARCTURUS */ 208 if (adev->asic_type == CHIP_VEGA20) 209 control->i2c_address = EEPROM_I2C_MADDR_0; 210 else if (strnstr(atom_ctx->vbios_pn, 211 "D342", 212 sizeof(atom_ctx->vbios_pn))) 213 control->i2c_address = EEPROM_I2C_MADDR_0; 214 else 215 control->i2c_address = EEPROM_I2C_MADDR_4; 216 return true; 217 case IP_VERSION(11, 0, 7): 218 control->i2c_address = EEPROM_I2C_MADDR_0; 219 return true; 220 case IP_VERSION(13, 0, 2): 221 if (strnstr(atom_ctx->vbios_pn, "D673", 222 sizeof(atom_ctx->vbios_pn))) 223 control->i2c_address = EEPROM_I2C_MADDR_4; 224 else 225 control->i2c_address = EEPROM_I2C_MADDR_0; 226 return true; 227 case IP_VERSION(13, 0, 0): 228 if (strnstr(atom_ctx->vbios_pn, "D707", 229 sizeof(atom_ctx->vbios_pn))) 230 control->i2c_address = EEPROM_I2C_MADDR_0; 231 else 232 control->i2c_address = EEPROM_I2C_MADDR_4; 233 return true; 234 case IP_VERSION(13, 0, 6): 235 case IP_VERSION(13, 0, 10): 236 case IP_VERSION(13, 0, 12): 237 case IP_VERSION(13, 0, 14): 238 control->i2c_address = EEPROM_I2C_MADDR_4; 239 return true; 240 default: 241 return false; 242 } 243 } 244 245 static void 246 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 247 unsigned char *buf) 248 { 249 u32 *pp = (uint32_t *)buf; 250 251 pp[0] = cpu_to_le32(hdr->header); 252 pp[1] = cpu_to_le32(hdr->version); 253 pp[2] = cpu_to_le32(hdr->first_rec_offset); 254 pp[3] = cpu_to_le32(hdr->tbl_size); 255 pp[4] = cpu_to_le32(hdr->checksum); 256 } 257 258 static void 259 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 260 unsigned char *buf) 261 { 262 u32 *pp = (uint32_t *)buf; 263 264 hdr->header = le32_to_cpu(pp[0]); 265 hdr->version = le32_to_cpu(pp[1]); 266 hdr->first_rec_offset = le32_to_cpu(pp[2]); 267 hdr->tbl_size = le32_to_cpu(pp[3]); 268 hdr->checksum = le32_to_cpu(pp[4]); 269 } 270 271 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 272 { 273 u8 buf[RAS_TABLE_HEADER_SIZE]; 274 struct amdgpu_device *adev = to_amdgpu_device(control); 275 int res; 276 277 memset(buf, 0, sizeof(buf)); 278 __encode_table_header_to_buf(&control->tbl_hdr, buf); 279 280 /* i2c may be unstable in gpu reset */ 281 down_read(&adev->reset_domain->sem); 282 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 283 control->i2c_address + 284 control->ras_header_offset, 285 buf, RAS_TABLE_HEADER_SIZE); 286 up_read(&adev->reset_domain->sem); 287 288 if (res < 0) { 289 dev_err(adev->dev, "Failed to write EEPROM table header:%d", 290 res); 291 } else if (res < RAS_TABLE_HEADER_SIZE) { 292 dev_err(adev->dev, "Short write:%d out of %d\n", res, 293 RAS_TABLE_HEADER_SIZE); 294 res = -EIO; 295 } else { 296 res = 0; 297 } 298 299 return res; 300 } 301 302 static void 303 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 304 unsigned char *buf) 305 { 306 u32 *pp = (uint32_t *)buf; 307 u32 tmp; 308 309 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 310 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 311 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 312 pp[0] = cpu_to_le32(tmp); 313 } 314 315 static void 316 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 317 unsigned char *buf) 318 { 319 u32 *pp = (uint32_t *)buf; 320 u32 tmp; 321 322 tmp = le32_to_cpu(pp[0]); 323 rai->rma_status = tmp & 0xFF; 324 rai->health_percent = (tmp >> 8) & 0xFF; 325 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 326 } 327 328 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 329 { 330 struct amdgpu_device *adev = to_amdgpu_device(control); 331 u8 *buf; 332 int res; 333 334 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 335 if (!buf) { 336 dev_err(adev->dev, 337 "Failed to alloc buf to write table ras info\n"); 338 return -ENOMEM; 339 } 340 341 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 342 343 /* i2c may be unstable in gpu reset */ 344 down_read(&adev->reset_domain->sem); 345 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 346 control->i2c_address + 347 control->ras_info_offset, 348 buf, RAS_TABLE_V2_1_INFO_SIZE); 349 up_read(&adev->reset_domain->sem); 350 351 if (res < 0) { 352 dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", 353 res); 354 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 355 dev_err(adev->dev, "Short write:%d out of %d\n", res, 356 RAS_TABLE_V2_1_INFO_SIZE); 357 res = -EIO; 358 } else { 359 res = 0; 360 } 361 362 kfree(buf); 363 364 return res; 365 } 366 367 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 368 { 369 int ii; 370 u8 *pp, csum; 371 size_t sz; 372 373 /* Header checksum, skip checksum field in the calculation */ 374 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 375 pp = (u8 *) &control->tbl_hdr; 376 csum = 0; 377 for (ii = 0; ii < sz; ii++, pp++) 378 csum += *pp; 379 380 return csum; 381 } 382 383 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 384 { 385 int ii; 386 u8 *pp, csum; 387 size_t sz; 388 389 sz = sizeof(control->tbl_rai); 390 pp = (u8 *) &control->tbl_rai; 391 csum = 0; 392 for (ii = 0; ii < sz; ii++, pp++) 393 csum += *pp; 394 395 return csum; 396 } 397 398 static int amdgpu_ras_eeprom_correct_header_tag( 399 struct amdgpu_ras_eeprom_control *control, 400 uint32_t header) 401 { 402 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 403 u8 *hh; 404 int res; 405 u8 csum; 406 407 csum = -hdr->checksum; 408 409 hh = (void *) &hdr->header; 410 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 411 hh = (void *) &header; 412 csum += hh[0] + hh[1] + hh[2] + hh[3]; 413 csum = -csum; 414 mutex_lock(&control->ras_tbl_mutex); 415 hdr->header = header; 416 hdr->checksum = csum; 417 res = __write_table_header(control); 418 mutex_unlock(&control->ras_tbl_mutex); 419 420 return res; 421 } 422 423 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 424 { 425 struct amdgpu_device *adev = to_amdgpu_device(control); 426 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 427 428 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 429 case IP_VERSION(8, 10, 0): 430 hdr->version = RAS_TABLE_VER_V2_1; 431 return; 432 case IP_VERSION(12, 0, 0): 433 case IP_VERSION(12, 5, 0): 434 hdr->version = RAS_TABLE_VER_V3; 435 return; 436 default: 437 hdr->version = RAS_TABLE_VER_V1; 438 return; 439 } 440 } 441 442 /** 443 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 444 * @control: pointer to control structure 445 * 446 * Reset the contents of the header of the RAS EEPROM table. 447 * Return 0 on success, -errno on error. 448 */ 449 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 450 { 451 struct amdgpu_device *adev = to_amdgpu_device(control); 452 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 453 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 454 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 455 u32 erase_res = 0; 456 u8 csum; 457 int res; 458 459 mutex_lock(&control->ras_tbl_mutex); 460 461 if (!amdgpu_ras_smu_eeprom_supported(adev)) { 462 hdr->header = RAS_TABLE_HDR_VAL; 463 amdgpu_ras_set_eeprom_table_version(control); 464 465 if (hdr->version >= RAS_TABLE_VER_V2_1) { 466 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 467 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 468 RAS_TABLE_V2_1_INFO_SIZE; 469 rai->rma_status = GPU_HEALTH_USABLE; 470 471 control->ras_record_offset = RAS_RECORD_START_V2_1; 472 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 473 /** 474 * GPU health represented as a percentage. 475 * 0 means worst health, 100 means fully health. 476 */ 477 rai->health_percent = 100; 478 /* ecc_page_threshold = 0 means disable bad page retirement */ 479 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 480 } else { 481 hdr->first_rec_offset = RAS_RECORD_START; 482 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 483 484 control->ras_record_offset = RAS_RECORD_START; 485 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 486 } 487 488 csum = __calc_hdr_byte_sum(control); 489 if (hdr->version >= RAS_TABLE_VER_V2_1) 490 csum += __calc_ras_info_byte_sum(control); 491 csum = -csum; 492 hdr->checksum = csum; 493 res = __write_table_header(control); 494 if (!res && hdr->version > RAS_TABLE_VER_V1) 495 res = __write_table_ras_info(control); 496 } else { 497 res = amdgpu_ras_smu_erase_ras_table(adev, &erase_res); 498 if (res || erase_res) { 499 dev_warn(adev->dev, "RAS EEPROM reset failed, res:%d result:%d", 500 res, erase_res); 501 if (!res) 502 res = -EIO; 503 } 504 } 505 506 control->ras_num_recs = 0; 507 control->ras_num_bad_pages = 0; 508 control->ras_num_mca_recs = 0; 509 control->ras_num_pa_recs = 0; 510 control->ras_fri = 0; 511 512 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); 513 514 control->bad_channel_bitmap = 0; 515 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 516 con->update_channel_flag = false; 517 /* there is no record on eeprom now, clear the counter */ 518 if (con->eh_data) 519 con->eh_data->count_saved = 0; 520 521 amdgpu_ras_debugfs_set_ret_size(control); 522 523 mutex_unlock(&control->ras_tbl_mutex); 524 525 return res; 526 } 527 528 static void 529 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 530 struct eeprom_table_record *record, 531 unsigned char *buf) 532 { 533 __le64 tmp = 0; 534 int i = 0; 535 536 /* Next are all record fields according to EEPROM page spec in LE foramt */ 537 buf[i++] = record->err_type; 538 539 buf[i++] = record->bank; 540 541 tmp = cpu_to_le64(record->ts); 542 memcpy(buf + i, &tmp, 8); 543 i += 8; 544 545 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 546 memcpy(buf + i, &tmp, 6); 547 i += 6; 548 549 buf[i++] = record->mem_channel; 550 buf[i++] = record->mcumc_id; 551 552 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 553 memcpy(buf + i, &tmp, 6); 554 } 555 556 static void 557 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 558 struct eeprom_table_record *record, 559 unsigned char *buf) 560 { 561 __le64 tmp = 0; 562 int i = 0; 563 564 /* Next are all record fields according to EEPROM page spec in LE foramt */ 565 record->err_type = buf[i++]; 566 567 record->bank = buf[i++]; 568 569 memcpy(&tmp, buf + i, 8); 570 record->ts = le64_to_cpu(tmp); 571 i += 8; 572 573 memcpy(&tmp, buf + i, 6); 574 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 575 i += 6; 576 577 record->mem_channel = buf[i++]; 578 record->mcumc_id = buf[i++]; 579 580 memcpy(&tmp, buf + i, 6); 581 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 582 } 583 584 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 585 { 586 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 587 588 if (amdgpu_uniras_enabled(adev)) 589 return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev); 590 591 if (!__is_ras_eeprom_supported(adev) || 592 !amdgpu_bad_page_threshold) 593 return false; 594 595 /* skip check eeprom table for VEGA20 Gaming */ 596 if (!con) 597 return false; 598 else 599 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 600 return false; 601 602 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 603 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold) 604 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 605 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold); 606 if ((amdgpu_bad_page_threshold == -1) || 607 (amdgpu_bad_page_threshold == -2)) { 608 dev_warn(adev->dev, 609 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 610 return false; 611 } else { 612 dev_warn(adev->dev, 613 "Please consider adjusting the customized threshold.\n"); 614 return true; 615 } 616 } 617 618 return false; 619 } 620 621 /** 622 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 623 * @control: pointer to control structure 624 * @buf: pointer to buffer containing data to write 625 * @fri: start writing at this index 626 * @num: number of records to write 627 * 628 * The caller must hold the table mutex in @control. 629 * Return 0 on success, -errno otherwise. 630 */ 631 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 632 u8 *buf, const u32 fri, const u32 num) 633 { 634 struct amdgpu_device *adev = to_amdgpu_device(control); 635 u32 buf_size; 636 int res; 637 638 /* i2c may be unstable in gpu reset */ 639 down_read(&adev->reset_domain->sem); 640 buf_size = num * RAS_TABLE_RECORD_SIZE; 641 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 642 control->i2c_address + 643 RAS_INDEX_TO_OFFSET(control, fri), 644 buf, buf_size); 645 up_read(&adev->reset_domain->sem); 646 if (res < 0) { 647 dev_err(adev->dev, "Writing %d EEPROM table records error:%d", 648 num, res); 649 } else if (res < buf_size) { 650 /* Short write, return error. 651 */ 652 dev_err(adev->dev, "Wrote %d records out of %d", 653 res / RAS_TABLE_RECORD_SIZE, num); 654 res = -EIO; 655 } else { 656 res = 0; 657 } 658 659 return res; 660 } 661 662 static int 663 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 664 struct eeprom_table_record *record, 665 const u32 num) 666 { 667 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 668 struct amdgpu_device *adev = to_amdgpu_device(control); 669 u32 a, b, i; 670 u8 *buf, *pp; 671 int res; 672 673 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 674 if (!buf) 675 return -ENOMEM; 676 677 /* Encode all of them in one go. 678 */ 679 pp = buf; 680 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 681 __encode_table_record_to_buf(control, &record[i], pp); 682 683 /* update bad channel bitmap */ 684 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 685 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 686 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 687 con->update_channel_flag = true; 688 } 689 } 690 691 /* a, first record index to write into. 692 * b, last record index to write into. 693 * a = first index to read (fri) + number of records in the table, 694 * b = a + @num - 1. 695 * Let N = control->ras_max_num_record_count, then we have, 696 * case 0: 0 <= a <= b < N, 697 * just append @num records starting at a; 698 * case 1: 0 <= a < N <= b, 699 * append (N - a) records starting at a, and 700 * append the remainder, b % N + 1, starting at 0. 701 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 702 * case 2a: 0 <= a <= b < N 703 * append num records starting at a; and fix fri if b overwrote it, 704 * and since a <= b, if b overwrote it then a must've also, 705 * and if b didn't overwrite it, then a didn't also. 706 * case 2b: 0 <= b < a < N 707 * write num records starting at a, which wraps around 0=N 708 * and overwrite fri unconditionally. Now from case 2a, 709 * this means that b eclipsed fri to overwrite it and wrap 710 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 711 * set fri = b + 1 (mod N). 712 * Now, since fri is updated in every case, except the trivial case 0, 713 * the number of records present in the table after writing, is, 714 * num_recs - 1 = b - fri (mod N), and we take the positive value, 715 * by adding an arbitrary multiple of N before taking the modulo N 716 * as shown below. 717 */ 718 a = control->ras_fri + control->ras_num_recs; 719 b = a + num - 1; 720 if (b < control->ras_max_record_count) { 721 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 722 } else if (a < control->ras_max_record_count) { 723 u32 g0, g1; 724 725 g0 = control->ras_max_record_count - a; 726 g1 = b % control->ras_max_record_count + 1; 727 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 728 if (res) 729 goto Out; 730 res = __amdgpu_ras_eeprom_write(control, 731 buf + g0 * RAS_TABLE_RECORD_SIZE, 732 0, g1); 733 if (res) 734 goto Out; 735 if (g1 > control->ras_fri) 736 control->ras_fri = g1 % control->ras_max_record_count; 737 } else { 738 a %= control->ras_max_record_count; 739 b %= control->ras_max_record_count; 740 741 if (a <= b) { 742 /* Note that, b - a + 1 = num. */ 743 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 744 if (res) 745 goto Out; 746 if (b >= control->ras_fri) 747 control->ras_fri = (b + 1) % control->ras_max_record_count; 748 } else { 749 u32 g0, g1; 750 751 /* b < a, which means, we write from 752 * a to the end of the table, and from 753 * the start of the table to b. 754 */ 755 g0 = control->ras_max_record_count - a; 756 g1 = b + 1; 757 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 758 if (res) 759 goto Out; 760 res = __amdgpu_ras_eeprom_write(control, 761 buf + g0 * RAS_TABLE_RECORD_SIZE, 762 0, g1); 763 if (res) 764 goto Out; 765 control->ras_fri = g1 % control->ras_max_record_count; 766 } 767 } 768 control->ras_num_recs = 1 + (control->ras_max_record_count + b 769 - control->ras_fri) 770 % control->ras_max_record_count; 771 772 /*old asics only save pa to eeprom like before*/ 773 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) 774 control->ras_num_pa_recs += num; 775 else 776 control->ras_num_mca_recs += num; 777 778 control->ras_num_bad_pages = con->bad_page_num; 779 Out: 780 kfree(buf); 781 return res; 782 } 783 784 static int 785 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 786 { 787 struct amdgpu_device *adev = to_amdgpu_device(control); 788 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 789 u8 *buf, *pp, csum; 790 u32 buf_size; 791 int res; 792 793 /* Modify the header if it exceeds. 794 */ 795 if (amdgpu_bad_page_threshold != 0 && 796 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 797 dev_warn(adev->dev, 798 "Saved bad pages %d reaches threshold value %d\n", 799 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 800 801 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev) && 802 amdgpu_cper_generate_bp_threshold_record(adev)) 803 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 804 805 if ((amdgpu_bad_page_threshold != -1) && 806 (amdgpu_bad_page_threshold != -2)) { 807 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 808 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 809 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 810 control->tbl_rai.health_percent = 0; 811 } 812 ras->is_rma = true; 813 } 814 815 /* ignore the -ENOTSUPP return value */ 816 amdgpu_dpm_send_rma_reason(adev); 817 } 818 819 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 820 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 821 RAS_TABLE_V2_1_INFO_SIZE + 822 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 823 else 824 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 825 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 826 control->tbl_hdr.checksum = 0; 827 828 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 829 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 830 if (!buf) { 831 dev_err(adev->dev, 832 "allocating memory for table of size %d bytes failed\n", 833 control->tbl_hdr.tbl_size); 834 res = -ENOMEM; 835 goto Out; 836 } 837 838 down_read(&adev->reset_domain->sem); 839 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 840 control->i2c_address + 841 control->ras_record_offset, 842 buf, buf_size); 843 up_read(&adev->reset_domain->sem); 844 if (res < 0) { 845 dev_err(adev->dev, "EEPROM failed reading records:%d\n", res); 846 goto Out; 847 } else if (res < buf_size) { 848 dev_err(adev->dev, "EEPROM read %d out of %d bytes\n", res, 849 buf_size); 850 res = -EIO; 851 goto Out; 852 } 853 854 /** 855 * bad page records have been stored in eeprom, 856 * now calculate gpu health percent 857 */ 858 if (amdgpu_bad_page_threshold != 0 && 859 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 860 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) 861 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 862 control->ras_num_bad_pages) * 100) / 863 ras->bad_page_cnt_threshold; 864 865 /* Recalc the checksum. 866 */ 867 csum = 0; 868 for (pp = buf; pp < buf + buf_size; pp++) 869 csum += *pp; 870 871 csum += __calc_hdr_byte_sum(control); 872 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 873 csum += __calc_ras_info_byte_sum(control); 874 /* avoid sign extension when assigning to "checksum" */ 875 csum = -csum; 876 control->tbl_hdr.checksum = csum; 877 res = __write_table_header(control); 878 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 879 res = __write_table_ras_info(control); 880 Out: 881 kfree(buf); 882 return res; 883 } 884 885 int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) 886 { 887 struct amdgpu_device *adev = to_amdgpu_device(control); 888 int ret, retry = 20; 889 890 if (!amdgpu_ras_smu_eeprom_supported(adev)) 891 return 0; 892 893 control->ras_num_recs_old = control->ras_num_recs; 894 895 do { 896 /* 1000ms timeout is long enough, smu_get_badpage_count won't 897 * return -EBUSY before timeout. 898 */ 899 ret = amdgpu_ras_smu_get_badpage_count(adev, 900 &(control->ras_num_recs), RAS_SMU_MESSAGE_TIMEOUT_MS); 901 if (!ret && 902 (control->ras_num_recs_old == control->ras_num_recs)) { 903 /* record number update in PMFW needs some time, 904 * smu_get_badpage_count may return immediately without 905 * count update, sleep for a while and retry again. 906 */ 907 msleep(50); 908 retry--; 909 } else { 910 break; 911 } 912 } while (retry); 913 914 /* no update of record number is not a real failure, 915 * don't print warning here 916 */ 917 if (!ret && (control->ras_num_recs_old == control->ras_num_recs)) 918 ret = -EINVAL; 919 920 return ret; 921 } 922 923 static int amdgpu_ras_smu_eeprom_append(struct amdgpu_ras_eeprom_control *control) 924 { 925 struct amdgpu_device *adev = to_amdgpu_device(control); 926 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 927 928 if (!amdgpu_ras_smu_eeprom_supported(adev) || !con) 929 return 0; 930 931 control->ras_num_bad_pages = con->bad_page_num; 932 933 if (amdgpu_bad_page_threshold != 0 && 934 control->ras_num_bad_pages > con->bad_page_cnt_threshold) { 935 dev_warn(adev->dev, 936 "Saved bad pages %d reaches threshold value %d\n", 937 control->ras_num_bad_pages, con->bad_page_cnt_threshold); 938 939 if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev)) 940 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 941 942 if ((amdgpu_bad_page_threshold != -1) && 943 (amdgpu_bad_page_threshold != -2)) 944 con->is_rma = true; 945 } 946 947 return 0; 948 } 949 950 /** 951 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 952 * @control: pointer to control structure 953 * @record: array of records to append 954 * @num: number of records in @record array 955 * 956 * Append @num records to the table, calculate the checksum and write 957 * the table back to EEPROM. The maximum number of records that 958 * can be appended is between 1 and control->ras_max_record_count, 959 * regardless of how many records are already stored in the table. 960 * 961 * Return 0 on success or if EEPROM is not supported, -errno on error. 962 */ 963 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 964 struct eeprom_table_record *record, 965 const u32 num) 966 { 967 struct amdgpu_device *adev = to_amdgpu_device(control); 968 int res, i; 969 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 970 971 if (!__is_ras_eeprom_supported(adev)) 972 return 0; 973 974 if (amdgpu_ras_smu_eeprom_supported(adev)) 975 return amdgpu_ras_smu_eeprom_append(control); 976 977 if (num == 0) { 978 dev_err(adev->dev, "will not append 0 records\n"); 979 return -EINVAL; 980 } else if (num > control->ras_max_record_count) { 981 dev_err(adev->dev, 982 "cannot append %d records than the size of table %d\n", 983 num, control->ras_max_record_count); 984 return -EINVAL; 985 } 986 987 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 988 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 989 990 /* set the new channel index flag */ 991 for (i = 0; i < num; i++) 992 record[i].retired_page |= (nps << UMC_NPS_SHIFT); 993 994 mutex_lock(&control->ras_tbl_mutex); 995 996 res = amdgpu_ras_eeprom_append_table(control, record, num); 997 if (!res) 998 res = amdgpu_ras_eeprom_update_header(control); 999 if (!res) 1000 amdgpu_ras_debugfs_set_ret_size(control); 1001 1002 mutex_unlock(&control->ras_tbl_mutex); 1003 1004 /* clear channel index flag, the flag is only saved on eeprom */ 1005 for (i = 0; i < num; i++) 1006 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT); 1007 1008 return res; 1009 } 1010 1011 /** 1012 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 1013 * @control: pointer to control structure 1014 * @buf: pointer to buffer to read into 1015 * @fri: first record index, start reading at this index, absolute index 1016 * @num: number of records to read 1017 * 1018 * The caller must hold the table mutex in @control. 1019 * Return 0 on success, -errno otherwise. 1020 */ 1021 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 1022 u8 *buf, const u32 fri, const u32 num) 1023 { 1024 struct amdgpu_device *adev = to_amdgpu_device(control); 1025 u32 buf_size; 1026 int res; 1027 1028 /* i2c may be unstable in gpu reset */ 1029 down_read(&adev->reset_domain->sem); 1030 buf_size = num * RAS_TABLE_RECORD_SIZE; 1031 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1032 control->i2c_address + 1033 RAS_INDEX_TO_OFFSET(control, fri), 1034 buf, buf_size); 1035 up_read(&adev->reset_domain->sem); 1036 if (res < 0) { 1037 dev_err(adev->dev, "Reading %d EEPROM table records error:%d", 1038 num, res); 1039 } else if (res < buf_size) { 1040 /* Short read, return error. 1041 */ 1042 dev_err(adev->dev, "Read %d records out of %d", 1043 res / RAS_TABLE_RECORD_SIZE, num); 1044 res = -EIO; 1045 } else { 1046 res = 0; 1047 } 1048 1049 return res; 1050 } 1051 1052 int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, 1053 struct eeprom_table_record *record, u32 rec_idx, 1054 const u32 num) 1055 { 1056 struct amdgpu_device *adev = to_amdgpu_device(control); 1057 uint64_t ts, end_idx; 1058 int i, ret; 1059 u64 mca, ipid; 1060 u32 cu, mem_channel, mcumc_id; 1061 1062 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1063 return 0; 1064 1065 if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) 1066 return -EOPNOTSUPP; 1067 1068 end_idx = rec_idx + num; 1069 for (i = rec_idx; i < end_idx; i++) { 1070 ret = amdgpu_ras_smu_get_badpage_mca_addr(adev, i, &mca); 1071 if (ret) 1072 return ret; 1073 1074 ret = amdgpu_ras_smu_get_badpage_ipid(adev, i, &ipid); 1075 if (ret) 1076 return ret; 1077 1078 ret = amdgpu_ras_smu_get_timestamp(adev, i, &ts); 1079 if (ret) 1080 return ret; 1081 1082 record[i - rec_idx].address = mca; 1083 /* retired_page (pa) is unused now */ 1084 record[i - rec_idx].retired_page = 0x1ULL; 1085 record[i - rec_idx].ts = ts; 1086 record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 1087 1088 adev->umc.ras->mca_ipid_parse(adev, ipid, 1089 &cu, &mem_channel, &mcumc_id, NULL); 1090 record[i - rec_idx].cu = (u8)cu; 1091 record[i - rec_idx].mem_channel = (u8)mem_channel; 1092 record[i - rec_idx].mcumc_id = (u8)mcumc_id; 1093 } 1094 1095 return 0; 1096 } 1097 1098 /** 1099 * amdgpu_ras_eeprom_read -- read EEPROM 1100 * @control: pointer to control structure 1101 * @record: array of records to read into 1102 * @num: number of records in @record 1103 * 1104 * Reads num records from the RAS table in EEPROM and 1105 * writes the data into @record array. 1106 * 1107 * Returns 0 on success, -errno on error. 1108 */ 1109 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 1110 struct eeprom_table_record *record, 1111 const u32 num) 1112 { 1113 struct amdgpu_device *adev = to_amdgpu_device(control); 1114 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1115 int i, res; 1116 u8 *buf, *pp; 1117 u32 g0, g1; 1118 1119 if (amdgpu_ras_smu_eeprom_supported(adev)) 1120 return amdgpu_ras_eeprom_read_idx(control, record, 0, num); 1121 1122 if (!__is_ras_eeprom_supported(adev)) 1123 return 0; 1124 1125 if (num == 0) { 1126 dev_err(adev->dev, "will not read 0 records\n"); 1127 return -EINVAL; 1128 } else if (num > control->ras_num_recs) { 1129 dev_err(adev->dev, "too many records to read:%d available:%d\n", 1130 num, control->ras_num_recs); 1131 return -EINVAL; 1132 } 1133 1134 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 1135 if (!buf) 1136 return -ENOMEM; 1137 1138 /* Determine how many records to read, from the first record 1139 * index, fri, to the end of the table, and from the beginning 1140 * of the table, such that the total number of records is 1141 * @num, and we handle wrap around when fri > 0 and 1142 * fri + num > RAS_MAX_RECORD_COUNT. 1143 * 1144 * First we compute the index of the last element 1145 * which would be fetched from each region, 1146 * g0 is in [fri, fri + num - 1], and 1147 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 1148 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 1149 * the last element to fetch, we set g0 to _the number_ 1150 * of elements to fetch, @num, since we know that the last 1151 * indexed to be fetched does not exceed the table. 1152 * 1153 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 1154 * we set g0 to the number of elements to read 1155 * until the end of the table, and g1 to the number of 1156 * elements to read from the beginning of the table. 1157 */ 1158 g0 = control->ras_fri + num - 1; 1159 g1 = g0 % control->ras_max_record_count; 1160 if (g0 < control->ras_max_record_count) { 1161 g0 = num; 1162 g1 = 0; 1163 } else { 1164 g0 = control->ras_max_record_count - control->ras_fri; 1165 g1 += 1; 1166 } 1167 1168 mutex_lock(&control->ras_tbl_mutex); 1169 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 1170 if (res) 1171 goto Out; 1172 if (g1) { 1173 res = __amdgpu_ras_eeprom_read(control, 1174 buf + g0 * RAS_TABLE_RECORD_SIZE, 1175 0, g1); 1176 if (res) 1177 goto Out; 1178 } 1179 1180 res = 0; 1181 1182 /* Read up everything? Then transform. 1183 */ 1184 pp = buf; 1185 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 1186 __decode_table_record_from_buf(control, &record[i], pp); 1187 1188 /* update bad channel bitmap */ 1189 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1190 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1191 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1192 con->update_channel_flag = true; 1193 } 1194 } 1195 Out: 1196 kfree(buf); 1197 mutex_unlock(&control->ras_tbl_mutex); 1198 1199 return res; 1200 } 1201 1202 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1203 { 1204 /* get available eeprom table version first before eeprom table init */ 1205 amdgpu_ras_set_eeprom_table_version(control); 1206 1207 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1208 return RAS_MAX_RECORD_COUNT_V2_1; 1209 else 1210 return RAS_MAX_RECORD_COUNT; 1211 } 1212 1213 static ssize_t 1214 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1215 size_t size, loff_t *pos) 1216 { 1217 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1218 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1219 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1220 u8 data[50]; 1221 int res; 1222 1223 if (!size) 1224 return size; 1225 1226 if (!ras || !control) { 1227 res = snprintf(data, sizeof(data), "Not supported\n"); 1228 } else { 1229 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1230 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1231 } 1232 1233 if (*pos >= res) 1234 return 0; 1235 1236 res -= *pos; 1237 res = min_t(size_t, res, size); 1238 1239 if (copy_to_user(buf, &data[*pos], res)) 1240 return -EFAULT; 1241 1242 *pos += res; 1243 1244 return res; 1245 } 1246 1247 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1248 .owner = THIS_MODULE, 1249 .read = amdgpu_ras_debugfs_eeprom_size_read, 1250 .write = NULL, 1251 .llseek = default_llseek, 1252 }; 1253 1254 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1255 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1256 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1257 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1258 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1259 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1260 1261 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1262 "ignore", 1263 "re", 1264 "ue", 1265 }; 1266 1267 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1268 { 1269 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1270 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1271 } 1272 1273 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1274 { 1275 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1276 eeprom_control); 1277 struct dentry *de = ras->de_ras_eeprom_table; 1278 1279 if (de) 1280 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1281 } 1282 1283 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1284 size_t size, loff_t *pos) 1285 { 1286 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1287 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1288 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1289 const size_t orig_size = size; 1290 int res = -EFAULT; 1291 size_t data_len; 1292 1293 /* pmfw manages eeprom data by itself */ 1294 if (amdgpu_ras_smu_eeprom_supported(adev)) 1295 return 0; 1296 1297 mutex_lock(&control->ras_tbl_mutex); 1298 1299 /* We want *pos - data_len > 0, which means there's 1300 * bytes to be printed from data. 1301 */ 1302 data_len = strlen(tbl_hdr_str); 1303 if (*pos < data_len) { 1304 data_len -= *pos; 1305 data_len = min_t(size_t, data_len, size); 1306 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1307 goto Out; 1308 buf += data_len; 1309 size -= data_len; 1310 *pos += data_len; 1311 } 1312 1313 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1314 if (*pos < data_len && size > 0) { 1315 u8 data[tbl_hdr_fmt_size + 1]; 1316 loff_t lpos; 1317 1318 snprintf(data, sizeof(data), tbl_hdr_fmt, 1319 control->tbl_hdr.header, 1320 control->tbl_hdr.version, 1321 control->tbl_hdr.first_rec_offset, 1322 control->tbl_hdr.tbl_size, 1323 control->tbl_hdr.checksum); 1324 1325 data_len -= *pos; 1326 data_len = min_t(size_t, data_len, size); 1327 lpos = *pos - strlen(tbl_hdr_str); 1328 if (copy_to_user(buf, &data[lpos], data_len)) 1329 goto Out; 1330 buf += data_len; 1331 size -= data_len; 1332 *pos += data_len; 1333 } 1334 1335 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1336 if (*pos < data_len && size > 0) { 1337 loff_t lpos; 1338 1339 data_len -= *pos; 1340 data_len = min_t(size_t, data_len, size); 1341 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1342 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1343 goto Out; 1344 buf += data_len; 1345 size -= data_len; 1346 *pos += data_len; 1347 } 1348 1349 data_len = amdgpu_ras_debugfs_table_size(control); 1350 if (*pos < data_len && size > 0) { 1351 u8 dare[RAS_TABLE_RECORD_SIZE]; 1352 u8 data[rec_hdr_fmt_size + 1]; 1353 struct eeprom_table_record record; 1354 int s, r; 1355 1356 /* Find the starting record index 1357 */ 1358 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1359 strlen(rec_hdr_str); 1360 s = s / rec_hdr_fmt_size; 1361 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1362 strlen(rec_hdr_str); 1363 r = r % rec_hdr_fmt_size; 1364 1365 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1366 u32 ai = RAS_RI_TO_AI(control, s); 1367 /* Read a single record 1368 */ 1369 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1370 if (res) 1371 goto Out; 1372 __decode_table_record_from_buf(control, &record, dare); 1373 snprintf(data, sizeof(data), rec_hdr_fmt, 1374 s, 1375 RAS_INDEX_TO_OFFSET(control, ai), 1376 record_err_type_str[record.err_type], 1377 record.bank, 1378 record.ts, 1379 record.offset, 1380 record.mem_channel, 1381 record.mcumc_id, 1382 record.retired_page); 1383 1384 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1385 if (copy_to_user(buf, &data[r], data_len)) { 1386 res = -EFAULT; 1387 goto Out; 1388 } 1389 buf += data_len; 1390 size -= data_len; 1391 *pos += data_len; 1392 r = 0; 1393 } 1394 } 1395 res = 0; 1396 Out: 1397 mutex_unlock(&control->ras_tbl_mutex); 1398 return res < 0 ? res : orig_size - size; 1399 } 1400 1401 static ssize_t 1402 amdgpu_ras_debugfs_table_read_uniras(struct amdgpu_device *adev, 1403 char __user *buf, 1404 size_t size, loff_t *pos) 1405 { 1406 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 1407 struct ras_core_context *ras_core = ras_mgr ? ras_mgr->ras_core : NULL; 1408 struct eeprom_umc_record *records = NULL; 1409 struct ras_eeprom_control *control; 1410 size_t bufsz, len = 0; 1411 u32 num_recs; 1412 char *kbuf; 1413 ssize_t res; 1414 int i; 1415 1416 if (!ras_core) 1417 return 0; 1418 1419 /* pmfw manages eeprom data by itself */ 1420 if (ras_fw_eeprom_supported(ras_core)) 1421 return 0; 1422 1423 control = &ras_core->ras_eeprom; 1424 num_recs = ras_eeprom_get_record_count(ras_core); 1425 1426 bufsz = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1427 strlen(rec_hdr_str) + (size_t)rec_hdr_fmt_size * num_recs + 1; 1428 1429 kbuf = kvmalloc(bufsz, GFP_KERNEL); 1430 if (!kbuf) 1431 return -ENOMEM; 1432 1433 if (num_recs) { 1434 records = kvcalloc(num_recs, sizeof(*records), GFP_KERNEL); 1435 if (!records) { 1436 res = -ENOMEM; 1437 goto out; 1438 } 1439 1440 res = ras_eeprom_read(ras_core, records, num_recs); 1441 if (res) 1442 goto out; 1443 } 1444 1445 len += scnprintf(kbuf + len, bufsz - len, "%s", tbl_hdr_str); 1446 len += scnprintf(kbuf + len, bufsz - len, tbl_hdr_fmt, 1447 control->tbl_hdr.header, 1448 control->tbl_hdr.version, 1449 control->tbl_hdr.first_rec_offset, 1450 control->tbl_hdr.tbl_size, 1451 control->tbl_hdr.checksum); 1452 len += scnprintf(kbuf + len, bufsz - len, "%s", rec_hdr_str); 1453 1454 for (i = 0; i < num_recs; i++) { 1455 u32 ai = RAS_RI_TO_AI(control, i); 1456 int et = records[i].err_type; 1457 const char *ets = (et >= 0 && et < AMDGPU_RAS_EEPROM_ERR_COUNT) ? 1458 record_err_type_str[et] : "na"; 1459 1460 len += scnprintf(kbuf + len, bufsz - len, rec_hdr_fmt, 1461 i, 1462 RAS_INDEX_TO_OFFSET(control, ai), 1463 ets, 1464 records[i].bank, 1465 records[i].ts, 1466 records[i].offset, 1467 records[i].mem_channel, 1468 records[i].mcumc_id, 1469 records[i].retired_row_pfn); 1470 } 1471 1472 res = simple_read_from_buffer(buf, size, pos, kbuf, len); 1473 1474 out: 1475 kvfree(records); 1476 kvfree(kbuf); 1477 1478 return res; 1479 } 1480 1481 static ssize_t 1482 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1483 size_t size, loff_t *pos) 1484 { 1485 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1486 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1487 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1488 u8 data[81]; 1489 int res; 1490 1491 if (!size) 1492 return size; 1493 1494 if (amdgpu_uniras_enabled(adev)) 1495 return amdgpu_ras_debugfs_table_read_uniras(adev, buf, 1496 size, pos); 1497 1498 if (!ras || !control) { 1499 res = snprintf(data, sizeof(data), "Not supported\n"); 1500 if (*pos >= res) 1501 return 0; 1502 1503 res -= *pos; 1504 res = min_t(size_t, res, size); 1505 1506 if (copy_to_user(buf, &data[*pos], res)) 1507 return -EFAULT; 1508 1509 *pos += res; 1510 1511 return res; 1512 } else { 1513 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1514 } 1515 } 1516 1517 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1518 .owner = THIS_MODULE, 1519 .read = amdgpu_ras_debugfs_eeprom_table_read, 1520 .write = NULL, 1521 .llseek = default_llseek, 1522 }; 1523 1524 /** 1525 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1526 * @control: pointer to control structure 1527 * 1528 * Check the checksum of the stored in EEPROM RAS table. 1529 * 1530 * Return 0 if the checksum is correct, 1531 * positive if it is not correct, and 1532 * -errno on I/O error. 1533 */ 1534 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1535 { 1536 struct amdgpu_device *adev = to_amdgpu_device(control); 1537 int buf_size, res; 1538 u8 csum, *buf, *pp; 1539 1540 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1541 buf_size = RAS_TABLE_HEADER_SIZE + 1542 RAS_TABLE_V2_1_INFO_SIZE + 1543 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1544 else 1545 buf_size = RAS_TABLE_HEADER_SIZE + 1546 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1547 1548 buf = kzalloc(buf_size, GFP_KERNEL); 1549 if (!buf) { 1550 dev_err(adev->dev, 1551 "Out of memory checking RAS table checksum.\n"); 1552 return -ENOMEM; 1553 } 1554 1555 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1556 control->i2c_address + 1557 control->ras_header_offset, 1558 buf, buf_size); 1559 if (res < buf_size) { 1560 dev_err(adev->dev, "Partial read for checksum, res:%d\n", res); 1561 /* On partial reads, return -EIO. 1562 */ 1563 if (res >= 0) 1564 res = -EIO; 1565 goto Out; 1566 } 1567 1568 csum = 0; 1569 for (pp = buf; pp < buf + buf_size; pp++) 1570 csum += *pp; 1571 Out: 1572 kfree(buf); 1573 return res < 0 ? res : csum; 1574 } 1575 1576 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1577 { 1578 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1579 struct amdgpu_device *adev = to_amdgpu_device(control); 1580 unsigned char *buf; 1581 int res; 1582 1583 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1584 if (!buf) { 1585 dev_err(adev->dev, 1586 "Failed to alloc buf to read EEPROM table ras info\n"); 1587 return -ENOMEM; 1588 } 1589 1590 /** 1591 * EEPROM table V2_1 supports ras info, 1592 * read EEPROM table ras info 1593 */ 1594 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1595 control->i2c_address + control->ras_info_offset, 1596 buf, RAS_TABLE_V2_1_INFO_SIZE); 1597 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1598 dev_err(adev->dev, 1599 "Failed to read EEPROM table ras info, res:%d", res); 1600 res = res >= 0 ? -EIO : res; 1601 goto Out; 1602 } 1603 1604 __decode_table_ras_info_from_buf(rai, buf); 1605 1606 Out: 1607 kfree(buf); 1608 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1609 } 1610 1611 static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1612 { 1613 struct amdgpu_device *adev = to_amdgpu_device(control); 1614 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1615 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1616 uint64_t local_time; 1617 int res; 1618 1619 ras->is_rma = false; 1620 1621 if (!__is_ras_eeprom_supported(adev)) 1622 return 0; 1623 mutex_init(&control->ras_tbl_mutex); 1624 1625 res = amdgpu_ras_smu_get_table_version(adev, &(hdr->version)); 1626 if (res) 1627 return res; 1628 1629 res = amdgpu_ras_smu_get_badpage_count(adev, 1630 &(control->ras_num_recs), 100); 1631 if (res) 1632 return res; 1633 1634 local_time = (uint64_t)ktime_get_real_seconds(); 1635 res = amdgpu_ras_smu_set_timestamp(adev, local_time); 1636 if (res) 1637 return res; 1638 1639 control->ras_max_record_count = 4000; 1640 1641 control->ras_num_mca_recs = 0; 1642 control->ras_num_pa_recs = 0; 1643 1644 return 0; 1645 } 1646 1647 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1648 { 1649 struct amdgpu_device *adev = to_amdgpu_device(control); 1650 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1651 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1652 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1653 int dev_var = adev->pdev->device & 0xF; 1654 uint32_t vram_type = adev->gmc.vram_type; 1655 int res; 1656 1657 if (amdgpu_ras_smu_eeprom_supported(adev)) 1658 return amdgpu_ras_smu_eeprom_init(control); 1659 1660 ras->is_rma = false; 1661 1662 if (!__is_ras_eeprom_supported(adev)) 1663 return 0; 1664 1665 /* Verify i2c adapter is initialized */ 1666 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1667 return -ENOENT; 1668 1669 if (!__get_eeprom_i2c_addr(adev, control)) 1670 return -EINVAL; 1671 1672 control->ras_header_offset = RAS_HDR_START; 1673 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1674 mutex_init(&control->ras_tbl_mutex); 1675 1676 /* Read the table header from EEPROM address */ 1677 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1678 control->i2c_address + control->ras_header_offset, 1679 buf, RAS_TABLE_HEADER_SIZE); 1680 if (res < RAS_TABLE_HEADER_SIZE) { 1681 dev_err(adev->dev, "Failed to read EEPROM table header, res:%d", 1682 res); 1683 return res >= 0 ? -EIO : res; 1684 } 1685 1686 __decode_table_header_from_buf(hdr, buf); 1687 1688 if (hdr->header != RAS_TABLE_HDR_VAL && 1689 hdr->header != RAS_TABLE_HDR_BAD) { 1690 dev_info(adev->dev, "Creating a new EEPROM table"); 1691 return amdgpu_ras_eeprom_reset_table(control); 1692 } 1693 1694 if (!(adev->flags & AMD_IS_APU) && (dev_var == 0x5) && 1695 (vram_type == AMDGPU_VRAM_TYPE_HBM3E) && 1696 (hdr->version < RAS_TABLE_VER_V3)) { 1697 return amdgpu_ras_eeprom_reset_table(control); 1698 } 1699 1700 switch (hdr->version) { 1701 case RAS_TABLE_VER_V2_1: 1702 case RAS_TABLE_VER_V3: 1703 if (hdr->tbl_size < RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE) { 1704 dev_err(adev->dev, 1705 "RAS header invalid, tbl_size %u smaller than minimum %u, resetting table\n", 1706 hdr->tbl_size, 1707 RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE); 1708 return amdgpu_ras_eeprom_reset_table(control); 1709 } 1710 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1711 control->ras_record_offset = RAS_RECORD_START_V2_1; 1712 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1713 break; 1714 case RAS_TABLE_VER_V1: 1715 if (hdr->tbl_size < RAS_TABLE_HEADER_SIZE) { 1716 dev_err(adev->dev, 1717 "RAS header invalid, tbl_size %u smaller than minimum %u, resetting table\n", 1718 hdr->tbl_size, RAS_TABLE_HEADER_SIZE); 1719 return amdgpu_ras_eeprom_reset_table(control); 1720 } 1721 control->ras_num_recs = RAS_NUM_RECS(hdr); 1722 control->ras_record_offset = RAS_RECORD_START; 1723 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1724 break; 1725 default: 1726 dev_err(adev->dev, 1727 "RAS header invalid, unsupported version: %u", 1728 hdr->version); 1729 return -EINVAL; 1730 } 1731 1732 if (control->ras_num_recs > control->ras_max_record_count) { 1733 dev_err(adev->dev, 1734 "RAS header invalid, records in header: %u max allowed :%u", 1735 control->ras_num_recs, control->ras_max_record_count); 1736 return -EINVAL; 1737 } 1738 1739 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1740 if (hdr->first_rec_offset < control->ras_record_offset || 1741 control->ras_fri >= control->ras_max_record_count) { 1742 dev_err(adev->dev, 1743 "RAS header invalid, ras_fri: %u, first_rec_offset:0x%x", 1744 control->ras_fri, hdr->first_rec_offset); 1745 return -EINVAL; 1746 } 1747 1748 control->ras_num_mca_recs = 0; 1749 control->ras_num_pa_recs = 0; 1750 return 0; 1751 } 1752 1753 static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1754 { 1755 struct amdgpu_device *adev = to_amdgpu_device(control); 1756 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1757 1758 if (!__is_ras_eeprom_supported(adev)) 1759 return 0; 1760 1761 control->ras_num_bad_pages = ras->bad_page_num; 1762 1763 if ((ras->bad_page_cnt_threshold < control->ras_num_bad_pages) && 1764 amdgpu_bad_page_threshold != 0) { 1765 dev_warn(adev->dev, 1766 "RAS records:%d exceed threshold:%d\n", 1767 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1768 if ((amdgpu_bad_page_threshold == -1) || 1769 (amdgpu_bad_page_threshold == -2)) { 1770 dev_warn(adev->dev, 1771 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1772 } else { 1773 ras->is_rma = true; 1774 dev_warn(adev->dev, 1775 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1776 } 1777 1778 return 0; 1779 } 1780 1781 dev_dbg(adev->dev, 1782 "Found existing EEPROM table with %d records", 1783 control->ras_num_bad_pages); 1784 1785 /* Warn if we are at 90% of the threshold or above 1786 */ 1787 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1788 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1789 control->ras_num_bad_pages, 1790 ras->bad_page_cnt_threshold); 1791 return 0; 1792 } 1793 1794 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1795 { 1796 struct amdgpu_device *adev = to_amdgpu_device(control); 1797 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1798 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1799 int res = 0; 1800 1801 if (amdgpu_ras_smu_eeprom_supported(adev)) 1802 return amdgpu_ras_smu_eeprom_check(control); 1803 1804 if (!__is_ras_eeprom_supported(adev)) 1805 return 0; 1806 1807 /* Verify i2c adapter is initialized */ 1808 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1809 return -ENOENT; 1810 1811 if (!__get_eeprom_i2c_addr(adev, control)) 1812 return -EINVAL; 1813 1814 control->ras_num_bad_pages = ras->bad_page_num; 1815 1816 if (hdr->header == RAS_TABLE_HDR_VAL) { 1817 dev_dbg(adev->dev, 1818 "Found existing EEPROM table with %d records", 1819 control->ras_num_bad_pages); 1820 1821 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1822 res = __read_table_ras_info(control); 1823 if (res) 1824 return res; 1825 } 1826 1827 res = __verify_ras_table_checksum(control); 1828 if (res) { 1829 dev_err(adev->dev, 1830 "RAS table incorrect checksum or error:%d\n", 1831 res); 1832 return -EINVAL; 1833 } 1834 1835 /* Warn if we are at 90% of the threshold or above 1836 */ 1837 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1838 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1839 control->ras_num_bad_pages, 1840 ras->bad_page_cnt_threshold); 1841 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1842 amdgpu_bad_page_threshold != 0) { 1843 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1844 res = __read_table_ras_info(control); 1845 if (res) 1846 return res; 1847 } 1848 1849 res = __verify_ras_table_checksum(control); 1850 if (res) { 1851 dev_err(adev->dev, 1852 "RAS Table incorrect checksum or error:%d\n", 1853 res); 1854 return -EINVAL; 1855 } 1856 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { 1857 /* This means that, the threshold was increased since 1858 * the last time the system was booted, and now, 1859 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1860 * so that at least one more record can be saved, 1861 * before the page count threshold is reached. 1862 */ 1863 dev_info(adev->dev, 1864 "records:%d threshold:%d, resetting " 1865 "RAS table header signature", 1866 control->ras_num_bad_pages, 1867 ras->bad_page_cnt_threshold); 1868 res = amdgpu_ras_eeprom_correct_header_tag(control, 1869 RAS_TABLE_HDR_VAL); 1870 } else { 1871 dev_warn(adev->dev, 1872 "RAS records:%d exceed threshold:%d\n", 1873 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1874 if ((amdgpu_bad_page_threshold == -1) || 1875 (amdgpu_bad_page_threshold == -2)) { 1876 res = 0; 1877 dev_warn(adev->dev, 1878 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1879 } else { 1880 ras->is_rma = true; 1881 dev_warn(adev->dev, 1882 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1883 } 1884 } 1885 } 1886 1887 return res < 0 ? res : 0; 1888 } 1889 1890 void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev) 1891 { 1892 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1893 struct amdgpu_ras_eeprom_control *control; 1894 int res; 1895 1896 if (!__is_ras_eeprom_supported(adev) || !ras || 1897 amdgpu_ras_smu_eeprom_supported(adev)) 1898 return; 1899 control = &ras->eeprom_control; 1900 if (!control->is_eeprom_valid) 1901 return; 1902 res = __verify_ras_table_checksum(control); 1903 if (res) { 1904 dev_warn(adev->dev, 1905 "RAS table incorrect checksum or error:%d, try to recover\n", 1906 res); 1907 if (!amdgpu_ras_eeprom_reset_table(control)) 1908 if (!amdgpu_ras_save_bad_pages(adev, NULL)) 1909 if (!__verify_ras_table_checksum(control)) { 1910 dev_info(adev->dev, "RAS table recovery succeed\n"); 1911 return; 1912 } 1913 dev_err(adev->dev, "RAS table recovery failed\n"); 1914 control->is_eeprom_valid = false; 1915 } 1916 return; 1917 } 1918 1919 static const struct ras_smu_drv *amdgpu_ras_get_smu_ras_drv(struct amdgpu_device *adev) 1920 { 1921 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1922 1923 if (!ras) 1924 return NULL; 1925 1926 return ras->ras_smu_drv; 1927 } 1928 1929 static uint64_t amdgpu_ras_smu_get_feature_flags(struct amdgpu_device *adev) 1930 { 1931 const struct ras_smu_drv *ras_smu_drv = amdgpu_ras_get_smu_ras_drv(adev); 1932 uint64_t flags = 0ULL; 1933 1934 if (!ras_smu_drv) 1935 goto out; 1936 1937 if (ras_smu_drv->ras_smu_feature_flags) 1938 ras_smu_drv->ras_smu_feature_flags(adev, &flags); 1939 1940 out: 1941 return flags; 1942 } 1943 1944 bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev) 1945 { 1946 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1947 uint64_t flags = 0ULL; 1948 1949 if (!__is_ras_eeprom_supported(adev) || !smu_ras_drv) 1950 return false; 1951 1952 if (!smu_ras_drv->smu_eeprom_funcs) 1953 return false; 1954 1955 flags = amdgpu_ras_smu_get_feature_flags(adev); 1956 1957 return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM); 1958 } 1959 1960 int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, 1961 uint32_t *table_version) 1962 { 1963 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1964 1965 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1966 return -EOPNOTSUPP; 1967 1968 if (smu_ras_drv->smu_eeprom_funcs->get_ras_table_version) 1969 return smu_ras_drv->smu_eeprom_funcs->get_ras_table_version(adev, 1970 table_version); 1971 return -EOPNOTSUPP; 1972 } 1973 1974 int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, 1975 uint32_t *count, uint32_t timeout) 1976 { 1977 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1978 1979 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1980 return -EOPNOTSUPP; 1981 1982 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_count) 1983 return smu_ras_drv->smu_eeprom_funcs->get_badpage_count(adev, 1984 count, timeout); 1985 return -EOPNOTSUPP; 1986 } 1987 1988 int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, 1989 uint16_t index, uint64_t *mca_addr) 1990 { 1991 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1992 1993 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1994 return -EOPNOTSUPP; 1995 1996 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr) 1997 return smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr(adev, 1998 index, mca_addr); 1999 return -EOPNOTSUPP; 2000 } 2001 2002 int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, 2003 uint64_t timestamp) 2004 { 2005 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 2006 2007 if (!amdgpu_ras_smu_eeprom_supported(adev)) 2008 return -EOPNOTSUPP; 2009 2010 if (smu_ras_drv->smu_eeprom_funcs->set_timestamp) 2011 return smu_ras_drv->smu_eeprom_funcs->set_timestamp(adev, 2012 timestamp); 2013 return -EOPNOTSUPP; 2014 } 2015 2016 int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, 2017 uint16_t index, uint64_t *timestamp) 2018 { 2019 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 2020 2021 if (!amdgpu_ras_smu_eeprom_supported(adev)) 2022 return -EOPNOTSUPP; 2023 2024 if (smu_ras_drv->smu_eeprom_funcs->get_timestamp) 2025 return smu_ras_drv->smu_eeprom_funcs->get_timestamp(adev, 2026 index, timestamp); 2027 return -EOPNOTSUPP; 2028 } 2029 2030 int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, 2031 uint16_t index, uint64_t *ipid) 2032 { 2033 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 2034 2035 if (!amdgpu_ras_smu_eeprom_supported(adev)) 2036 return -EOPNOTSUPP; 2037 2038 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid) 2039 return smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid(adev, 2040 index, ipid); 2041 return -EOPNOTSUPP; 2042 } 2043 2044 int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, 2045 uint32_t *result) 2046 { 2047 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 2048 2049 if (!amdgpu_ras_smu_eeprom_supported(adev)) 2050 return -EOPNOTSUPP; 2051 2052 if (smu_ras_drv->smu_eeprom_funcs->erase_ras_table) 2053 return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev, 2054 result); 2055 return -EOPNOTSUPP; 2056 } 2057 2058 void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) 2059 { 2060 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 2061 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 2062 2063 if (!__is_ras_eeprom_supported(adev) || !control || amdgpu_bad_page_threshold == 0) 2064 return; 2065 2066 if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 2067 if (amdgpu_dpm_send_rma_reason(adev)) 2068 dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); 2069 else 2070 dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); 2071 2072 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { 2073 if (amdgpu_cper_generate_bp_threshold_record(adev)) 2074 dev_warn(adev->dev, "Unable to send in-band RMA CPER"); 2075 else 2076 dev_dbg(adev->dev, "Sent in-band RMA CPER"); 2077 } 2078 } 2079 } 2080