1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 #include "amdgpu_ras_mgr.h" 36 37 /* These are memory addresses as would be seen by one or more EEPROM 38 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 39 * set of EEPROM devices. They form a continuous memory space. 40 * 41 * The I2C device address includes the device type identifier, 1010b, 42 * which is a reserved value and indicates that this is an I2C EEPROM 43 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 44 * address, namely bits 18, 17, and 16. This makes up the 7 bit 45 * address sent on the I2C bus with bit 0 being the direction bit, 46 * which is not represented here, and sent by the hardware directly. 47 * 48 * For instance, 49 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 50 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 51 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 52 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 53 * address memory in a device or a device on the I2C bus, depending on 54 * the status of pins 1-3. See top of amdgpu_eeprom.c. 55 * 56 * The RAS table lives either at address 0 or address 40000h of EEPROM. 57 */ 58 #define EEPROM_I2C_MADDR_0 0x0 59 #define EEPROM_I2C_MADDR_4 0x40000 60 61 /* 62 * The 2 macros below represent the actual size in bytes that 63 * those entities occupy in the EEPROM memory. 64 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 65 * uses uint64 to store 6b fields such as retired_page. 66 */ 67 #define RAS_TABLE_HEADER_SIZE 20 68 #define RAS_TABLE_RECORD_SIZE 24 69 70 /* Table hdr is 'AMDR' */ 71 #define RAS_TABLE_HDR_VAL 0x414d4452 72 73 /* Bad GPU tag ‘BADG’ */ 74 #define RAS_TABLE_HDR_BAD 0x42414447 75 76 /* 77 * EEPROM Table structure v1 78 * --------------------------------- 79 * | | 80 * | EEPROM TABLE HEADER | 81 * | ( size 20 Bytes ) | 82 * | | 83 * --------------------------------- 84 * | | 85 * | BAD PAGE RECORD AREA | 86 * | | 87 * --------------------------------- 88 */ 89 90 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 91 #define RAS_TBL_SIZE_BYTES (256 * 1024) 92 #define RAS_TABLE_START 0 93 #define RAS_HDR_START RAS_TABLE_START 94 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 95 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 96 / RAS_TABLE_RECORD_SIZE) 97 98 /* 99 * EEPROM Table structrue v2.1 100 * --------------------------------- 101 * | | 102 * | EEPROM TABLE HEADER | 103 * | ( size 20 Bytes ) | 104 * | | 105 * --------------------------------- 106 * | | 107 * | EEPROM TABLE RAS INFO | 108 * | (available info size 4 Bytes) | 109 * | ( reserved size 252 Bytes ) | 110 * | | 111 * --------------------------------- 112 * | | 113 * | BAD PAGE RECORD AREA | 114 * | | 115 * --------------------------------- 116 */ 117 118 /* EEPROM Table V2_1 */ 119 #define RAS_TABLE_V2_1_INFO_SIZE 256 120 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 121 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 122 RAS_TABLE_V2_1_INFO_SIZE) 123 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 124 RAS_TABLE_V2_1_INFO_SIZE) \ 125 / RAS_TABLE_RECORD_SIZE) 126 127 #define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */ 128 129 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 130 * offset off of RAS_TABLE_START. That is, this is something you can 131 * add to control->i2c_address, and then tell I2C layer to read 132 * from/write to there. _N is the so called absolute index, 133 * because it starts right after the table header. 134 */ 135 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 136 (_N) * RAS_TABLE_RECORD_SIZE) 137 138 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 139 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 140 141 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 142 * of "fri", return the absolute record index off of the end of 143 * the table header. 144 */ 145 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 146 (_C)->ras_max_record_count) 147 148 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 150 151 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 152 RAS_TABLE_HEADER_SIZE - \ 153 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 154 155 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 156 157 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 158 { 159 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 160 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 161 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 162 case IP_VERSION(13, 0, 0): 163 case IP_VERSION(13, 0, 2): /* Aldebaran */ 164 case IP_VERSION(13, 0, 10): 165 return true; 166 case IP_VERSION(13, 0, 6): 167 case IP_VERSION(13, 0, 12): 168 case IP_VERSION(13, 0, 14): 169 return (adev->gmc.is_app_apu) ? false : true; 170 default: 171 return false; 172 } 173 } 174 175 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 176 struct amdgpu_ras_eeprom_control *control) 177 { 178 struct atom_context *atom_ctx = adev->mode_info.atom_context; 179 u8 i2c_addr; 180 181 if (!control) 182 return false; 183 184 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 185 /* The address given by VBIOS is an 8-bit, wire-format 186 * address, i.e. the most significant byte. 187 * 188 * Normalize it to a 19-bit EEPROM address. Remove the 189 * device type identifier and make it a 7-bit address; 190 * then make it a 19-bit EEPROM address. See top of 191 * amdgpu_eeprom.c. 192 */ 193 i2c_addr = (i2c_addr & 0x0F) >> 1; 194 control->i2c_address = ((u32) i2c_addr) << 16; 195 196 return true; 197 } 198 199 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 200 case IP_VERSION(11, 0, 2): 201 /* VEGA20 and ARCTURUS */ 202 if (adev->asic_type == CHIP_VEGA20) 203 control->i2c_address = EEPROM_I2C_MADDR_0; 204 else if (strnstr(atom_ctx->vbios_pn, 205 "D342", 206 sizeof(atom_ctx->vbios_pn))) 207 control->i2c_address = EEPROM_I2C_MADDR_0; 208 else 209 control->i2c_address = EEPROM_I2C_MADDR_4; 210 return true; 211 case IP_VERSION(11, 0, 7): 212 control->i2c_address = EEPROM_I2C_MADDR_0; 213 return true; 214 case IP_VERSION(13, 0, 2): 215 if (strnstr(atom_ctx->vbios_pn, "D673", 216 sizeof(atom_ctx->vbios_pn))) 217 control->i2c_address = EEPROM_I2C_MADDR_4; 218 else 219 control->i2c_address = EEPROM_I2C_MADDR_0; 220 return true; 221 case IP_VERSION(13, 0, 0): 222 if (strnstr(atom_ctx->vbios_pn, "D707", 223 sizeof(atom_ctx->vbios_pn))) 224 control->i2c_address = EEPROM_I2C_MADDR_0; 225 else 226 control->i2c_address = EEPROM_I2C_MADDR_4; 227 return true; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 10): 230 case IP_VERSION(13, 0, 12): 231 case IP_VERSION(13, 0, 14): 232 control->i2c_address = EEPROM_I2C_MADDR_4; 233 return true; 234 default: 235 return false; 236 } 237 } 238 239 static void 240 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 241 unsigned char *buf) 242 { 243 u32 *pp = (uint32_t *)buf; 244 245 pp[0] = cpu_to_le32(hdr->header); 246 pp[1] = cpu_to_le32(hdr->version); 247 pp[2] = cpu_to_le32(hdr->first_rec_offset); 248 pp[3] = cpu_to_le32(hdr->tbl_size); 249 pp[4] = cpu_to_le32(hdr->checksum); 250 } 251 252 static void 253 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 254 unsigned char *buf) 255 { 256 u32 *pp = (uint32_t *)buf; 257 258 hdr->header = le32_to_cpu(pp[0]); 259 hdr->version = le32_to_cpu(pp[1]); 260 hdr->first_rec_offset = le32_to_cpu(pp[2]); 261 hdr->tbl_size = le32_to_cpu(pp[3]); 262 hdr->checksum = le32_to_cpu(pp[4]); 263 } 264 265 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 266 { 267 u8 buf[RAS_TABLE_HEADER_SIZE]; 268 struct amdgpu_device *adev = to_amdgpu_device(control); 269 int res; 270 271 memset(buf, 0, sizeof(buf)); 272 __encode_table_header_to_buf(&control->tbl_hdr, buf); 273 274 /* i2c may be unstable in gpu reset */ 275 down_read(&adev->reset_domain->sem); 276 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 277 control->i2c_address + 278 control->ras_header_offset, 279 buf, RAS_TABLE_HEADER_SIZE); 280 up_read(&adev->reset_domain->sem); 281 282 if (res < 0) { 283 dev_err(adev->dev, "Failed to write EEPROM table header:%d", 284 res); 285 } else if (res < RAS_TABLE_HEADER_SIZE) { 286 dev_err(adev->dev, "Short write:%d out of %d\n", res, 287 RAS_TABLE_HEADER_SIZE); 288 res = -EIO; 289 } else { 290 res = 0; 291 } 292 293 return res; 294 } 295 296 static void 297 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 298 unsigned char *buf) 299 { 300 u32 *pp = (uint32_t *)buf; 301 u32 tmp; 302 303 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 304 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 305 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 306 pp[0] = cpu_to_le32(tmp); 307 } 308 309 static void 310 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 311 unsigned char *buf) 312 { 313 u32 *pp = (uint32_t *)buf; 314 u32 tmp; 315 316 tmp = le32_to_cpu(pp[0]); 317 rai->rma_status = tmp & 0xFF; 318 rai->health_percent = (tmp >> 8) & 0xFF; 319 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 320 } 321 322 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 323 { 324 struct amdgpu_device *adev = to_amdgpu_device(control); 325 u8 *buf; 326 int res; 327 328 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 329 if (!buf) { 330 dev_err(adev->dev, 331 "Failed to alloc buf to write table ras info\n"); 332 return -ENOMEM; 333 } 334 335 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 336 337 /* i2c may be unstable in gpu reset */ 338 down_read(&adev->reset_domain->sem); 339 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 340 control->i2c_address + 341 control->ras_info_offset, 342 buf, RAS_TABLE_V2_1_INFO_SIZE); 343 up_read(&adev->reset_domain->sem); 344 345 if (res < 0) { 346 dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", 347 res); 348 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 349 dev_err(adev->dev, "Short write:%d out of %d\n", res, 350 RAS_TABLE_V2_1_INFO_SIZE); 351 res = -EIO; 352 } else { 353 res = 0; 354 } 355 356 kfree(buf); 357 358 return res; 359 } 360 361 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 362 { 363 int ii; 364 u8 *pp, csum; 365 size_t sz; 366 367 /* Header checksum, skip checksum field in the calculation */ 368 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 369 pp = (u8 *) &control->tbl_hdr; 370 csum = 0; 371 for (ii = 0; ii < sz; ii++, pp++) 372 csum += *pp; 373 374 return csum; 375 } 376 377 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 378 { 379 int ii; 380 u8 *pp, csum; 381 size_t sz; 382 383 sz = sizeof(control->tbl_rai); 384 pp = (u8 *) &control->tbl_rai; 385 csum = 0; 386 for (ii = 0; ii < sz; ii++, pp++) 387 csum += *pp; 388 389 return csum; 390 } 391 392 static int amdgpu_ras_eeprom_correct_header_tag( 393 struct amdgpu_ras_eeprom_control *control, 394 uint32_t header) 395 { 396 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 397 u8 *hh; 398 int res; 399 u8 csum; 400 401 csum = -hdr->checksum; 402 403 hh = (void *) &hdr->header; 404 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 405 hh = (void *) &header; 406 csum += hh[0] + hh[1] + hh[2] + hh[3]; 407 csum = -csum; 408 mutex_lock(&control->ras_tbl_mutex); 409 hdr->header = header; 410 hdr->checksum = csum; 411 res = __write_table_header(control); 412 mutex_unlock(&control->ras_tbl_mutex); 413 414 return res; 415 } 416 417 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 418 { 419 struct amdgpu_device *adev = to_amdgpu_device(control); 420 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 421 422 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 423 case IP_VERSION(8, 10, 0): 424 hdr->version = RAS_TABLE_VER_V2_1; 425 return; 426 case IP_VERSION(12, 0, 0): 427 case IP_VERSION(12, 5, 0): 428 hdr->version = RAS_TABLE_VER_V3; 429 return; 430 default: 431 hdr->version = RAS_TABLE_VER_V1; 432 return; 433 } 434 } 435 436 /** 437 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 438 * @control: pointer to control structure 439 * 440 * Reset the contents of the header of the RAS EEPROM table. 441 * Return 0 on success, -errno on error. 442 */ 443 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 444 { 445 struct amdgpu_device *adev = to_amdgpu_device(control); 446 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 447 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 448 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 449 u32 erase_res = 0; 450 u8 csum; 451 int res; 452 453 mutex_lock(&control->ras_tbl_mutex); 454 455 if (!amdgpu_ras_smu_eeprom_supported(adev)) { 456 hdr->header = RAS_TABLE_HDR_VAL; 457 amdgpu_ras_set_eeprom_table_version(control); 458 459 if (hdr->version >= RAS_TABLE_VER_V2_1) { 460 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 461 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 462 RAS_TABLE_V2_1_INFO_SIZE; 463 rai->rma_status = GPU_HEALTH_USABLE; 464 465 control->ras_record_offset = RAS_RECORD_START_V2_1; 466 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 467 /** 468 * GPU health represented as a percentage. 469 * 0 means worst health, 100 means fully health. 470 */ 471 rai->health_percent = 100; 472 /* ecc_page_threshold = 0 means disable bad page retirement */ 473 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 474 } else { 475 hdr->first_rec_offset = RAS_RECORD_START; 476 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 477 478 control->ras_record_offset = RAS_RECORD_START; 479 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 480 } 481 482 csum = __calc_hdr_byte_sum(control); 483 if (hdr->version >= RAS_TABLE_VER_V2_1) 484 csum += __calc_ras_info_byte_sum(control); 485 csum = -csum; 486 hdr->checksum = csum; 487 res = __write_table_header(control); 488 if (!res && hdr->version > RAS_TABLE_VER_V1) 489 res = __write_table_ras_info(control); 490 } else { 491 res = amdgpu_ras_smu_erase_ras_table(adev, &erase_res); 492 if (res || erase_res) { 493 dev_warn(adev->dev, "RAS EEPROM reset failed, res:%d result:%d", 494 res, erase_res); 495 if (!res) 496 res = -EIO; 497 } 498 } 499 500 control->ras_num_recs = 0; 501 control->ras_num_bad_pages = 0; 502 control->ras_num_mca_recs = 0; 503 control->ras_num_pa_recs = 0; 504 control->ras_fri = 0; 505 506 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); 507 508 control->bad_channel_bitmap = 0; 509 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 510 con->update_channel_flag = false; 511 /* there is no record on eeprom now, clear the counter */ 512 if (con->eh_data) 513 con->eh_data->count_saved = 0; 514 515 amdgpu_ras_debugfs_set_ret_size(control); 516 517 mutex_unlock(&control->ras_tbl_mutex); 518 519 return res; 520 } 521 522 static void 523 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 524 struct eeprom_table_record *record, 525 unsigned char *buf) 526 { 527 __le64 tmp = 0; 528 int i = 0; 529 530 /* Next are all record fields according to EEPROM page spec in LE foramt */ 531 buf[i++] = record->err_type; 532 533 buf[i++] = record->bank; 534 535 tmp = cpu_to_le64(record->ts); 536 memcpy(buf + i, &tmp, 8); 537 i += 8; 538 539 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 540 memcpy(buf + i, &tmp, 6); 541 i += 6; 542 543 buf[i++] = record->mem_channel; 544 buf[i++] = record->mcumc_id; 545 546 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 547 memcpy(buf + i, &tmp, 6); 548 } 549 550 static void 551 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 552 struct eeprom_table_record *record, 553 unsigned char *buf) 554 { 555 __le64 tmp = 0; 556 int i = 0; 557 558 /* Next are all record fields according to EEPROM page spec in LE foramt */ 559 record->err_type = buf[i++]; 560 561 record->bank = buf[i++]; 562 563 memcpy(&tmp, buf + i, 8); 564 record->ts = le64_to_cpu(tmp); 565 i += 8; 566 567 memcpy(&tmp, buf + i, 6); 568 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 569 i += 6; 570 571 record->mem_channel = buf[i++]; 572 record->mcumc_id = buf[i++]; 573 574 memcpy(&tmp, buf + i, 6); 575 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 576 } 577 578 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 579 { 580 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 581 582 if (amdgpu_uniras_enabled(adev)) 583 return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev); 584 585 if (!__is_ras_eeprom_supported(adev) || 586 !amdgpu_bad_page_threshold) 587 return false; 588 589 /* skip check eeprom table for VEGA20 Gaming */ 590 if (!con) 591 return false; 592 else 593 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 594 return false; 595 596 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 597 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold) 598 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 599 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold); 600 if ((amdgpu_bad_page_threshold == -1) || 601 (amdgpu_bad_page_threshold == -2)) { 602 dev_warn(adev->dev, 603 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 604 return false; 605 } else { 606 dev_warn(adev->dev, 607 "Please consider adjusting the customized threshold.\n"); 608 return true; 609 } 610 } 611 612 return false; 613 } 614 615 /** 616 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 617 * @control: pointer to control structure 618 * @buf: pointer to buffer containing data to write 619 * @fri: start writing at this index 620 * @num: number of records to write 621 * 622 * The caller must hold the table mutex in @control. 623 * Return 0 on success, -errno otherwise. 624 */ 625 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 626 u8 *buf, const u32 fri, const u32 num) 627 { 628 struct amdgpu_device *adev = to_amdgpu_device(control); 629 u32 buf_size; 630 int res; 631 632 /* i2c may be unstable in gpu reset */ 633 down_read(&adev->reset_domain->sem); 634 buf_size = num * RAS_TABLE_RECORD_SIZE; 635 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 636 control->i2c_address + 637 RAS_INDEX_TO_OFFSET(control, fri), 638 buf, buf_size); 639 up_read(&adev->reset_domain->sem); 640 if (res < 0) { 641 dev_err(adev->dev, "Writing %d EEPROM table records error:%d", 642 num, res); 643 } else if (res < buf_size) { 644 /* Short write, return error. 645 */ 646 dev_err(adev->dev, "Wrote %d records out of %d", 647 res / RAS_TABLE_RECORD_SIZE, num); 648 res = -EIO; 649 } else { 650 res = 0; 651 } 652 653 return res; 654 } 655 656 static int 657 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 658 struct eeprom_table_record *record, 659 const u32 num) 660 { 661 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 662 struct amdgpu_device *adev = to_amdgpu_device(control); 663 u32 a, b, i; 664 u8 *buf, *pp; 665 int res; 666 667 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 668 if (!buf) 669 return -ENOMEM; 670 671 /* Encode all of them in one go. 672 */ 673 pp = buf; 674 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 675 __encode_table_record_to_buf(control, &record[i], pp); 676 677 /* update bad channel bitmap */ 678 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 679 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 680 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 681 con->update_channel_flag = true; 682 } 683 } 684 685 /* a, first record index to write into. 686 * b, last record index to write into. 687 * a = first index to read (fri) + number of records in the table, 688 * b = a + @num - 1. 689 * Let N = control->ras_max_num_record_count, then we have, 690 * case 0: 0 <= a <= b < N, 691 * just append @num records starting at a; 692 * case 1: 0 <= a < N <= b, 693 * append (N - a) records starting at a, and 694 * append the remainder, b % N + 1, starting at 0. 695 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 696 * case 2a: 0 <= a <= b < N 697 * append num records starting at a; and fix fri if b overwrote it, 698 * and since a <= b, if b overwrote it then a must've also, 699 * and if b didn't overwrite it, then a didn't also. 700 * case 2b: 0 <= b < a < N 701 * write num records starting at a, which wraps around 0=N 702 * and overwrite fri unconditionally. Now from case 2a, 703 * this means that b eclipsed fri to overwrite it and wrap 704 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 705 * set fri = b + 1 (mod N). 706 * Now, since fri is updated in every case, except the trivial case 0, 707 * the number of records present in the table after writing, is, 708 * num_recs - 1 = b - fri (mod N), and we take the positive value, 709 * by adding an arbitrary multiple of N before taking the modulo N 710 * as shown below. 711 */ 712 a = control->ras_fri + control->ras_num_recs; 713 b = a + num - 1; 714 if (b < control->ras_max_record_count) { 715 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 716 } else if (a < control->ras_max_record_count) { 717 u32 g0, g1; 718 719 g0 = control->ras_max_record_count - a; 720 g1 = b % control->ras_max_record_count + 1; 721 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 722 if (res) 723 goto Out; 724 res = __amdgpu_ras_eeprom_write(control, 725 buf + g0 * RAS_TABLE_RECORD_SIZE, 726 0, g1); 727 if (res) 728 goto Out; 729 if (g1 > control->ras_fri) 730 control->ras_fri = g1 % control->ras_max_record_count; 731 } else { 732 a %= control->ras_max_record_count; 733 b %= control->ras_max_record_count; 734 735 if (a <= b) { 736 /* Note that, b - a + 1 = num. */ 737 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 738 if (res) 739 goto Out; 740 if (b >= control->ras_fri) 741 control->ras_fri = (b + 1) % control->ras_max_record_count; 742 } else { 743 u32 g0, g1; 744 745 /* b < a, which means, we write from 746 * a to the end of the table, and from 747 * the start of the table to b. 748 */ 749 g0 = control->ras_max_record_count - a; 750 g1 = b + 1; 751 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 752 if (res) 753 goto Out; 754 res = __amdgpu_ras_eeprom_write(control, 755 buf + g0 * RAS_TABLE_RECORD_SIZE, 756 0, g1); 757 if (res) 758 goto Out; 759 control->ras_fri = g1 % control->ras_max_record_count; 760 } 761 } 762 control->ras_num_recs = 1 + (control->ras_max_record_count + b 763 - control->ras_fri) 764 % control->ras_max_record_count; 765 766 /*old asics only save pa to eeprom like before*/ 767 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) 768 control->ras_num_pa_recs += num; 769 else 770 control->ras_num_mca_recs += num; 771 772 control->ras_num_bad_pages = con->bad_page_num; 773 Out: 774 kfree(buf); 775 return res; 776 } 777 778 static int 779 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 780 { 781 struct amdgpu_device *adev = to_amdgpu_device(control); 782 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 783 u8 *buf, *pp, csum; 784 u32 buf_size; 785 int res; 786 787 /* Modify the header if it exceeds. 788 */ 789 if (amdgpu_bad_page_threshold != 0 && 790 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 791 dev_warn(adev->dev, 792 "Saved bad pages %d reaches threshold value %d\n", 793 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 794 795 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev) && 796 amdgpu_cper_generate_bp_threshold_record(adev)) 797 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 798 799 if ((amdgpu_bad_page_threshold != -1) && 800 (amdgpu_bad_page_threshold != -2)) { 801 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 802 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 803 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 804 control->tbl_rai.health_percent = 0; 805 } 806 ras->is_rma = true; 807 } 808 809 /* ignore the -ENOTSUPP return value */ 810 amdgpu_dpm_send_rma_reason(adev); 811 } 812 813 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 814 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 815 RAS_TABLE_V2_1_INFO_SIZE + 816 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 817 else 818 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 819 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 820 control->tbl_hdr.checksum = 0; 821 822 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 823 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 824 if (!buf) { 825 dev_err(adev->dev, 826 "allocating memory for table of size %d bytes failed\n", 827 control->tbl_hdr.tbl_size); 828 res = -ENOMEM; 829 goto Out; 830 } 831 832 down_read(&adev->reset_domain->sem); 833 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 834 control->i2c_address + 835 control->ras_record_offset, 836 buf, buf_size); 837 up_read(&adev->reset_domain->sem); 838 if (res < 0) { 839 dev_err(adev->dev, "EEPROM failed reading records:%d\n", res); 840 goto Out; 841 } else if (res < buf_size) { 842 dev_err(adev->dev, "EEPROM read %d out of %d bytes\n", res, 843 buf_size); 844 res = -EIO; 845 goto Out; 846 } 847 848 /** 849 * bad page records have been stored in eeprom, 850 * now calculate gpu health percent 851 */ 852 if (amdgpu_bad_page_threshold != 0 && 853 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 854 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) 855 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 856 control->ras_num_bad_pages) * 100) / 857 ras->bad_page_cnt_threshold; 858 859 /* Recalc the checksum. 860 */ 861 csum = 0; 862 for (pp = buf; pp < buf + buf_size; pp++) 863 csum += *pp; 864 865 csum += __calc_hdr_byte_sum(control); 866 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 867 csum += __calc_ras_info_byte_sum(control); 868 /* avoid sign extension when assigning to "checksum" */ 869 csum = -csum; 870 control->tbl_hdr.checksum = csum; 871 res = __write_table_header(control); 872 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 873 res = __write_table_ras_info(control); 874 Out: 875 kfree(buf); 876 return res; 877 } 878 879 int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) 880 { 881 struct amdgpu_device *adev = to_amdgpu_device(control); 882 int ret, retry = 20; 883 884 if (!amdgpu_ras_smu_eeprom_supported(adev)) 885 return 0; 886 887 control->ras_num_recs_old = control->ras_num_recs; 888 889 do { 890 /* 1000ms timeout is long enough, smu_get_badpage_count won't 891 * return -EBUSY before timeout. 892 */ 893 ret = amdgpu_ras_smu_get_badpage_count(adev, 894 &(control->ras_num_recs), RAS_SMU_MESSAGE_TIMEOUT_MS); 895 if (!ret && 896 (control->ras_num_recs_old == control->ras_num_recs)) { 897 /* record number update in PMFW needs some time, 898 * smu_get_badpage_count may return immediately without 899 * count update, sleep for a while and retry again. 900 */ 901 msleep(50); 902 retry--; 903 } else { 904 break; 905 } 906 } while (retry); 907 908 /* no update of record number is not a real failure, 909 * don't print warning here 910 */ 911 if (!ret && (control->ras_num_recs_old == control->ras_num_recs)) 912 ret = -EINVAL; 913 914 return ret; 915 } 916 917 static int amdgpu_ras_smu_eeprom_append(struct amdgpu_ras_eeprom_control *control) 918 { 919 struct amdgpu_device *adev = to_amdgpu_device(control); 920 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 921 922 if (!amdgpu_ras_smu_eeprom_supported(adev) || !con) 923 return 0; 924 925 control->ras_num_bad_pages = con->bad_page_num; 926 927 if (amdgpu_bad_page_threshold != 0 && 928 control->ras_num_bad_pages > con->bad_page_cnt_threshold) { 929 dev_warn(adev->dev, 930 "Saved bad pages %d reaches threshold value %d\n", 931 control->ras_num_bad_pages, con->bad_page_cnt_threshold); 932 933 if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev)) 934 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 935 936 if ((amdgpu_bad_page_threshold != -1) && 937 (amdgpu_bad_page_threshold != -2)) 938 con->is_rma = true; 939 } 940 941 return 0; 942 } 943 944 /** 945 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 946 * @control: pointer to control structure 947 * @record: array of records to append 948 * @num: number of records in @record array 949 * 950 * Append @num records to the table, calculate the checksum and write 951 * the table back to EEPROM. The maximum number of records that 952 * can be appended is between 1 and control->ras_max_record_count, 953 * regardless of how many records are already stored in the table. 954 * 955 * Return 0 on success or if EEPROM is not supported, -errno on error. 956 */ 957 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 958 struct eeprom_table_record *record, 959 const u32 num) 960 { 961 struct amdgpu_device *adev = to_amdgpu_device(control); 962 int res, i; 963 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 964 965 if (!__is_ras_eeprom_supported(adev)) 966 return 0; 967 968 if (amdgpu_ras_smu_eeprom_supported(adev)) 969 return amdgpu_ras_smu_eeprom_append(control); 970 971 if (num == 0) { 972 dev_err(adev->dev, "will not append 0 records\n"); 973 return -EINVAL; 974 } else if (num > control->ras_max_record_count) { 975 dev_err(adev->dev, 976 "cannot append %d records than the size of table %d\n", 977 num, control->ras_max_record_count); 978 return -EINVAL; 979 } 980 981 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 982 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 983 984 /* set the new channel index flag */ 985 for (i = 0; i < num; i++) 986 record[i].retired_page |= (nps << UMC_NPS_SHIFT); 987 988 mutex_lock(&control->ras_tbl_mutex); 989 990 res = amdgpu_ras_eeprom_append_table(control, record, num); 991 if (!res) 992 res = amdgpu_ras_eeprom_update_header(control); 993 if (!res) 994 amdgpu_ras_debugfs_set_ret_size(control); 995 996 mutex_unlock(&control->ras_tbl_mutex); 997 998 /* clear channel index flag, the flag is only saved on eeprom */ 999 for (i = 0; i < num; i++) 1000 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT); 1001 1002 return res; 1003 } 1004 1005 /** 1006 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 1007 * @control: pointer to control structure 1008 * @buf: pointer to buffer to read into 1009 * @fri: first record index, start reading at this index, absolute index 1010 * @num: number of records to read 1011 * 1012 * The caller must hold the table mutex in @control. 1013 * Return 0 on success, -errno otherwise. 1014 */ 1015 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 1016 u8 *buf, const u32 fri, const u32 num) 1017 { 1018 struct amdgpu_device *adev = to_amdgpu_device(control); 1019 u32 buf_size; 1020 int res; 1021 1022 /* i2c may be unstable in gpu reset */ 1023 down_read(&adev->reset_domain->sem); 1024 buf_size = num * RAS_TABLE_RECORD_SIZE; 1025 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1026 control->i2c_address + 1027 RAS_INDEX_TO_OFFSET(control, fri), 1028 buf, buf_size); 1029 up_read(&adev->reset_domain->sem); 1030 if (res < 0) { 1031 dev_err(adev->dev, "Reading %d EEPROM table records error:%d", 1032 num, res); 1033 } else if (res < buf_size) { 1034 /* Short read, return error. 1035 */ 1036 dev_err(adev->dev, "Read %d records out of %d", 1037 res / RAS_TABLE_RECORD_SIZE, num); 1038 res = -EIO; 1039 } else { 1040 res = 0; 1041 } 1042 1043 return res; 1044 } 1045 1046 int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, 1047 struct eeprom_table_record *record, u32 rec_idx, 1048 const u32 num) 1049 { 1050 struct amdgpu_device *adev = to_amdgpu_device(control); 1051 uint64_t ts, end_idx; 1052 int i, ret; 1053 u64 mca, ipid; 1054 u32 cu, mem_channel, mcumc_id; 1055 1056 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1057 return 0; 1058 1059 if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) 1060 return -EOPNOTSUPP; 1061 1062 end_idx = rec_idx + num; 1063 for (i = rec_idx; i < end_idx; i++) { 1064 ret = amdgpu_ras_smu_get_badpage_mca_addr(adev, i, &mca); 1065 if (ret) 1066 return ret; 1067 1068 ret = amdgpu_ras_smu_get_badpage_ipid(adev, i, &ipid); 1069 if (ret) 1070 return ret; 1071 1072 ret = amdgpu_ras_smu_get_timestamp(adev, i, &ts); 1073 if (ret) 1074 return ret; 1075 1076 record[i - rec_idx].address = mca; 1077 /* retired_page (pa) is unused now */ 1078 record[i - rec_idx].retired_page = 0x1ULL; 1079 record[i - rec_idx].ts = ts; 1080 record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 1081 1082 adev->umc.ras->mca_ipid_parse(adev, ipid, 1083 &cu, &mem_channel, &mcumc_id, NULL); 1084 record[i - rec_idx].cu = (u8)cu; 1085 record[i - rec_idx].mem_channel = (u8)mem_channel; 1086 record[i - rec_idx].mcumc_id = (u8)mcumc_id; 1087 } 1088 1089 return 0; 1090 } 1091 1092 /** 1093 * amdgpu_ras_eeprom_read -- read EEPROM 1094 * @control: pointer to control structure 1095 * @record: array of records to read into 1096 * @num: number of records in @record 1097 * 1098 * Reads num records from the RAS table in EEPROM and 1099 * writes the data into @record array. 1100 * 1101 * Returns 0 on success, -errno on error. 1102 */ 1103 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 1104 struct eeprom_table_record *record, 1105 const u32 num) 1106 { 1107 struct amdgpu_device *adev = to_amdgpu_device(control); 1108 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1109 int i, res; 1110 u8 *buf, *pp; 1111 u32 g0, g1; 1112 1113 if (amdgpu_ras_smu_eeprom_supported(adev)) 1114 return amdgpu_ras_eeprom_read_idx(control, record, 0, num); 1115 1116 if (!__is_ras_eeprom_supported(adev)) 1117 return 0; 1118 1119 if (num == 0) { 1120 dev_err(adev->dev, "will not read 0 records\n"); 1121 return -EINVAL; 1122 } else if (num > control->ras_num_recs) { 1123 dev_err(adev->dev, "too many records to read:%d available:%d\n", 1124 num, control->ras_num_recs); 1125 return -EINVAL; 1126 } 1127 1128 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 1129 if (!buf) 1130 return -ENOMEM; 1131 1132 /* Determine how many records to read, from the first record 1133 * index, fri, to the end of the table, and from the beginning 1134 * of the table, such that the total number of records is 1135 * @num, and we handle wrap around when fri > 0 and 1136 * fri + num > RAS_MAX_RECORD_COUNT. 1137 * 1138 * First we compute the index of the last element 1139 * which would be fetched from each region, 1140 * g0 is in [fri, fri + num - 1], and 1141 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 1142 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 1143 * the last element to fetch, we set g0 to _the number_ 1144 * of elements to fetch, @num, since we know that the last 1145 * indexed to be fetched does not exceed the table. 1146 * 1147 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 1148 * we set g0 to the number of elements to read 1149 * until the end of the table, and g1 to the number of 1150 * elements to read from the beginning of the table. 1151 */ 1152 g0 = control->ras_fri + num - 1; 1153 g1 = g0 % control->ras_max_record_count; 1154 if (g0 < control->ras_max_record_count) { 1155 g0 = num; 1156 g1 = 0; 1157 } else { 1158 g0 = control->ras_max_record_count - control->ras_fri; 1159 g1 += 1; 1160 } 1161 1162 mutex_lock(&control->ras_tbl_mutex); 1163 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 1164 if (res) 1165 goto Out; 1166 if (g1) { 1167 res = __amdgpu_ras_eeprom_read(control, 1168 buf + g0 * RAS_TABLE_RECORD_SIZE, 1169 0, g1); 1170 if (res) 1171 goto Out; 1172 } 1173 1174 res = 0; 1175 1176 /* Read up everything? Then transform. 1177 */ 1178 pp = buf; 1179 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 1180 __decode_table_record_from_buf(control, &record[i], pp); 1181 1182 /* update bad channel bitmap */ 1183 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1184 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1185 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1186 con->update_channel_flag = true; 1187 } 1188 } 1189 Out: 1190 kfree(buf); 1191 mutex_unlock(&control->ras_tbl_mutex); 1192 1193 return res; 1194 } 1195 1196 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1197 { 1198 /* get available eeprom table version first before eeprom table init */ 1199 amdgpu_ras_set_eeprom_table_version(control); 1200 1201 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1202 return RAS_MAX_RECORD_COUNT_V2_1; 1203 else 1204 return RAS_MAX_RECORD_COUNT; 1205 } 1206 1207 static ssize_t 1208 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1209 size_t size, loff_t *pos) 1210 { 1211 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1212 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1213 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1214 u8 data[50]; 1215 int res; 1216 1217 if (!size) 1218 return size; 1219 1220 if (!ras || !control) { 1221 res = snprintf(data, sizeof(data), "Not supported\n"); 1222 } else { 1223 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1224 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1225 } 1226 1227 if (*pos >= res) 1228 return 0; 1229 1230 res -= *pos; 1231 res = min_t(size_t, res, size); 1232 1233 if (copy_to_user(buf, &data[*pos], res)) 1234 return -EFAULT; 1235 1236 *pos += res; 1237 1238 return res; 1239 } 1240 1241 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1242 .owner = THIS_MODULE, 1243 .read = amdgpu_ras_debugfs_eeprom_size_read, 1244 .write = NULL, 1245 .llseek = default_llseek, 1246 }; 1247 1248 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1249 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1250 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1251 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1252 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1253 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1254 1255 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1256 "ignore", 1257 "re", 1258 "ue", 1259 }; 1260 1261 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1262 { 1263 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1264 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1265 } 1266 1267 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1268 { 1269 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1270 eeprom_control); 1271 struct dentry *de = ras->de_ras_eeprom_table; 1272 1273 if (de) 1274 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1275 } 1276 1277 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1278 size_t size, loff_t *pos) 1279 { 1280 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1281 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1282 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1283 const size_t orig_size = size; 1284 int res = -EFAULT; 1285 size_t data_len; 1286 1287 /* pmfw manages eeprom data by itself */ 1288 if (amdgpu_ras_smu_eeprom_supported(adev)) 1289 return 0; 1290 1291 mutex_lock(&control->ras_tbl_mutex); 1292 1293 /* We want *pos - data_len > 0, which means there's 1294 * bytes to be printed from data. 1295 */ 1296 data_len = strlen(tbl_hdr_str); 1297 if (*pos < data_len) { 1298 data_len -= *pos; 1299 data_len = min_t(size_t, data_len, size); 1300 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1301 goto Out; 1302 buf += data_len; 1303 size -= data_len; 1304 *pos += data_len; 1305 } 1306 1307 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1308 if (*pos < data_len && size > 0) { 1309 u8 data[tbl_hdr_fmt_size + 1]; 1310 loff_t lpos; 1311 1312 snprintf(data, sizeof(data), tbl_hdr_fmt, 1313 control->tbl_hdr.header, 1314 control->tbl_hdr.version, 1315 control->tbl_hdr.first_rec_offset, 1316 control->tbl_hdr.tbl_size, 1317 control->tbl_hdr.checksum); 1318 1319 data_len -= *pos; 1320 data_len = min_t(size_t, data_len, size); 1321 lpos = *pos - strlen(tbl_hdr_str); 1322 if (copy_to_user(buf, &data[lpos], data_len)) 1323 goto Out; 1324 buf += data_len; 1325 size -= data_len; 1326 *pos += data_len; 1327 } 1328 1329 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1330 if (*pos < data_len && size > 0) { 1331 loff_t lpos; 1332 1333 data_len -= *pos; 1334 data_len = min_t(size_t, data_len, size); 1335 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1336 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1337 goto Out; 1338 buf += data_len; 1339 size -= data_len; 1340 *pos += data_len; 1341 } 1342 1343 data_len = amdgpu_ras_debugfs_table_size(control); 1344 if (*pos < data_len && size > 0) { 1345 u8 dare[RAS_TABLE_RECORD_SIZE]; 1346 u8 data[rec_hdr_fmt_size + 1]; 1347 struct eeprom_table_record record; 1348 int s, r; 1349 1350 /* Find the starting record index 1351 */ 1352 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1353 strlen(rec_hdr_str); 1354 s = s / rec_hdr_fmt_size; 1355 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1356 strlen(rec_hdr_str); 1357 r = r % rec_hdr_fmt_size; 1358 1359 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1360 u32 ai = RAS_RI_TO_AI(control, s); 1361 /* Read a single record 1362 */ 1363 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1364 if (res) 1365 goto Out; 1366 __decode_table_record_from_buf(control, &record, dare); 1367 snprintf(data, sizeof(data), rec_hdr_fmt, 1368 s, 1369 RAS_INDEX_TO_OFFSET(control, ai), 1370 record_err_type_str[record.err_type], 1371 record.bank, 1372 record.ts, 1373 record.offset, 1374 record.mem_channel, 1375 record.mcumc_id, 1376 record.retired_page); 1377 1378 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1379 if (copy_to_user(buf, &data[r], data_len)) { 1380 res = -EFAULT; 1381 goto Out; 1382 } 1383 buf += data_len; 1384 size -= data_len; 1385 *pos += data_len; 1386 r = 0; 1387 } 1388 } 1389 res = 0; 1390 Out: 1391 mutex_unlock(&control->ras_tbl_mutex); 1392 return res < 0 ? res : orig_size - size; 1393 } 1394 1395 static ssize_t 1396 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1397 size_t size, loff_t *pos) 1398 { 1399 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1400 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1401 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1402 u8 data[81]; 1403 int res; 1404 1405 if (!size) 1406 return size; 1407 1408 if (!ras || !control) { 1409 res = snprintf(data, sizeof(data), "Not supported\n"); 1410 if (*pos >= res) 1411 return 0; 1412 1413 res -= *pos; 1414 res = min_t(size_t, res, size); 1415 1416 if (copy_to_user(buf, &data[*pos], res)) 1417 return -EFAULT; 1418 1419 *pos += res; 1420 1421 return res; 1422 } else { 1423 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1424 } 1425 } 1426 1427 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1428 .owner = THIS_MODULE, 1429 .read = amdgpu_ras_debugfs_eeprom_table_read, 1430 .write = NULL, 1431 .llseek = default_llseek, 1432 }; 1433 1434 /** 1435 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1436 * @control: pointer to control structure 1437 * 1438 * Check the checksum of the stored in EEPROM RAS table. 1439 * 1440 * Return 0 if the checksum is correct, 1441 * positive if it is not correct, and 1442 * -errno on I/O error. 1443 */ 1444 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1445 { 1446 struct amdgpu_device *adev = to_amdgpu_device(control); 1447 int buf_size, res; 1448 u8 csum, *buf, *pp; 1449 1450 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1451 buf_size = RAS_TABLE_HEADER_SIZE + 1452 RAS_TABLE_V2_1_INFO_SIZE + 1453 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1454 else 1455 buf_size = RAS_TABLE_HEADER_SIZE + 1456 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1457 1458 buf = kzalloc(buf_size, GFP_KERNEL); 1459 if (!buf) { 1460 dev_err(adev->dev, 1461 "Out of memory checking RAS table checksum.\n"); 1462 return -ENOMEM; 1463 } 1464 1465 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1466 control->i2c_address + 1467 control->ras_header_offset, 1468 buf, buf_size); 1469 if (res < buf_size) { 1470 dev_err(adev->dev, "Partial read for checksum, res:%d\n", res); 1471 /* On partial reads, return -EIO. 1472 */ 1473 if (res >= 0) 1474 res = -EIO; 1475 goto Out; 1476 } 1477 1478 csum = 0; 1479 for (pp = buf; pp < buf + buf_size; pp++) 1480 csum += *pp; 1481 Out: 1482 kfree(buf); 1483 return res < 0 ? res : csum; 1484 } 1485 1486 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1487 { 1488 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1489 struct amdgpu_device *adev = to_amdgpu_device(control); 1490 unsigned char *buf; 1491 int res; 1492 1493 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1494 if (!buf) { 1495 dev_err(adev->dev, 1496 "Failed to alloc buf to read EEPROM table ras info\n"); 1497 return -ENOMEM; 1498 } 1499 1500 /** 1501 * EEPROM table V2_1 supports ras info, 1502 * read EEPROM table ras info 1503 */ 1504 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1505 control->i2c_address + control->ras_info_offset, 1506 buf, RAS_TABLE_V2_1_INFO_SIZE); 1507 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1508 dev_err(adev->dev, 1509 "Failed to read EEPROM table ras info, res:%d", res); 1510 res = res >= 0 ? -EIO : res; 1511 goto Out; 1512 } 1513 1514 __decode_table_ras_info_from_buf(rai, buf); 1515 1516 Out: 1517 kfree(buf); 1518 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1519 } 1520 1521 static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1522 { 1523 struct amdgpu_device *adev = to_amdgpu_device(control); 1524 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1525 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1526 uint64_t local_time; 1527 int res; 1528 1529 ras->is_rma = false; 1530 1531 if (!__is_ras_eeprom_supported(adev)) 1532 return 0; 1533 mutex_init(&control->ras_tbl_mutex); 1534 1535 res = amdgpu_ras_smu_get_table_version(adev, &(hdr->version)); 1536 if (res) 1537 return res; 1538 1539 res = amdgpu_ras_smu_get_badpage_count(adev, 1540 &(control->ras_num_recs), 100); 1541 if (res) 1542 return res; 1543 1544 local_time = (uint64_t)ktime_get_real_seconds(); 1545 res = amdgpu_ras_smu_set_timestamp(adev, local_time); 1546 if (res) 1547 return res; 1548 1549 control->ras_max_record_count = 4000; 1550 1551 control->ras_num_mca_recs = 0; 1552 control->ras_num_pa_recs = 0; 1553 1554 return 0; 1555 } 1556 1557 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1558 { 1559 struct amdgpu_device *adev = to_amdgpu_device(control); 1560 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1561 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1562 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1563 int dev_var = adev->pdev->device & 0xF; 1564 uint32_t vram_type = adev->gmc.vram_type; 1565 int res; 1566 1567 if (amdgpu_ras_smu_eeprom_supported(adev)) 1568 return amdgpu_ras_smu_eeprom_init(control); 1569 1570 ras->is_rma = false; 1571 1572 if (!__is_ras_eeprom_supported(adev)) 1573 return 0; 1574 1575 /* Verify i2c adapter is initialized */ 1576 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1577 return -ENOENT; 1578 1579 if (!__get_eeprom_i2c_addr(adev, control)) 1580 return -EINVAL; 1581 1582 control->ras_header_offset = RAS_HDR_START; 1583 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1584 mutex_init(&control->ras_tbl_mutex); 1585 1586 /* Read the table header from EEPROM address */ 1587 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1588 control->i2c_address + control->ras_header_offset, 1589 buf, RAS_TABLE_HEADER_SIZE); 1590 if (res < RAS_TABLE_HEADER_SIZE) { 1591 dev_err(adev->dev, "Failed to read EEPROM table header, res:%d", 1592 res); 1593 return res >= 0 ? -EIO : res; 1594 } 1595 1596 __decode_table_header_from_buf(hdr, buf); 1597 1598 if (hdr->header != RAS_TABLE_HDR_VAL && 1599 hdr->header != RAS_TABLE_HDR_BAD) { 1600 dev_info(adev->dev, "Creating a new EEPROM table"); 1601 return amdgpu_ras_eeprom_reset_table(control); 1602 } 1603 1604 if (!(adev->flags & AMD_IS_APU) && (dev_var == 0x5) && 1605 (vram_type == AMDGPU_VRAM_TYPE_HBM3E) && 1606 (hdr->version < RAS_TABLE_VER_V3)) { 1607 return amdgpu_ras_eeprom_reset_table(control); 1608 } 1609 1610 switch (hdr->version) { 1611 case RAS_TABLE_VER_V2_1: 1612 case RAS_TABLE_VER_V3: 1613 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1614 control->ras_record_offset = RAS_RECORD_START_V2_1; 1615 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1616 break; 1617 case RAS_TABLE_VER_V1: 1618 control->ras_num_recs = RAS_NUM_RECS(hdr); 1619 control->ras_record_offset = RAS_RECORD_START; 1620 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1621 break; 1622 default: 1623 dev_err(adev->dev, 1624 "RAS header invalid, unsupported version: %u", 1625 hdr->version); 1626 return -EINVAL; 1627 } 1628 1629 if (control->ras_num_recs > control->ras_max_record_count) { 1630 dev_err(adev->dev, 1631 "RAS header invalid, records in header: %u max allowed :%u", 1632 control->ras_num_recs, control->ras_max_record_count); 1633 return -EINVAL; 1634 } 1635 1636 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1637 if (hdr->first_rec_offset < control->ras_record_offset || 1638 control->ras_fri >= control->ras_max_record_count) { 1639 dev_err(adev->dev, 1640 "RAS header invalid, ras_fri: %u, first_rec_offset:0x%x", 1641 control->ras_fri, hdr->first_rec_offset); 1642 return -EINVAL; 1643 } 1644 1645 control->ras_num_mca_recs = 0; 1646 control->ras_num_pa_recs = 0; 1647 return 0; 1648 } 1649 1650 static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1651 { 1652 struct amdgpu_device *adev = to_amdgpu_device(control); 1653 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1654 1655 if (!__is_ras_eeprom_supported(adev)) 1656 return 0; 1657 1658 control->ras_num_bad_pages = ras->bad_page_num; 1659 1660 if ((ras->bad_page_cnt_threshold < control->ras_num_bad_pages) && 1661 amdgpu_bad_page_threshold != 0) { 1662 dev_warn(adev->dev, 1663 "RAS records:%d exceed threshold:%d\n", 1664 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1665 if ((amdgpu_bad_page_threshold == -1) || 1666 (amdgpu_bad_page_threshold == -2)) { 1667 dev_warn(adev->dev, 1668 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1669 } else { 1670 ras->is_rma = true; 1671 dev_warn(adev->dev, 1672 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1673 } 1674 1675 return 0; 1676 } 1677 1678 dev_dbg(adev->dev, 1679 "Found existing EEPROM table with %d records", 1680 control->ras_num_bad_pages); 1681 1682 /* Warn if we are at 90% of the threshold or above 1683 */ 1684 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1685 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1686 control->ras_num_bad_pages, 1687 ras->bad_page_cnt_threshold); 1688 return 0; 1689 } 1690 1691 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1692 { 1693 struct amdgpu_device *adev = to_amdgpu_device(control); 1694 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1695 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1696 int res = 0; 1697 1698 if (amdgpu_ras_smu_eeprom_supported(adev)) 1699 return amdgpu_ras_smu_eeprom_check(control); 1700 1701 if (!__is_ras_eeprom_supported(adev)) 1702 return 0; 1703 1704 /* Verify i2c adapter is initialized */ 1705 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1706 return -ENOENT; 1707 1708 if (!__get_eeprom_i2c_addr(adev, control)) 1709 return -EINVAL; 1710 1711 control->ras_num_bad_pages = ras->bad_page_num; 1712 1713 if (hdr->header == RAS_TABLE_HDR_VAL) { 1714 dev_dbg(adev->dev, 1715 "Found existing EEPROM table with %d records", 1716 control->ras_num_bad_pages); 1717 1718 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1719 res = __read_table_ras_info(control); 1720 if (res) 1721 return res; 1722 } 1723 1724 res = __verify_ras_table_checksum(control); 1725 if (res) { 1726 dev_err(adev->dev, 1727 "RAS table incorrect checksum or error:%d\n", 1728 res); 1729 return -EINVAL; 1730 } 1731 1732 /* Warn if we are at 90% of the threshold or above 1733 */ 1734 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1735 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1736 control->ras_num_bad_pages, 1737 ras->bad_page_cnt_threshold); 1738 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1739 amdgpu_bad_page_threshold != 0) { 1740 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1741 res = __read_table_ras_info(control); 1742 if (res) 1743 return res; 1744 } 1745 1746 res = __verify_ras_table_checksum(control); 1747 if (res) { 1748 dev_err(adev->dev, 1749 "RAS Table incorrect checksum or error:%d\n", 1750 res); 1751 return -EINVAL; 1752 } 1753 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { 1754 /* This means that, the threshold was increased since 1755 * the last time the system was booted, and now, 1756 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1757 * so that at least one more record can be saved, 1758 * before the page count threshold is reached. 1759 */ 1760 dev_info(adev->dev, 1761 "records:%d threshold:%d, resetting " 1762 "RAS table header signature", 1763 control->ras_num_bad_pages, 1764 ras->bad_page_cnt_threshold); 1765 res = amdgpu_ras_eeprom_correct_header_tag(control, 1766 RAS_TABLE_HDR_VAL); 1767 } else { 1768 dev_warn(adev->dev, 1769 "RAS records:%d exceed threshold:%d\n", 1770 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1771 if ((amdgpu_bad_page_threshold == -1) || 1772 (amdgpu_bad_page_threshold == -2)) { 1773 res = 0; 1774 dev_warn(adev->dev, 1775 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1776 } else { 1777 ras->is_rma = true; 1778 dev_warn(adev->dev, 1779 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1780 } 1781 } 1782 } 1783 1784 return res < 0 ? res : 0; 1785 } 1786 1787 void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev) 1788 { 1789 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1790 struct amdgpu_ras_eeprom_control *control; 1791 int res; 1792 1793 if (!__is_ras_eeprom_supported(adev) || !ras || 1794 amdgpu_ras_smu_eeprom_supported(adev)) 1795 return; 1796 control = &ras->eeprom_control; 1797 if (!control->is_eeprom_valid) 1798 return; 1799 res = __verify_ras_table_checksum(control); 1800 if (res) { 1801 dev_warn(adev->dev, 1802 "RAS table incorrect checksum or error:%d, try to recover\n", 1803 res); 1804 if (!amdgpu_ras_eeprom_reset_table(control)) 1805 if (!amdgpu_ras_save_bad_pages(adev, NULL)) 1806 if (!__verify_ras_table_checksum(control)) { 1807 dev_info(adev->dev, "RAS table recovery succeed\n"); 1808 return; 1809 } 1810 dev_err(adev->dev, "RAS table recovery failed\n"); 1811 control->is_eeprom_valid = false; 1812 } 1813 return; 1814 } 1815 1816 static const struct ras_smu_drv *amdgpu_ras_get_smu_ras_drv(struct amdgpu_device *adev) 1817 { 1818 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1819 1820 if (!ras) 1821 return NULL; 1822 1823 return ras->ras_smu_drv; 1824 } 1825 1826 static uint64_t amdgpu_ras_smu_get_feature_flags(struct amdgpu_device *adev) 1827 { 1828 const struct ras_smu_drv *ras_smu_drv = amdgpu_ras_get_smu_ras_drv(adev); 1829 uint64_t flags = 0ULL; 1830 1831 if (!ras_smu_drv) 1832 goto out; 1833 1834 if (ras_smu_drv->ras_smu_feature_flags) 1835 ras_smu_drv->ras_smu_feature_flags(adev, &flags); 1836 1837 out: 1838 return flags; 1839 } 1840 1841 bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev) 1842 { 1843 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1844 uint64_t flags = 0ULL; 1845 1846 if (!__is_ras_eeprom_supported(adev) || !smu_ras_drv) 1847 return false; 1848 1849 if (!smu_ras_drv->smu_eeprom_funcs) 1850 return false; 1851 1852 flags = amdgpu_ras_smu_get_feature_flags(adev); 1853 1854 return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM); 1855 } 1856 1857 int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, 1858 uint32_t *table_version) 1859 { 1860 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1861 1862 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1863 return -EOPNOTSUPP; 1864 1865 if (smu_ras_drv->smu_eeprom_funcs->get_ras_table_version) 1866 return smu_ras_drv->smu_eeprom_funcs->get_ras_table_version(adev, 1867 table_version); 1868 return -EOPNOTSUPP; 1869 } 1870 1871 int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, 1872 uint32_t *count, uint32_t timeout) 1873 { 1874 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1875 1876 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1877 return -EOPNOTSUPP; 1878 1879 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_count) 1880 return smu_ras_drv->smu_eeprom_funcs->get_badpage_count(adev, 1881 count, timeout); 1882 return -EOPNOTSUPP; 1883 } 1884 1885 int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, 1886 uint16_t index, uint64_t *mca_addr) 1887 { 1888 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1889 1890 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1891 return -EOPNOTSUPP; 1892 1893 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr) 1894 return smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr(adev, 1895 index, mca_addr); 1896 return -EOPNOTSUPP; 1897 } 1898 1899 int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, 1900 uint64_t timestamp) 1901 { 1902 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1903 1904 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1905 return -EOPNOTSUPP; 1906 1907 if (smu_ras_drv->smu_eeprom_funcs->set_timestamp) 1908 return smu_ras_drv->smu_eeprom_funcs->set_timestamp(adev, 1909 timestamp); 1910 return -EOPNOTSUPP; 1911 } 1912 1913 int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, 1914 uint16_t index, uint64_t *timestamp) 1915 { 1916 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1917 1918 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1919 return -EOPNOTSUPP; 1920 1921 if (smu_ras_drv->smu_eeprom_funcs->get_timestamp) 1922 return smu_ras_drv->smu_eeprom_funcs->get_timestamp(adev, 1923 index, timestamp); 1924 return -EOPNOTSUPP; 1925 } 1926 1927 int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, 1928 uint16_t index, uint64_t *ipid) 1929 { 1930 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1931 1932 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1933 return -EOPNOTSUPP; 1934 1935 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid) 1936 return smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid(adev, 1937 index, ipid); 1938 return -EOPNOTSUPP; 1939 } 1940 1941 int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, 1942 uint32_t *result) 1943 { 1944 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1945 1946 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1947 return -EOPNOTSUPP; 1948 1949 if (smu_ras_drv->smu_eeprom_funcs->erase_ras_table) 1950 return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev, 1951 result); 1952 return -EOPNOTSUPP; 1953 } 1954 1955 void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) 1956 { 1957 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1958 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1959 1960 if (!control || amdgpu_bad_page_threshold == 0) 1961 return; 1962 1963 if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 1964 if (amdgpu_dpm_send_rma_reason(adev)) 1965 dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); 1966 else 1967 dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); 1968 1969 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { 1970 if (amdgpu_cper_generate_bp_threshold_record(adev)) 1971 dev_warn(adev->dev, "Unable to send in-band RMA CPER"); 1972 else 1973 dev_dbg(adev->dev, "Sent in-band RMA CPER"); 1974 } 1975 } 1976 } 1977