1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros below represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 10): 162 return true; 163 case IP_VERSION(13, 0, 6): 164 case IP_VERSION(13, 0, 12): 165 case IP_VERSION(13, 0, 14): 166 return (adev->gmc.is_app_apu) ? false : true; 167 default: 168 return false; 169 } 170 } 171 172 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 173 struct amdgpu_ras_eeprom_control *control) 174 { 175 struct atom_context *atom_ctx = adev->mode_info.atom_context; 176 u8 i2c_addr; 177 178 if (!control) 179 return false; 180 181 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 182 /* The address given by VBIOS is an 8-bit, wire-format 183 * address, i.e. the most significant byte. 184 * 185 * Normalize it to a 19-bit EEPROM address. Remove the 186 * device type identifier and make it a 7-bit address; 187 * then make it a 19-bit EEPROM address. See top of 188 * amdgpu_eeprom.c. 189 */ 190 i2c_addr = (i2c_addr & 0x0F) >> 1; 191 control->i2c_address = ((u32) i2c_addr) << 16; 192 193 return true; 194 } 195 196 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 197 case IP_VERSION(11, 0, 2): 198 /* VEGA20 and ARCTURUS */ 199 if (adev->asic_type == CHIP_VEGA20) 200 control->i2c_address = EEPROM_I2C_MADDR_0; 201 else if (strnstr(atom_ctx->vbios_pn, 202 "D342", 203 sizeof(atom_ctx->vbios_pn))) 204 control->i2c_address = EEPROM_I2C_MADDR_0; 205 else 206 control->i2c_address = EEPROM_I2C_MADDR_4; 207 return true; 208 case IP_VERSION(11, 0, 7): 209 control->i2c_address = EEPROM_I2C_MADDR_0; 210 return true; 211 case IP_VERSION(13, 0, 2): 212 if (strnstr(atom_ctx->vbios_pn, "D673", 213 sizeof(atom_ctx->vbios_pn))) 214 control->i2c_address = EEPROM_I2C_MADDR_4; 215 else 216 control->i2c_address = EEPROM_I2C_MADDR_0; 217 return true; 218 case IP_VERSION(13, 0, 0): 219 if (strnstr(atom_ctx->vbios_pn, "D707", 220 sizeof(atom_ctx->vbios_pn))) 221 control->i2c_address = EEPROM_I2C_MADDR_0; 222 else 223 control->i2c_address = EEPROM_I2C_MADDR_4; 224 return true; 225 case IP_VERSION(13, 0, 6): 226 case IP_VERSION(13, 0, 10): 227 case IP_VERSION(13, 0, 12): 228 case IP_VERSION(13, 0, 14): 229 control->i2c_address = EEPROM_I2C_MADDR_4; 230 return true; 231 default: 232 return false; 233 } 234 } 235 236 static void 237 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 238 unsigned char *buf) 239 { 240 u32 *pp = (uint32_t *)buf; 241 242 pp[0] = cpu_to_le32(hdr->header); 243 pp[1] = cpu_to_le32(hdr->version); 244 pp[2] = cpu_to_le32(hdr->first_rec_offset); 245 pp[3] = cpu_to_le32(hdr->tbl_size); 246 pp[4] = cpu_to_le32(hdr->checksum); 247 } 248 249 static void 250 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 251 unsigned char *buf) 252 { 253 u32 *pp = (uint32_t *)buf; 254 255 hdr->header = le32_to_cpu(pp[0]); 256 hdr->version = le32_to_cpu(pp[1]); 257 hdr->first_rec_offset = le32_to_cpu(pp[2]); 258 hdr->tbl_size = le32_to_cpu(pp[3]); 259 hdr->checksum = le32_to_cpu(pp[4]); 260 } 261 262 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 263 { 264 u8 buf[RAS_TABLE_HEADER_SIZE]; 265 struct amdgpu_device *adev = to_amdgpu_device(control); 266 int res; 267 268 memset(buf, 0, sizeof(buf)); 269 __encode_table_header_to_buf(&control->tbl_hdr, buf); 270 271 /* i2c may be unstable in gpu reset */ 272 down_read(&adev->reset_domain->sem); 273 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 274 control->i2c_address + 275 control->ras_header_offset, 276 buf, RAS_TABLE_HEADER_SIZE); 277 up_read(&adev->reset_domain->sem); 278 279 if (res < 0) { 280 DRM_ERROR("Failed to write EEPROM table header:%d", res); 281 } else if (res < RAS_TABLE_HEADER_SIZE) { 282 DRM_ERROR("Short write:%d out of %d\n", 283 res, RAS_TABLE_HEADER_SIZE); 284 res = -EIO; 285 } else { 286 res = 0; 287 } 288 289 return res; 290 } 291 292 static void 293 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 294 unsigned char *buf) 295 { 296 u32 *pp = (uint32_t *)buf; 297 u32 tmp; 298 299 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 300 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 301 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 302 pp[0] = cpu_to_le32(tmp); 303 } 304 305 static void 306 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 307 unsigned char *buf) 308 { 309 u32 *pp = (uint32_t *)buf; 310 u32 tmp; 311 312 tmp = le32_to_cpu(pp[0]); 313 rai->rma_status = tmp & 0xFF; 314 rai->health_percent = (tmp >> 8) & 0xFF; 315 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 316 } 317 318 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 319 { 320 struct amdgpu_device *adev = to_amdgpu_device(control); 321 u8 *buf; 322 int res; 323 324 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 325 if (!buf) { 326 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 327 return -ENOMEM; 328 } 329 330 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 331 332 /* i2c may be unstable in gpu reset */ 333 down_read(&adev->reset_domain->sem); 334 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 335 control->i2c_address + 336 control->ras_info_offset, 337 buf, RAS_TABLE_V2_1_INFO_SIZE); 338 up_read(&adev->reset_domain->sem); 339 340 if (res < 0) { 341 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 342 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 343 DRM_ERROR("Short write:%d out of %d\n", 344 res, RAS_TABLE_V2_1_INFO_SIZE); 345 res = -EIO; 346 } else { 347 res = 0; 348 } 349 350 kfree(buf); 351 352 return res; 353 } 354 355 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 356 { 357 int ii; 358 u8 *pp, csum; 359 size_t sz; 360 361 /* Header checksum, skip checksum field in the calculation */ 362 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 363 pp = (u8 *) &control->tbl_hdr; 364 csum = 0; 365 for (ii = 0; ii < sz; ii++, pp++) 366 csum += *pp; 367 368 return csum; 369 } 370 371 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 372 { 373 int ii; 374 u8 *pp, csum; 375 size_t sz; 376 377 sz = sizeof(control->tbl_rai); 378 pp = (u8 *) &control->tbl_rai; 379 csum = 0; 380 for (ii = 0; ii < sz; ii++, pp++) 381 csum += *pp; 382 383 return csum; 384 } 385 386 static int amdgpu_ras_eeprom_correct_header_tag( 387 struct amdgpu_ras_eeprom_control *control, 388 uint32_t header) 389 { 390 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 391 u8 *hh; 392 int res; 393 u8 csum; 394 395 csum = -hdr->checksum; 396 397 hh = (void *) &hdr->header; 398 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 399 hh = (void *) &header; 400 csum += hh[0] + hh[1] + hh[2] + hh[3]; 401 csum = -csum; 402 mutex_lock(&control->ras_tbl_mutex); 403 hdr->header = header; 404 hdr->checksum = csum; 405 res = __write_table_header(control); 406 mutex_unlock(&control->ras_tbl_mutex); 407 408 return res; 409 } 410 411 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 412 { 413 struct amdgpu_device *adev = to_amdgpu_device(control); 414 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 415 416 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 417 case IP_VERSION(8, 10, 0): 418 hdr->version = RAS_TABLE_VER_V2_1; 419 return; 420 case IP_VERSION(12, 0, 0): 421 case IP_VERSION(12, 5, 0): 422 hdr->version = RAS_TABLE_VER_V3; 423 return; 424 default: 425 hdr->version = RAS_TABLE_VER_V1; 426 return; 427 } 428 } 429 430 /** 431 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 432 * @control: pointer to control structure 433 * 434 * Reset the contents of the header of the RAS EEPROM table. 435 * Return 0 on success, -errno on error. 436 */ 437 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 438 { 439 struct amdgpu_device *adev = to_amdgpu_device(control); 440 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 441 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 442 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 443 u8 csum; 444 int res; 445 446 mutex_lock(&control->ras_tbl_mutex); 447 448 hdr->header = RAS_TABLE_HDR_VAL; 449 amdgpu_ras_set_eeprom_table_version(control); 450 451 if (hdr->version >= RAS_TABLE_VER_V2_1) { 452 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 453 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 454 RAS_TABLE_V2_1_INFO_SIZE; 455 rai->rma_status = GPU_HEALTH_USABLE; 456 /** 457 * GPU health represented as a percentage. 458 * 0 means worst health, 100 means fully health. 459 */ 460 rai->health_percent = 100; 461 /* ecc_page_threshold = 0 means disable bad page retirement */ 462 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 463 } else { 464 hdr->first_rec_offset = RAS_RECORD_START; 465 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 466 } 467 468 csum = __calc_hdr_byte_sum(control); 469 if (hdr->version >= RAS_TABLE_VER_V2_1) 470 csum += __calc_ras_info_byte_sum(control); 471 csum = -csum; 472 hdr->checksum = csum; 473 res = __write_table_header(control); 474 if (!res && hdr->version > RAS_TABLE_VER_V1) 475 res = __write_table_ras_info(control); 476 477 control->ras_num_recs = 0; 478 control->ras_num_bad_pages = 0; 479 control->ras_num_mca_recs = 0; 480 control->ras_num_pa_recs = 0; 481 control->ras_fri = 0; 482 483 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); 484 485 control->bad_channel_bitmap = 0; 486 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 487 con->update_channel_flag = false; 488 489 amdgpu_ras_debugfs_set_ret_size(control); 490 491 mutex_unlock(&control->ras_tbl_mutex); 492 493 return res; 494 } 495 496 static void 497 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 498 struct eeprom_table_record *record, 499 unsigned char *buf) 500 { 501 __le64 tmp = 0; 502 int i = 0; 503 504 /* Next are all record fields according to EEPROM page spec in LE foramt */ 505 buf[i++] = record->err_type; 506 507 buf[i++] = record->bank; 508 509 tmp = cpu_to_le64(record->ts); 510 memcpy(buf + i, &tmp, 8); 511 i += 8; 512 513 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 514 memcpy(buf + i, &tmp, 6); 515 i += 6; 516 517 buf[i++] = record->mem_channel; 518 buf[i++] = record->mcumc_id; 519 520 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 521 memcpy(buf + i, &tmp, 6); 522 } 523 524 static void 525 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 526 struct eeprom_table_record *record, 527 unsigned char *buf) 528 { 529 __le64 tmp = 0; 530 int i = 0; 531 532 /* Next are all record fields according to EEPROM page spec in LE foramt */ 533 record->err_type = buf[i++]; 534 535 record->bank = buf[i++]; 536 537 memcpy(&tmp, buf + i, 8); 538 record->ts = le64_to_cpu(tmp); 539 i += 8; 540 541 memcpy(&tmp, buf + i, 6); 542 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 543 i += 6; 544 545 record->mem_channel = buf[i++]; 546 record->mcumc_id = buf[i++]; 547 548 memcpy(&tmp, buf + i, 6); 549 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 550 } 551 552 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 553 { 554 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 555 556 if (!__is_ras_eeprom_supported(adev) || 557 !amdgpu_bad_page_threshold) 558 return false; 559 560 /* skip check eeprom table for VEGA20 Gaming */ 561 if (!con) 562 return false; 563 else 564 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 565 return false; 566 567 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 568 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold) 569 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 570 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold); 571 if ((amdgpu_bad_page_threshold == -1) || 572 (amdgpu_bad_page_threshold == -2)) { 573 dev_warn(adev->dev, 574 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 575 return false; 576 } else { 577 dev_warn(adev->dev, 578 "Please consider adjusting the customized threshold.\n"); 579 return true; 580 } 581 } 582 583 return false; 584 } 585 586 /** 587 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 588 * @control: pointer to control structure 589 * @buf: pointer to buffer containing data to write 590 * @fri: start writing at this index 591 * @num: number of records to write 592 * 593 * The caller must hold the table mutex in @control. 594 * Return 0 on success, -errno otherwise. 595 */ 596 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 597 u8 *buf, const u32 fri, const u32 num) 598 { 599 struct amdgpu_device *adev = to_amdgpu_device(control); 600 u32 buf_size; 601 int res; 602 603 /* i2c may be unstable in gpu reset */ 604 down_read(&adev->reset_domain->sem); 605 buf_size = num * RAS_TABLE_RECORD_SIZE; 606 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 607 control->i2c_address + 608 RAS_INDEX_TO_OFFSET(control, fri), 609 buf, buf_size); 610 up_read(&adev->reset_domain->sem); 611 if (res < 0) { 612 DRM_ERROR("Writing %d EEPROM table records error:%d", 613 num, res); 614 } else if (res < buf_size) { 615 /* Short write, return error. 616 */ 617 DRM_ERROR("Wrote %d records out of %d", 618 res / RAS_TABLE_RECORD_SIZE, num); 619 res = -EIO; 620 } else { 621 res = 0; 622 } 623 624 return res; 625 } 626 627 static int 628 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 629 struct eeprom_table_record *record, 630 const u32 num) 631 { 632 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 633 struct amdgpu_device *adev = to_amdgpu_device(control); 634 u32 a, b, i; 635 u8 *buf, *pp; 636 int res; 637 638 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 639 if (!buf) 640 return -ENOMEM; 641 642 /* Encode all of them in one go. 643 */ 644 pp = buf; 645 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 646 __encode_table_record_to_buf(control, &record[i], pp); 647 648 /* update bad channel bitmap */ 649 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 650 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 651 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 652 con->update_channel_flag = true; 653 } 654 } 655 656 /* a, first record index to write into. 657 * b, last record index to write into. 658 * a = first index to read (fri) + number of records in the table, 659 * b = a + @num - 1. 660 * Let N = control->ras_max_num_record_count, then we have, 661 * case 0: 0 <= a <= b < N, 662 * just append @num records starting at a; 663 * case 1: 0 <= a < N <= b, 664 * append (N - a) records starting at a, and 665 * append the remainder, b % N + 1, starting at 0. 666 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 667 * case 2a: 0 <= a <= b < N 668 * append num records starting at a; and fix fri if b overwrote it, 669 * and since a <= b, if b overwrote it then a must've also, 670 * and if b didn't overwrite it, then a didn't also. 671 * case 2b: 0 <= b < a < N 672 * write num records starting at a, which wraps around 0=N 673 * and overwrite fri unconditionally. Now from case 2a, 674 * this means that b eclipsed fri to overwrite it and wrap 675 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 676 * set fri = b + 1 (mod N). 677 * Now, since fri is updated in every case, except the trivial case 0, 678 * the number of records present in the table after writing, is, 679 * num_recs - 1 = b - fri (mod N), and we take the positive value, 680 * by adding an arbitrary multiple of N before taking the modulo N 681 * as shown below. 682 */ 683 a = control->ras_fri + control->ras_num_recs; 684 b = a + num - 1; 685 if (b < control->ras_max_record_count) { 686 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 687 } else if (a < control->ras_max_record_count) { 688 u32 g0, g1; 689 690 g0 = control->ras_max_record_count - a; 691 g1 = b % control->ras_max_record_count + 1; 692 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 693 if (res) 694 goto Out; 695 res = __amdgpu_ras_eeprom_write(control, 696 buf + g0 * RAS_TABLE_RECORD_SIZE, 697 0, g1); 698 if (res) 699 goto Out; 700 if (g1 > control->ras_fri) 701 control->ras_fri = g1 % control->ras_max_record_count; 702 } else { 703 a %= control->ras_max_record_count; 704 b %= control->ras_max_record_count; 705 706 if (a <= b) { 707 /* Note that, b - a + 1 = num. */ 708 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 709 if (res) 710 goto Out; 711 if (b >= control->ras_fri) 712 control->ras_fri = (b + 1) % control->ras_max_record_count; 713 } else { 714 u32 g0, g1; 715 716 /* b < a, which means, we write from 717 * a to the end of the table, and from 718 * the start of the table to b. 719 */ 720 g0 = control->ras_max_record_count - a; 721 g1 = b + 1; 722 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 723 if (res) 724 goto Out; 725 res = __amdgpu_ras_eeprom_write(control, 726 buf + g0 * RAS_TABLE_RECORD_SIZE, 727 0, g1); 728 if (res) 729 goto Out; 730 control->ras_fri = g1 % control->ras_max_record_count; 731 } 732 } 733 control->ras_num_recs = 1 + (control->ras_max_record_count + b 734 - control->ras_fri) 735 % control->ras_max_record_count; 736 737 /*old asics only save pa to eeprom like before*/ 738 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) 739 control->ras_num_pa_recs += num; 740 else 741 control->ras_num_mca_recs += num; 742 743 control->ras_num_bad_pages = control->ras_num_pa_recs + 744 control->ras_num_mca_recs * adev->umc.retire_unit; 745 Out: 746 kfree(buf); 747 return res; 748 } 749 750 static int 751 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 752 { 753 struct amdgpu_device *adev = to_amdgpu_device(control); 754 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 755 u8 *buf, *pp, csum; 756 u32 buf_size; 757 int res; 758 759 /* Modify the header if it exceeds. 760 */ 761 if (amdgpu_bad_page_threshold != 0 && 762 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 763 dev_warn(adev->dev, 764 "Saved bad pages %d reaches threshold value %d\n", 765 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 766 if ((amdgpu_bad_page_threshold != -1) && 767 (amdgpu_bad_page_threshold != -2)) { 768 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 769 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 770 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 771 control->tbl_rai.health_percent = 0; 772 } 773 ras->is_rma = true; 774 /* ignore the -ENOTSUPP return value */ 775 amdgpu_dpm_send_rma_reason(adev); 776 } 777 } 778 779 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 780 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 781 RAS_TABLE_V2_1_INFO_SIZE + 782 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 783 else 784 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 785 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 786 control->tbl_hdr.checksum = 0; 787 788 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 789 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 790 if (!buf) { 791 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 792 control->tbl_hdr.tbl_size); 793 res = -ENOMEM; 794 goto Out; 795 } 796 797 down_read(&adev->reset_domain->sem); 798 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 799 control->i2c_address + 800 control->ras_record_offset, 801 buf, buf_size); 802 up_read(&adev->reset_domain->sem); 803 if (res < 0) { 804 DRM_ERROR("EEPROM failed reading records:%d\n", 805 res); 806 goto Out; 807 } else if (res < buf_size) { 808 DRM_ERROR("EEPROM read %d out of %d bytes\n", 809 res, buf_size); 810 res = -EIO; 811 goto Out; 812 } 813 814 /** 815 * bad page records have been stored in eeprom, 816 * now calculate gpu health percent 817 */ 818 if (amdgpu_bad_page_threshold != 0 && 819 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 820 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) 821 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 822 control->ras_num_bad_pages) * 100) / 823 ras->bad_page_cnt_threshold; 824 825 /* Recalc the checksum. 826 */ 827 csum = 0; 828 for (pp = buf; pp < buf + buf_size; pp++) 829 csum += *pp; 830 831 csum += __calc_hdr_byte_sum(control); 832 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 833 csum += __calc_ras_info_byte_sum(control); 834 /* avoid sign extension when assigning to "checksum" */ 835 csum = -csum; 836 control->tbl_hdr.checksum = csum; 837 res = __write_table_header(control); 838 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 839 res = __write_table_ras_info(control); 840 Out: 841 kfree(buf); 842 return res; 843 } 844 845 /** 846 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 847 * @control: pointer to control structure 848 * @record: array of records to append 849 * @num: number of records in @record array 850 * 851 * Append @num records to the table, calculate the checksum and write 852 * the table back to EEPROM. The maximum number of records that 853 * can be appended is between 1 and control->ras_max_record_count, 854 * regardless of how many records are already stored in the table. 855 * 856 * Return 0 on success or if EEPROM is not supported, -errno on error. 857 */ 858 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 859 struct eeprom_table_record *record, 860 const u32 num) 861 { 862 struct amdgpu_device *adev = to_amdgpu_device(control); 863 int res, i; 864 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 865 866 if (!__is_ras_eeprom_supported(adev)) 867 return 0; 868 869 if (num == 0) { 870 DRM_ERROR("will not append 0 records\n"); 871 return -EINVAL; 872 } else if (num > control->ras_max_record_count) { 873 DRM_ERROR("cannot append %d records than the size of table %d\n", 874 num, control->ras_max_record_count); 875 return -EINVAL; 876 } 877 878 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 879 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 880 881 /* set the new channel index flag */ 882 for (i = 0; i < num; i++) 883 record[i].retired_page |= (nps << UMC_NPS_SHIFT); 884 885 mutex_lock(&control->ras_tbl_mutex); 886 887 res = amdgpu_ras_eeprom_append_table(control, record, num); 888 if (!res) 889 res = amdgpu_ras_eeprom_update_header(control); 890 if (!res) 891 amdgpu_ras_debugfs_set_ret_size(control); 892 893 mutex_unlock(&control->ras_tbl_mutex); 894 895 /* clear channel index flag, the flag is only saved on eeprom */ 896 for (i = 0; i < num; i++) 897 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT); 898 899 return res; 900 } 901 902 /** 903 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 904 * @control: pointer to control structure 905 * @buf: pointer to buffer to read into 906 * @fri: first record index, start reading at this index, absolute index 907 * @num: number of records to read 908 * 909 * The caller must hold the table mutex in @control. 910 * Return 0 on success, -errno otherwise. 911 */ 912 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 913 u8 *buf, const u32 fri, const u32 num) 914 { 915 struct amdgpu_device *adev = to_amdgpu_device(control); 916 u32 buf_size; 917 int res; 918 919 /* i2c may be unstable in gpu reset */ 920 down_read(&adev->reset_domain->sem); 921 buf_size = num * RAS_TABLE_RECORD_SIZE; 922 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 923 control->i2c_address + 924 RAS_INDEX_TO_OFFSET(control, fri), 925 buf, buf_size); 926 up_read(&adev->reset_domain->sem); 927 if (res < 0) { 928 DRM_ERROR("Reading %d EEPROM table records error:%d", 929 num, res); 930 } else if (res < buf_size) { 931 /* Short read, return error. 932 */ 933 DRM_ERROR("Read %d records out of %d", 934 res / RAS_TABLE_RECORD_SIZE, num); 935 res = -EIO; 936 } else { 937 res = 0; 938 } 939 940 return res; 941 } 942 943 /** 944 * amdgpu_ras_eeprom_read -- read EEPROM 945 * @control: pointer to control structure 946 * @record: array of records to read into 947 * @num: number of records in @record 948 * 949 * Reads num records from the RAS table in EEPROM and 950 * writes the data into @record array. 951 * 952 * Returns 0 on success, -errno on error. 953 */ 954 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 955 struct eeprom_table_record *record, 956 const u32 num) 957 { 958 struct amdgpu_device *adev = to_amdgpu_device(control); 959 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 960 int i, res; 961 u8 *buf, *pp; 962 u32 g0, g1; 963 964 if (!__is_ras_eeprom_supported(adev)) 965 return 0; 966 967 if (num == 0) { 968 DRM_ERROR("will not read 0 records\n"); 969 return -EINVAL; 970 } else if (num > control->ras_num_recs) { 971 DRM_ERROR("too many records to read:%d available:%d\n", 972 num, control->ras_num_recs); 973 return -EINVAL; 974 } 975 976 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 977 if (!buf) 978 return -ENOMEM; 979 980 /* Determine how many records to read, from the first record 981 * index, fri, to the end of the table, and from the beginning 982 * of the table, such that the total number of records is 983 * @num, and we handle wrap around when fri > 0 and 984 * fri + num > RAS_MAX_RECORD_COUNT. 985 * 986 * First we compute the index of the last element 987 * which would be fetched from each region, 988 * g0 is in [fri, fri + num - 1], and 989 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 990 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 991 * the last element to fetch, we set g0 to _the number_ 992 * of elements to fetch, @num, since we know that the last 993 * indexed to be fetched does not exceed the table. 994 * 995 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 996 * we set g0 to the number of elements to read 997 * until the end of the table, and g1 to the number of 998 * elements to read from the beginning of the table. 999 */ 1000 g0 = control->ras_fri + num - 1; 1001 g1 = g0 % control->ras_max_record_count; 1002 if (g0 < control->ras_max_record_count) { 1003 g0 = num; 1004 g1 = 0; 1005 } else { 1006 g0 = control->ras_max_record_count - control->ras_fri; 1007 g1 += 1; 1008 } 1009 1010 mutex_lock(&control->ras_tbl_mutex); 1011 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 1012 if (res) 1013 goto Out; 1014 if (g1) { 1015 res = __amdgpu_ras_eeprom_read(control, 1016 buf + g0 * RAS_TABLE_RECORD_SIZE, 1017 0, g1); 1018 if (res) 1019 goto Out; 1020 } 1021 1022 res = 0; 1023 1024 /* Read up everything? Then transform. 1025 */ 1026 pp = buf; 1027 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 1028 __decode_table_record_from_buf(control, &record[i], pp); 1029 1030 /* update bad channel bitmap */ 1031 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1032 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1033 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1034 con->update_channel_flag = true; 1035 } 1036 } 1037 Out: 1038 kfree(buf); 1039 mutex_unlock(&control->ras_tbl_mutex); 1040 1041 return res; 1042 } 1043 1044 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1045 { 1046 /* get available eeprom table version first before eeprom table init */ 1047 amdgpu_ras_set_eeprom_table_version(control); 1048 1049 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1050 return RAS_MAX_RECORD_COUNT_V2_1; 1051 else 1052 return RAS_MAX_RECORD_COUNT; 1053 } 1054 1055 static ssize_t 1056 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1057 size_t size, loff_t *pos) 1058 { 1059 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1060 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1061 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1062 u8 data[50]; 1063 int res; 1064 1065 if (!size) 1066 return size; 1067 1068 if (!ras || !control) { 1069 res = snprintf(data, sizeof(data), "Not supported\n"); 1070 } else { 1071 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1072 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1073 } 1074 1075 if (*pos >= res) 1076 return 0; 1077 1078 res -= *pos; 1079 res = min_t(size_t, res, size); 1080 1081 if (copy_to_user(buf, &data[*pos], res)) 1082 return -EFAULT; 1083 1084 *pos += res; 1085 1086 return res; 1087 } 1088 1089 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1090 .owner = THIS_MODULE, 1091 .read = amdgpu_ras_debugfs_eeprom_size_read, 1092 .write = NULL, 1093 .llseek = default_llseek, 1094 }; 1095 1096 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1097 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1098 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1099 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1100 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1101 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1102 1103 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1104 "ignore", 1105 "re", 1106 "ue", 1107 }; 1108 1109 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1110 { 1111 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1112 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1113 } 1114 1115 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1116 { 1117 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1118 eeprom_control); 1119 struct dentry *de = ras->de_ras_eeprom_table; 1120 1121 if (de) 1122 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1123 } 1124 1125 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1126 size_t size, loff_t *pos) 1127 { 1128 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1129 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1130 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1131 const size_t orig_size = size; 1132 int res = -EFAULT; 1133 size_t data_len; 1134 1135 mutex_lock(&control->ras_tbl_mutex); 1136 1137 /* We want *pos - data_len > 0, which means there's 1138 * bytes to be printed from data. 1139 */ 1140 data_len = strlen(tbl_hdr_str); 1141 if (*pos < data_len) { 1142 data_len -= *pos; 1143 data_len = min_t(size_t, data_len, size); 1144 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1145 goto Out; 1146 buf += data_len; 1147 size -= data_len; 1148 *pos += data_len; 1149 } 1150 1151 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1152 if (*pos < data_len && size > 0) { 1153 u8 data[tbl_hdr_fmt_size + 1]; 1154 loff_t lpos; 1155 1156 snprintf(data, sizeof(data), tbl_hdr_fmt, 1157 control->tbl_hdr.header, 1158 control->tbl_hdr.version, 1159 control->tbl_hdr.first_rec_offset, 1160 control->tbl_hdr.tbl_size, 1161 control->tbl_hdr.checksum); 1162 1163 data_len -= *pos; 1164 data_len = min_t(size_t, data_len, size); 1165 lpos = *pos - strlen(tbl_hdr_str); 1166 if (copy_to_user(buf, &data[lpos], data_len)) 1167 goto Out; 1168 buf += data_len; 1169 size -= data_len; 1170 *pos += data_len; 1171 } 1172 1173 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1174 if (*pos < data_len && size > 0) { 1175 loff_t lpos; 1176 1177 data_len -= *pos; 1178 data_len = min_t(size_t, data_len, size); 1179 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1180 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1181 goto Out; 1182 buf += data_len; 1183 size -= data_len; 1184 *pos += data_len; 1185 } 1186 1187 data_len = amdgpu_ras_debugfs_table_size(control); 1188 if (*pos < data_len && size > 0) { 1189 u8 dare[RAS_TABLE_RECORD_SIZE]; 1190 u8 data[rec_hdr_fmt_size + 1]; 1191 struct eeprom_table_record record; 1192 int s, r; 1193 1194 /* Find the starting record index 1195 */ 1196 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1197 strlen(rec_hdr_str); 1198 s = s / rec_hdr_fmt_size; 1199 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1200 strlen(rec_hdr_str); 1201 r = r % rec_hdr_fmt_size; 1202 1203 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1204 u32 ai = RAS_RI_TO_AI(control, s); 1205 /* Read a single record 1206 */ 1207 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1208 if (res) 1209 goto Out; 1210 __decode_table_record_from_buf(control, &record, dare); 1211 snprintf(data, sizeof(data), rec_hdr_fmt, 1212 s, 1213 RAS_INDEX_TO_OFFSET(control, ai), 1214 record_err_type_str[record.err_type], 1215 record.bank, 1216 record.ts, 1217 record.offset, 1218 record.mem_channel, 1219 record.mcumc_id, 1220 record.retired_page); 1221 1222 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1223 if (copy_to_user(buf, &data[r], data_len)) { 1224 res = -EFAULT; 1225 goto Out; 1226 } 1227 buf += data_len; 1228 size -= data_len; 1229 *pos += data_len; 1230 r = 0; 1231 } 1232 } 1233 res = 0; 1234 Out: 1235 mutex_unlock(&control->ras_tbl_mutex); 1236 return res < 0 ? res : orig_size - size; 1237 } 1238 1239 static ssize_t 1240 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1241 size_t size, loff_t *pos) 1242 { 1243 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1244 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1245 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1246 u8 data[81]; 1247 int res; 1248 1249 if (!size) 1250 return size; 1251 1252 if (!ras || !control) { 1253 res = snprintf(data, sizeof(data), "Not supported\n"); 1254 if (*pos >= res) 1255 return 0; 1256 1257 res -= *pos; 1258 res = min_t(size_t, res, size); 1259 1260 if (copy_to_user(buf, &data[*pos], res)) 1261 return -EFAULT; 1262 1263 *pos += res; 1264 1265 return res; 1266 } else { 1267 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1268 } 1269 } 1270 1271 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1272 .owner = THIS_MODULE, 1273 .read = amdgpu_ras_debugfs_eeprom_table_read, 1274 .write = NULL, 1275 .llseek = default_llseek, 1276 }; 1277 1278 /** 1279 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1280 * @control: pointer to control structure 1281 * 1282 * Check the checksum of the stored in EEPROM RAS table. 1283 * 1284 * Return 0 if the checksum is correct, 1285 * positive if it is not correct, and 1286 * -errno on I/O error. 1287 */ 1288 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1289 { 1290 struct amdgpu_device *adev = to_amdgpu_device(control); 1291 int buf_size, res; 1292 u8 csum, *buf, *pp; 1293 1294 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1295 buf_size = RAS_TABLE_HEADER_SIZE + 1296 RAS_TABLE_V2_1_INFO_SIZE + 1297 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1298 else 1299 buf_size = RAS_TABLE_HEADER_SIZE + 1300 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1301 1302 buf = kzalloc(buf_size, GFP_KERNEL); 1303 if (!buf) { 1304 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1305 return -ENOMEM; 1306 } 1307 1308 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1309 control->i2c_address + 1310 control->ras_header_offset, 1311 buf, buf_size); 1312 if (res < buf_size) { 1313 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1314 /* On partial reads, return -EIO. 1315 */ 1316 if (res >= 0) 1317 res = -EIO; 1318 goto Out; 1319 } 1320 1321 csum = 0; 1322 for (pp = buf; pp < buf + buf_size; pp++) 1323 csum += *pp; 1324 Out: 1325 kfree(buf); 1326 return res < 0 ? res : csum; 1327 } 1328 1329 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1330 { 1331 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1332 struct amdgpu_device *adev = to_amdgpu_device(control); 1333 unsigned char *buf; 1334 int res; 1335 1336 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1337 if (!buf) { 1338 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1339 return -ENOMEM; 1340 } 1341 1342 /** 1343 * EEPROM table V2_1 supports ras info, 1344 * read EEPROM table ras info 1345 */ 1346 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1347 control->i2c_address + control->ras_info_offset, 1348 buf, RAS_TABLE_V2_1_INFO_SIZE); 1349 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1350 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1351 res = res >= 0 ? -EIO : res; 1352 goto Out; 1353 } 1354 1355 __decode_table_ras_info_from_buf(rai, buf); 1356 1357 Out: 1358 kfree(buf); 1359 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1360 } 1361 1362 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1363 { 1364 struct amdgpu_device *adev = to_amdgpu_device(control); 1365 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1366 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1367 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1368 int res; 1369 1370 ras->is_rma = false; 1371 1372 if (!__is_ras_eeprom_supported(adev)) 1373 return 0; 1374 1375 /* Verify i2c adapter is initialized */ 1376 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1377 return -ENOENT; 1378 1379 if (!__get_eeprom_i2c_addr(adev, control)) 1380 return -EINVAL; 1381 1382 control->ras_header_offset = RAS_HDR_START; 1383 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1384 mutex_init(&control->ras_tbl_mutex); 1385 1386 /* Read the table header from EEPROM address */ 1387 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1388 control->i2c_address + control->ras_header_offset, 1389 buf, RAS_TABLE_HEADER_SIZE); 1390 if (res < RAS_TABLE_HEADER_SIZE) { 1391 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1392 return res >= 0 ? -EIO : res; 1393 } 1394 1395 __decode_table_header_from_buf(hdr, buf); 1396 1397 if (hdr->header != RAS_TABLE_HDR_VAL && 1398 hdr->header != RAS_TABLE_HDR_BAD) { 1399 dev_info(adev->dev, "Creating a new EEPROM table"); 1400 return amdgpu_ras_eeprom_reset_table(control); 1401 } 1402 1403 switch (hdr->version) { 1404 case RAS_TABLE_VER_V2_1: 1405 case RAS_TABLE_VER_V3: 1406 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1407 control->ras_record_offset = RAS_RECORD_START_V2_1; 1408 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1409 break; 1410 case RAS_TABLE_VER_V1: 1411 control->ras_num_recs = RAS_NUM_RECS(hdr); 1412 control->ras_record_offset = RAS_RECORD_START; 1413 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1414 break; 1415 default: 1416 dev_err(adev->dev, 1417 "RAS header invalid, unsupported version: %u", 1418 hdr->version); 1419 return -EINVAL; 1420 } 1421 1422 if (control->ras_num_recs > control->ras_max_record_count) { 1423 dev_err(adev->dev, 1424 "RAS header invalid, records in header: %u max allowed :%u", 1425 control->ras_num_recs, control->ras_max_record_count); 1426 return -EINVAL; 1427 } 1428 1429 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1430 control->ras_num_mca_recs = 0; 1431 control->ras_num_pa_recs = 0; 1432 return 0; 1433 } 1434 1435 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1436 { 1437 struct amdgpu_device *adev = to_amdgpu_device(control); 1438 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1439 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1440 int res = 0; 1441 1442 if (!__is_ras_eeprom_supported(adev)) 1443 return 0; 1444 1445 /* Verify i2c adapter is initialized */ 1446 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1447 return -ENOENT; 1448 1449 if (!__get_eeprom_i2c_addr(adev, control)) 1450 return -EINVAL; 1451 1452 control->ras_num_bad_pages = control->ras_num_pa_recs + 1453 control->ras_num_mca_recs * adev->umc.retire_unit; 1454 1455 if (hdr->header == RAS_TABLE_HDR_VAL) { 1456 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1457 control->ras_num_bad_pages); 1458 1459 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1460 res = __read_table_ras_info(control); 1461 if (res) 1462 return res; 1463 } 1464 1465 res = __verify_ras_table_checksum(control); 1466 if (res) 1467 dev_err(adev->dev, 1468 "RAS table incorrect checksum or error:%d\n", 1469 res); 1470 1471 /* Warn if we are at 90% of the threshold or above 1472 */ 1473 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1474 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1475 control->ras_num_bad_pages, 1476 ras->bad_page_cnt_threshold); 1477 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1478 amdgpu_bad_page_threshold != 0) { 1479 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1480 res = __read_table_ras_info(control); 1481 if (res) 1482 return res; 1483 } 1484 1485 res = __verify_ras_table_checksum(control); 1486 if (res) { 1487 dev_err(adev->dev, 1488 "RAS Table incorrect checksum or error:%d\n", 1489 res); 1490 return -EINVAL; 1491 } 1492 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { 1493 /* This means that, the threshold was increased since 1494 * the last time the system was booted, and now, 1495 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1496 * so that at least one more record can be saved, 1497 * before the page count threshold is reached. 1498 */ 1499 dev_info(adev->dev, 1500 "records:%d threshold:%d, resetting " 1501 "RAS table header signature", 1502 control->ras_num_bad_pages, 1503 ras->bad_page_cnt_threshold); 1504 res = amdgpu_ras_eeprom_correct_header_tag(control, 1505 RAS_TABLE_HDR_VAL); 1506 } else { 1507 dev_warn(adev->dev, 1508 "RAS records:%d exceed threshold:%d\n", 1509 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1510 if ((amdgpu_bad_page_threshold == -1) || 1511 (amdgpu_bad_page_threshold == -2)) { 1512 res = 0; 1513 dev_warn(adev->dev, 1514 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1515 } else { 1516 ras->is_rma = true; 1517 dev_warn(adev->dev, 1518 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1519 } 1520 } 1521 } 1522 1523 return res < 0 ? res : 0; 1524 } 1525