1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 #include "amdgpu_ras_mgr.h" 36 37 /* These are memory addresses as would be seen by one or more EEPROM 38 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 39 * set of EEPROM devices. They form a continuous memory space. 40 * 41 * The I2C device address includes the device type identifier, 1010b, 42 * which is a reserved value and indicates that this is an I2C EEPROM 43 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 44 * address, namely bits 18, 17, and 16. This makes up the 7 bit 45 * address sent on the I2C bus with bit 0 being the direction bit, 46 * which is not represented here, and sent by the hardware directly. 47 * 48 * For instance, 49 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 50 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 51 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 52 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 53 * address memory in a device or a device on the I2C bus, depending on 54 * the status of pins 1-3. See top of amdgpu_eeprom.c. 55 * 56 * The RAS table lives either at address 0 or address 40000h of EEPROM. 57 */ 58 #define EEPROM_I2C_MADDR_0 0x0 59 #define EEPROM_I2C_MADDR_4 0x40000 60 61 /* 62 * The 2 macros below represent the actual size in bytes that 63 * those entities occupy in the EEPROM memory. 64 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 65 * uses uint64 to store 6b fields such as retired_page. 66 */ 67 #define RAS_TABLE_HEADER_SIZE 20 68 #define RAS_TABLE_RECORD_SIZE 24 69 70 /* Table hdr is 'AMDR' */ 71 #define RAS_TABLE_HDR_VAL 0x414d4452 72 73 /* Bad GPU tag ‘BADG’ */ 74 #define RAS_TABLE_HDR_BAD 0x42414447 75 76 /* 77 * EEPROM Table structure v1 78 * --------------------------------- 79 * | | 80 * | EEPROM TABLE HEADER | 81 * | ( size 20 Bytes ) | 82 * | | 83 * --------------------------------- 84 * | | 85 * | BAD PAGE RECORD AREA | 86 * | | 87 * --------------------------------- 88 */ 89 90 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 91 #define RAS_TBL_SIZE_BYTES (256 * 1024) 92 #define RAS_TABLE_START 0 93 #define RAS_HDR_START RAS_TABLE_START 94 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 95 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 96 / RAS_TABLE_RECORD_SIZE) 97 98 /* 99 * EEPROM Table structrue v2.1 100 * --------------------------------- 101 * | | 102 * | EEPROM TABLE HEADER | 103 * | ( size 20 Bytes ) | 104 * | | 105 * --------------------------------- 106 * | | 107 * | EEPROM TABLE RAS INFO | 108 * | (available info size 4 Bytes) | 109 * | ( reserved size 252 Bytes ) | 110 * | | 111 * --------------------------------- 112 * | | 113 * | BAD PAGE RECORD AREA | 114 * | | 115 * --------------------------------- 116 */ 117 118 /* EEPROM Table V2_1 */ 119 #define RAS_TABLE_V2_1_INFO_SIZE 256 120 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 121 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 122 RAS_TABLE_V2_1_INFO_SIZE) 123 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 124 RAS_TABLE_V2_1_INFO_SIZE) \ 125 / RAS_TABLE_RECORD_SIZE) 126 127 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 128 * offset off of RAS_TABLE_START. That is, this is something you can 129 * add to control->i2c_address, and then tell I2C layer to read 130 * from/write to there. _N is the so called absolute index, 131 * because it starts right after the table header. 132 */ 133 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 134 (_N) * RAS_TABLE_RECORD_SIZE) 135 136 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 137 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 138 139 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 140 * of "fri", return the absolute record index off of the end of 141 * the table header. 142 */ 143 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 144 (_C)->ras_max_record_count) 145 146 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 147 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 148 149 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 150 RAS_TABLE_HEADER_SIZE - \ 151 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 152 153 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 154 155 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 156 { 157 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 158 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 159 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 160 case IP_VERSION(13, 0, 0): 161 case IP_VERSION(13, 0, 2): /* Aldebaran */ 162 case IP_VERSION(13, 0, 10): 163 return true; 164 case IP_VERSION(13, 0, 6): 165 case IP_VERSION(13, 0, 12): 166 case IP_VERSION(13, 0, 14): 167 return (adev->gmc.is_app_apu) ? false : true; 168 default: 169 return false; 170 } 171 } 172 173 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 174 struct amdgpu_ras_eeprom_control *control) 175 { 176 struct atom_context *atom_ctx = adev->mode_info.atom_context; 177 u8 i2c_addr; 178 179 if (!control) 180 return false; 181 182 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 183 /* The address given by VBIOS is an 8-bit, wire-format 184 * address, i.e. the most significant byte. 185 * 186 * Normalize it to a 19-bit EEPROM address. Remove the 187 * device type identifier and make it a 7-bit address; 188 * then make it a 19-bit EEPROM address. See top of 189 * amdgpu_eeprom.c. 190 */ 191 i2c_addr = (i2c_addr & 0x0F) >> 1; 192 control->i2c_address = ((u32) i2c_addr) << 16; 193 194 return true; 195 } 196 197 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 198 case IP_VERSION(11, 0, 2): 199 /* VEGA20 and ARCTURUS */ 200 if (adev->asic_type == CHIP_VEGA20) 201 control->i2c_address = EEPROM_I2C_MADDR_0; 202 else if (strnstr(atom_ctx->vbios_pn, 203 "D342", 204 sizeof(atom_ctx->vbios_pn))) 205 control->i2c_address = EEPROM_I2C_MADDR_0; 206 else 207 control->i2c_address = EEPROM_I2C_MADDR_4; 208 return true; 209 case IP_VERSION(11, 0, 7): 210 control->i2c_address = EEPROM_I2C_MADDR_0; 211 return true; 212 case IP_VERSION(13, 0, 2): 213 if (strnstr(atom_ctx->vbios_pn, "D673", 214 sizeof(atom_ctx->vbios_pn))) 215 control->i2c_address = EEPROM_I2C_MADDR_4; 216 else 217 control->i2c_address = EEPROM_I2C_MADDR_0; 218 return true; 219 case IP_VERSION(13, 0, 0): 220 if (strnstr(atom_ctx->vbios_pn, "D707", 221 sizeof(atom_ctx->vbios_pn))) 222 control->i2c_address = EEPROM_I2C_MADDR_0; 223 else 224 control->i2c_address = EEPROM_I2C_MADDR_4; 225 return true; 226 case IP_VERSION(13, 0, 6): 227 case IP_VERSION(13, 0, 10): 228 case IP_VERSION(13, 0, 12): 229 case IP_VERSION(13, 0, 14): 230 control->i2c_address = EEPROM_I2C_MADDR_4; 231 return true; 232 default: 233 return false; 234 } 235 } 236 237 static void 238 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 239 unsigned char *buf) 240 { 241 u32 *pp = (uint32_t *)buf; 242 243 pp[0] = cpu_to_le32(hdr->header); 244 pp[1] = cpu_to_le32(hdr->version); 245 pp[2] = cpu_to_le32(hdr->first_rec_offset); 246 pp[3] = cpu_to_le32(hdr->tbl_size); 247 pp[4] = cpu_to_le32(hdr->checksum); 248 } 249 250 static void 251 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 252 unsigned char *buf) 253 { 254 u32 *pp = (uint32_t *)buf; 255 256 hdr->header = le32_to_cpu(pp[0]); 257 hdr->version = le32_to_cpu(pp[1]); 258 hdr->first_rec_offset = le32_to_cpu(pp[2]); 259 hdr->tbl_size = le32_to_cpu(pp[3]); 260 hdr->checksum = le32_to_cpu(pp[4]); 261 } 262 263 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 264 { 265 u8 buf[RAS_TABLE_HEADER_SIZE]; 266 struct amdgpu_device *adev = to_amdgpu_device(control); 267 int res; 268 269 memset(buf, 0, sizeof(buf)); 270 __encode_table_header_to_buf(&control->tbl_hdr, buf); 271 272 /* i2c may be unstable in gpu reset */ 273 down_read(&adev->reset_domain->sem); 274 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 275 control->i2c_address + 276 control->ras_header_offset, 277 buf, RAS_TABLE_HEADER_SIZE); 278 up_read(&adev->reset_domain->sem); 279 280 if (res < 0) { 281 dev_err(adev->dev, "Failed to write EEPROM table header:%d", 282 res); 283 } else if (res < RAS_TABLE_HEADER_SIZE) { 284 dev_err(adev->dev, "Short write:%d out of %d\n", res, 285 RAS_TABLE_HEADER_SIZE); 286 res = -EIO; 287 } else { 288 res = 0; 289 } 290 291 return res; 292 } 293 294 static void 295 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 296 unsigned char *buf) 297 { 298 u32 *pp = (uint32_t *)buf; 299 u32 tmp; 300 301 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 302 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 303 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 304 pp[0] = cpu_to_le32(tmp); 305 } 306 307 static void 308 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 309 unsigned char *buf) 310 { 311 u32 *pp = (uint32_t *)buf; 312 u32 tmp; 313 314 tmp = le32_to_cpu(pp[0]); 315 rai->rma_status = tmp & 0xFF; 316 rai->health_percent = (tmp >> 8) & 0xFF; 317 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 318 } 319 320 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 321 { 322 struct amdgpu_device *adev = to_amdgpu_device(control); 323 u8 *buf; 324 int res; 325 326 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 327 if (!buf) { 328 dev_err(adev->dev, 329 "Failed to alloc buf to write table ras info\n"); 330 return -ENOMEM; 331 } 332 333 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 334 335 /* i2c may be unstable in gpu reset */ 336 down_read(&adev->reset_domain->sem); 337 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 338 control->i2c_address + 339 control->ras_info_offset, 340 buf, RAS_TABLE_V2_1_INFO_SIZE); 341 up_read(&adev->reset_domain->sem); 342 343 if (res < 0) { 344 dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", 345 res); 346 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 347 dev_err(adev->dev, "Short write:%d out of %d\n", res, 348 RAS_TABLE_V2_1_INFO_SIZE); 349 res = -EIO; 350 } else { 351 res = 0; 352 } 353 354 kfree(buf); 355 356 return res; 357 } 358 359 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 360 { 361 int ii; 362 u8 *pp, csum; 363 size_t sz; 364 365 /* Header checksum, skip checksum field in the calculation */ 366 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 367 pp = (u8 *) &control->tbl_hdr; 368 csum = 0; 369 for (ii = 0; ii < sz; ii++, pp++) 370 csum += *pp; 371 372 return csum; 373 } 374 375 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 376 { 377 int ii; 378 u8 *pp, csum; 379 size_t sz; 380 381 sz = sizeof(control->tbl_rai); 382 pp = (u8 *) &control->tbl_rai; 383 csum = 0; 384 for (ii = 0; ii < sz; ii++, pp++) 385 csum += *pp; 386 387 return csum; 388 } 389 390 static int amdgpu_ras_eeprom_correct_header_tag( 391 struct amdgpu_ras_eeprom_control *control, 392 uint32_t header) 393 { 394 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 395 u8 *hh; 396 int res; 397 u8 csum; 398 399 csum = -hdr->checksum; 400 401 hh = (void *) &hdr->header; 402 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 403 hh = (void *) &header; 404 csum += hh[0] + hh[1] + hh[2] + hh[3]; 405 csum = -csum; 406 mutex_lock(&control->ras_tbl_mutex); 407 hdr->header = header; 408 hdr->checksum = csum; 409 res = __write_table_header(control); 410 mutex_unlock(&control->ras_tbl_mutex); 411 412 return res; 413 } 414 415 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 416 { 417 struct amdgpu_device *adev = to_amdgpu_device(control); 418 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 419 420 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 421 case IP_VERSION(8, 10, 0): 422 hdr->version = RAS_TABLE_VER_V2_1; 423 return; 424 case IP_VERSION(12, 0, 0): 425 case IP_VERSION(12, 5, 0): 426 hdr->version = RAS_TABLE_VER_V3; 427 return; 428 default: 429 hdr->version = RAS_TABLE_VER_V1; 430 return; 431 } 432 } 433 434 /** 435 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 436 * @control: pointer to control structure 437 * 438 * Reset the contents of the header of the RAS EEPROM table. 439 * Return 0 on success, -errno on error. 440 */ 441 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 442 { 443 struct amdgpu_device *adev = to_amdgpu_device(control); 444 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 445 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 446 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 447 u32 erase_res = 0; 448 u8 csum; 449 int res; 450 451 mutex_lock(&control->ras_tbl_mutex); 452 453 if (!amdgpu_ras_smu_eeprom_supported(adev)) { 454 hdr->header = RAS_TABLE_HDR_VAL; 455 amdgpu_ras_set_eeprom_table_version(control); 456 457 if (hdr->version >= RAS_TABLE_VER_V2_1) { 458 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 459 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 460 RAS_TABLE_V2_1_INFO_SIZE; 461 rai->rma_status = GPU_HEALTH_USABLE; 462 463 control->ras_record_offset = RAS_RECORD_START_V2_1; 464 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 465 /** 466 * GPU health represented as a percentage. 467 * 0 means worst health, 100 means fully health. 468 */ 469 rai->health_percent = 100; 470 /* ecc_page_threshold = 0 means disable bad page retirement */ 471 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 472 } else { 473 hdr->first_rec_offset = RAS_RECORD_START; 474 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 475 476 control->ras_record_offset = RAS_RECORD_START; 477 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 478 } 479 480 csum = __calc_hdr_byte_sum(control); 481 if (hdr->version >= RAS_TABLE_VER_V2_1) 482 csum += __calc_ras_info_byte_sum(control); 483 csum = -csum; 484 hdr->checksum = csum; 485 res = __write_table_header(control); 486 if (!res && hdr->version > RAS_TABLE_VER_V1) 487 res = __write_table_ras_info(control); 488 } else { 489 res = amdgpu_ras_smu_erase_ras_table(adev, &erase_res); 490 if (res || erase_res) { 491 dev_warn(adev->dev, "RAS EEPROM reset failed, res:%d result:%d", 492 res, erase_res); 493 if (!res) 494 res = -EIO; 495 } 496 } 497 498 control->ras_num_recs = 0; 499 control->ras_num_bad_pages = 0; 500 control->ras_num_mca_recs = 0; 501 control->ras_num_pa_recs = 0; 502 control->ras_fri = 0; 503 504 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); 505 506 control->bad_channel_bitmap = 0; 507 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 508 con->update_channel_flag = false; 509 510 amdgpu_ras_debugfs_set_ret_size(control); 511 512 mutex_unlock(&control->ras_tbl_mutex); 513 514 return res; 515 } 516 517 static void 518 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 519 struct eeprom_table_record *record, 520 unsigned char *buf) 521 { 522 __le64 tmp = 0; 523 int i = 0; 524 525 /* Next are all record fields according to EEPROM page spec in LE foramt */ 526 buf[i++] = record->err_type; 527 528 buf[i++] = record->bank; 529 530 tmp = cpu_to_le64(record->ts); 531 memcpy(buf + i, &tmp, 8); 532 i += 8; 533 534 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 535 memcpy(buf + i, &tmp, 6); 536 i += 6; 537 538 buf[i++] = record->mem_channel; 539 buf[i++] = record->mcumc_id; 540 541 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 542 memcpy(buf + i, &tmp, 6); 543 } 544 545 static void 546 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 547 struct eeprom_table_record *record, 548 unsigned char *buf) 549 { 550 __le64 tmp = 0; 551 int i = 0; 552 553 /* Next are all record fields according to EEPROM page spec in LE foramt */ 554 record->err_type = buf[i++]; 555 556 record->bank = buf[i++]; 557 558 memcpy(&tmp, buf + i, 8); 559 record->ts = le64_to_cpu(tmp); 560 i += 8; 561 562 memcpy(&tmp, buf + i, 6); 563 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 564 i += 6; 565 566 record->mem_channel = buf[i++]; 567 record->mcumc_id = buf[i++]; 568 569 memcpy(&tmp, buf + i, 6); 570 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 571 } 572 573 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 574 { 575 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 576 577 if (amdgpu_uniras_enabled(adev)) 578 return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev); 579 580 if (!__is_ras_eeprom_supported(adev) || 581 !amdgpu_bad_page_threshold) 582 return false; 583 584 /* skip check eeprom table for VEGA20 Gaming */ 585 if (!con) 586 return false; 587 else 588 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 589 return false; 590 591 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 592 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold) 593 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 594 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold); 595 if ((amdgpu_bad_page_threshold == -1) || 596 (amdgpu_bad_page_threshold == -2)) { 597 dev_warn(adev->dev, 598 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 599 return false; 600 } else { 601 dev_warn(adev->dev, 602 "Please consider adjusting the customized threshold.\n"); 603 return true; 604 } 605 } 606 607 return false; 608 } 609 610 /** 611 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 612 * @control: pointer to control structure 613 * @buf: pointer to buffer containing data to write 614 * @fri: start writing at this index 615 * @num: number of records to write 616 * 617 * The caller must hold the table mutex in @control. 618 * Return 0 on success, -errno otherwise. 619 */ 620 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 621 u8 *buf, const u32 fri, const u32 num) 622 { 623 struct amdgpu_device *adev = to_amdgpu_device(control); 624 u32 buf_size; 625 int res; 626 627 /* i2c may be unstable in gpu reset */ 628 down_read(&adev->reset_domain->sem); 629 buf_size = num * RAS_TABLE_RECORD_SIZE; 630 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 631 control->i2c_address + 632 RAS_INDEX_TO_OFFSET(control, fri), 633 buf, buf_size); 634 up_read(&adev->reset_domain->sem); 635 if (res < 0) { 636 dev_err(adev->dev, "Writing %d EEPROM table records error:%d", 637 num, res); 638 } else if (res < buf_size) { 639 /* Short write, return error. 640 */ 641 dev_err(adev->dev, "Wrote %d records out of %d", 642 res / RAS_TABLE_RECORD_SIZE, num); 643 res = -EIO; 644 } else { 645 res = 0; 646 } 647 648 return res; 649 } 650 651 static int 652 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 653 struct eeprom_table_record *record, 654 const u32 num) 655 { 656 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 657 struct amdgpu_device *adev = to_amdgpu_device(control); 658 u32 a, b, i; 659 u8 *buf, *pp; 660 int res; 661 662 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 663 if (!buf) 664 return -ENOMEM; 665 666 /* Encode all of them in one go. 667 */ 668 pp = buf; 669 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 670 __encode_table_record_to_buf(control, &record[i], pp); 671 672 /* update bad channel bitmap */ 673 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 674 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 675 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 676 con->update_channel_flag = true; 677 } 678 } 679 680 /* a, first record index to write into. 681 * b, last record index to write into. 682 * a = first index to read (fri) + number of records in the table, 683 * b = a + @num - 1. 684 * Let N = control->ras_max_num_record_count, then we have, 685 * case 0: 0 <= a <= b < N, 686 * just append @num records starting at a; 687 * case 1: 0 <= a < N <= b, 688 * append (N - a) records starting at a, and 689 * append the remainder, b % N + 1, starting at 0. 690 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 691 * case 2a: 0 <= a <= b < N 692 * append num records starting at a; and fix fri if b overwrote it, 693 * and since a <= b, if b overwrote it then a must've also, 694 * and if b didn't overwrite it, then a didn't also. 695 * case 2b: 0 <= b < a < N 696 * write num records starting at a, which wraps around 0=N 697 * and overwrite fri unconditionally. Now from case 2a, 698 * this means that b eclipsed fri to overwrite it and wrap 699 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 700 * set fri = b + 1 (mod N). 701 * Now, since fri is updated in every case, except the trivial case 0, 702 * the number of records present in the table after writing, is, 703 * num_recs - 1 = b - fri (mod N), and we take the positive value, 704 * by adding an arbitrary multiple of N before taking the modulo N 705 * as shown below. 706 */ 707 a = control->ras_fri + control->ras_num_recs; 708 b = a + num - 1; 709 if (b < control->ras_max_record_count) { 710 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 711 } else if (a < control->ras_max_record_count) { 712 u32 g0, g1; 713 714 g0 = control->ras_max_record_count - a; 715 g1 = b % control->ras_max_record_count + 1; 716 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 717 if (res) 718 goto Out; 719 res = __amdgpu_ras_eeprom_write(control, 720 buf + g0 * RAS_TABLE_RECORD_SIZE, 721 0, g1); 722 if (res) 723 goto Out; 724 if (g1 > control->ras_fri) 725 control->ras_fri = g1 % control->ras_max_record_count; 726 } else { 727 a %= control->ras_max_record_count; 728 b %= control->ras_max_record_count; 729 730 if (a <= b) { 731 /* Note that, b - a + 1 = num. */ 732 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 733 if (res) 734 goto Out; 735 if (b >= control->ras_fri) 736 control->ras_fri = (b + 1) % control->ras_max_record_count; 737 } else { 738 u32 g0, g1; 739 740 /* b < a, which means, we write from 741 * a to the end of the table, and from 742 * the start of the table to b. 743 */ 744 g0 = control->ras_max_record_count - a; 745 g1 = b + 1; 746 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 747 if (res) 748 goto Out; 749 res = __amdgpu_ras_eeprom_write(control, 750 buf + g0 * RAS_TABLE_RECORD_SIZE, 751 0, g1); 752 if (res) 753 goto Out; 754 control->ras_fri = g1 % control->ras_max_record_count; 755 } 756 } 757 control->ras_num_recs = 1 + (control->ras_max_record_count + b 758 - control->ras_fri) 759 % control->ras_max_record_count; 760 761 /*old asics only save pa to eeprom like before*/ 762 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) 763 control->ras_num_pa_recs += num; 764 else 765 control->ras_num_mca_recs += num; 766 767 control->ras_num_bad_pages = con->bad_page_num; 768 Out: 769 kfree(buf); 770 return res; 771 } 772 773 static int 774 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 775 { 776 struct amdgpu_device *adev = to_amdgpu_device(control); 777 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 778 u8 *buf, *pp, csum; 779 u32 buf_size; 780 int res; 781 782 /* Modify the header if it exceeds. 783 */ 784 if (amdgpu_bad_page_threshold != 0 && 785 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 786 dev_warn(adev->dev, 787 "Saved bad pages %d reaches threshold value %d\n", 788 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 789 790 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev) && 791 amdgpu_cper_generate_bp_threshold_record(adev)) 792 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 793 794 if ((amdgpu_bad_page_threshold != -1) && 795 (amdgpu_bad_page_threshold != -2)) { 796 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 797 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 798 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 799 control->tbl_rai.health_percent = 0; 800 } 801 ras->is_rma = true; 802 } 803 804 /* ignore the -ENOTSUPP return value */ 805 amdgpu_dpm_send_rma_reason(adev); 806 } 807 808 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 809 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 810 RAS_TABLE_V2_1_INFO_SIZE + 811 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 812 else 813 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 814 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 815 control->tbl_hdr.checksum = 0; 816 817 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 818 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 819 if (!buf) { 820 dev_err(adev->dev, 821 "allocating memory for table of size %d bytes failed\n", 822 control->tbl_hdr.tbl_size); 823 res = -ENOMEM; 824 goto Out; 825 } 826 827 down_read(&adev->reset_domain->sem); 828 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 829 control->i2c_address + 830 control->ras_record_offset, 831 buf, buf_size); 832 up_read(&adev->reset_domain->sem); 833 if (res < 0) { 834 dev_err(adev->dev, "EEPROM failed reading records:%d\n", res); 835 goto Out; 836 } else if (res < buf_size) { 837 dev_err(adev->dev, "EEPROM read %d out of %d bytes\n", res, 838 buf_size); 839 res = -EIO; 840 goto Out; 841 } 842 843 /** 844 * bad page records have been stored in eeprom, 845 * now calculate gpu health percent 846 */ 847 if (amdgpu_bad_page_threshold != 0 && 848 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 849 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) 850 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 851 control->ras_num_bad_pages) * 100) / 852 ras->bad_page_cnt_threshold; 853 854 /* Recalc the checksum. 855 */ 856 csum = 0; 857 for (pp = buf; pp < buf + buf_size; pp++) 858 csum += *pp; 859 860 csum += __calc_hdr_byte_sum(control); 861 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 862 csum += __calc_ras_info_byte_sum(control); 863 /* avoid sign extension when assigning to "checksum" */ 864 csum = -csum; 865 control->tbl_hdr.checksum = csum; 866 res = __write_table_header(control); 867 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 868 res = __write_table_ras_info(control); 869 Out: 870 kfree(buf); 871 return res; 872 } 873 874 int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) 875 { 876 struct amdgpu_device *adev = to_amdgpu_device(control); 877 878 if (!amdgpu_ras_smu_eeprom_supported(adev)) 879 return 0; 880 881 control->ras_num_recs_old = control->ras_num_recs; 882 return amdgpu_ras_smu_get_badpage_count(adev, 883 &(control->ras_num_recs), 12); 884 } 885 886 /** 887 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 888 * @control: pointer to control structure 889 * @record: array of records to append 890 * @num: number of records in @record array 891 * 892 * Append @num records to the table, calculate the checksum and write 893 * the table back to EEPROM. The maximum number of records that 894 * can be appended is between 1 and control->ras_max_record_count, 895 * regardless of how many records are already stored in the table. 896 * 897 * Return 0 on success or if EEPROM is not supported, -errno on error. 898 */ 899 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 900 struct eeprom_table_record *record, 901 const u32 num) 902 { 903 struct amdgpu_device *adev = to_amdgpu_device(control); 904 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 905 int res, i; 906 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 907 908 if (!__is_ras_eeprom_supported(adev) || !con) 909 return 0; 910 911 if (amdgpu_ras_smu_eeprom_supported(adev)) { 912 control->ras_num_bad_pages = con->bad_page_num; 913 return 0; 914 } 915 916 if (num == 0) { 917 dev_err(adev->dev, "will not append 0 records\n"); 918 return -EINVAL; 919 } else if (num > control->ras_max_record_count) { 920 dev_err(adev->dev, 921 "cannot append %d records than the size of table %d\n", 922 num, control->ras_max_record_count); 923 return -EINVAL; 924 } 925 926 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 927 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 928 929 /* set the new channel index flag */ 930 for (i = 0; i < num; i++) 931 record[i].retired_page |= (nps << UMC_NPS_SHIFT); 932 933 mutex_lock(&control->ras_tbl_mutex); 934 935 res = amdgpu_ras_eeprom_append_table(control, record, num); 936 if (!res) 937 res = amdgpu_ras_eeprom_update_header(control); 938 if (!res) 939 amdgpu_ras_debugfs_set_ret_size(control); 940 941 mutex_unlock(&control->ras_tbl_mutex); 942 943 /* clear channel index flag, the flag is only saved on eeprom */ 944 for (i = 0; i < num; i++) 945 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT); 946 947 return res; 948 } 949 950 /** 951 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 952 * @control: pointer to control structure 953 * @buf: pointer to buffer to read into 954 * @fri: first record index, start reading at this index, absolute index 955 * @num: number of records to read 956 * 957 * The caller must hold the table mutex in @control. 958 * Return 0 on success, -errno otherwise. 959 */ 960 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 961 u8 *buf, const u32 fri, const u32 num) 962 { 963 struct amdgpu_device *adev = to_amdgpu_device(control); 964 u32 buf_size; 965 int res; 966 967 /* i2c may be unstable in gpu reset */ 968 down_read(&adev->reset_domain->sem); 969 buf_size = num * RAS_TABLE_RECORD_SIZE; 970 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 971 control->i2c_address + 972 RAS_INDEX_TO_OFFSET(control, fri), 973 buf, buf_size); 974 up_read(&adev->reset_domain->sem); 975 if (res < 0) { 976 dev_err(adev->dev, "Reading %d EEPROM table records error:%d", 977 num, res); 978 } else if (res < buf_size) { 979 /* Short read, return error. 980 */ 981 dev_err(adev->dev, "Read %d records out of %d", 982 res / RAS_TABLE_RECORD_SIZE, num); 983 res = -EIO; 984 } else { 985 res = 0; 986 } 987 988 return res; 989 } 990 991 int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, 992 struct eeprom_table_record *record, u32 rec_idx, 993 const u32 num) 994 { 995 struct amdgpu_device *adev = to_amdgpu_device(control); 996 uint64_t ts, end_idx; 997 int i, ret; 998 u64 mca, ipid; 999 1000 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1001 return 0; 1002 1003 if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) 1004 return -EOPNOTSUPP; 1005 1006 end_idx = rec_idx + num; 1007 for (i = rec_idx; i < end_idx; i++) { 1008 ret = amdgpu_ras_smu_get_badpage_mca_addr(adev, i, &mca); 1009 if (ret) 1010 return ret; 1011 1012 ret = amdgpu_ras_smu_get_badpage_ipid(adev, i, &ipid); 1013 if (ret) 1014 return ret; 1015 1016 ret = amdgpu_ras_smu_get_timestamp(adev, i, &ts); 1017 if (ret) 1018 return ret; 1019 1020 record[i - rec_idx].address = mca; 1021 /* retired_page (pa) is unused now */ 1022 record[i - rec_idx].retired_page = 0x1ULL; 1023 record[i - rec_idx].ts = ts; 1024 record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 1025 record[i - rec_idx].cu = 0; 1026 1027 adev->umc.ras->mca_ipid_parse(adev, ipid, NULL, 1028 (uint32_t *)&(record[i - rec_idx].mem_channel), 1029 (uint32_t *)&(record[i - rec_idx].mcumc_id), NULL); 1030 } 1031 1032 return 0; 1033 } 1034 1035 /** 1036 * amdgpu_ras_eeprom_read -- read EEPROM 1037 * @control: pointer to control structure 1038 * @record: array of records to read into 1039 * @num: number of records in @record 1040 * 1041 * Reads num records from the RAS table in EEPROM and 1042 * writes the data into @record array. 1043 * 1044 * Returns 0 on success, -errno on error. 1045 */ 1046 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 1047 struct eeprom_table_record *record, 1048 const u32 num) 1049 { 1050 struct amdgpu_device *adev = to_amdgpu_device(control); 1051 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1052 int i, res; 1053 u8 *buf, *pp; 1054 u32 g0, g1; 1055 1056 if (amdgpu_ras_smu_eeprom_supported(adev)) 1057 return amdgpu_ras_eeprom_read_idx(control, record, 0, num); 1058 1059 if (!__is_ras_eeprom_supported(adev)) 1060 return 0; 1061 1062 if (num == 0) { 1063 dev_err(adev->dev, "will not read 0 records\n"); 1064 return -EINVAL; 1065 } else if (num > control->ras_num_recs) { 1066 dev_err(adev->dev, "too many records to read:%d available:%d\n", 1067 num, control->ras_num_recs); 1068 return -EINVAL; 1069 } 1070 1071 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 1072 if (!buf) 1073 return -ENOMEM; 1074 1075 /* Determine how many records to read, from the first record 1076 * index, fri, to the end of the table, and from the beginning 1077 * of the table, such that the total number of records is 1078 * @num, and we handle wrap around when fri > 0 and 1079 * fri + num > RAS_MAX_RECORD_COUNT. 1080 * 1081 * First we compute the index of the last element 1082 * which would be fetched from each region, 1083 * g0 is in [fri, fri + num - 1], and 1084 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 1085 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 1086 * the last element to fetch, we set g0 to _the number_ 1087 * of elements to fetch, @num, since we know that the last 1088 * indexed to be fetched does not exceed the table. 1089 * 1090 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 1091 * we set g0 to the number of elements to read 1092 * until the end of the table, and g1 to the number of 1093 * elements to read from the beginning of the table. 1094 */ 1095 g0 = control->ras_fri + num - 1; 1096 g1 = g0 % control->ras_max_record_count; 1097 if (g0 < control->ras_max_record_count) { 1098 g0 = num; 1099 g1 = 0; 1100 } else { 1101 g0 = control->ras_max_record_count - control->ras_fri; 1102 g1 += 1; 1103 } 1104 1105 mutex_lock(&control->ras_tbl_mutex); 1106 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 1107 if (res) 1108 goto Out; 1109 if (g1) { 1110 res = __amdgpu_ras_eeprom_read(control, 1111 buf + g0 * RAS_TABLE_RECORD_SIZE, 1112 0, g1); 1113 if (res) 1114 goto Out; 1115 } 1116 1117 res = 0; 1118 1119 /* Read up everything? Then transform. 1120 */ 1121 pp = buf; 1122 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 1123 __decode_table_record_from_buf(control, &record[i], pp); 1124 1125 /* update bad channel bitmap */ 1126 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1127 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1128 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1129 con->update_channel_flag = true; 1130 } 1131 } 1132 Out: 1133 kfree(buf); 1134 mutex_unlock(&control->ras_tbl_mutex); 1135 1136 return res; 1137 } 1138 1139 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1140 { 1141 /* get available eeprom table version first before eeprom table init */ 1142 amdgpu_ras_set_eeprom_table_version(control); 1143 1144 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1145 return RAS_MAX_RECORD_COUNT_V2_1; 1146 else 1147 return RAS_MAX_RECORD_COUNT; 1148 } 1149 1150 static ssize_t 1151 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1152 size_t size, loff_t *pos) 1153 { 1154 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1155 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1156 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1157 u8 data[50]; 1158 int res; 1159 1160 if (!size) 1161 return size; 1162 1163 if (!ras || !control) { 1164 res = snprintf(data, sizeof(data), "Not supported\n"); 1165 } else { 1166 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1167 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1168 } 1169 1170 if (*pos >= res) 1171 return 0; 1172 1173 res -= *pos; 1174 res = min_t(size_t, res, size); 1175 1176 if (copy_to_user(buf, &data[*pos], res)) 1177 return -EFAULT; 1178 1179 *pos += res; 1180 1181 return res; 1182 } 1183 1184 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1185 .owner = THIS_MODULE, 1186 .read = amdgpu_ras_debugfs_eeprom_size_read, 1187 .write = NULL, 1188 .llseek = default_llseek, 1189 }; 1190 1191 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1192 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1193 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1194 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1195 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1196 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1197 1198 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1199 "ignore", 1200 "re", 1201 "ue", 1202 }; 1203 1204 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1205 { 1206 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1207 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1208 } 1209 1210 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1211 { 1212 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1213 eeprom_control); 1214 struct dentry *de = ras->de_ras_eeprom_table; 1215 1216 if (de) 1217 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1218 } 1219 1220 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1221 size_t size, loff_t *pos) 1222 { 1223 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1224 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1225 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1226 const size_t orig_size = size; 1227 int res = -EFAULT; 1228 size_t data_len; 1229 1230 /* pmfw manages eeprom data by itself */ 1231 if (amdgpu_ras_smu_eeprom_supported(adev)) 1232 return 0; 1233 1234 mutex_lock(&control->ras_tbl_mutex); 1235 1236 /* We want *pos - data_len > 0, which means there's 1237 * bytes to be printed from data. 1238 */ 1239 data_len = strlen(tbl_hdr_str); 1240 if (*pos < data_len) { 1241 data_len -= *pos; 1242 data_len = min_t(size_t, data_len, size); 1243 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1244 goto Out; 1245 buf += data_len; 1246 size -= data_len; 1247 *pos += data_len; 1248 } 1249 1250 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1251 if (*pos < data_len && size > 0) { 1252 u8 data[tbl_hdr_fmt_size + 1]; 1253 loff_t lpos; 1254 1255 snprintf(data, sizeof(data), tbl_hdr_fmt, 1256 control->tbl_hdr.header, 1257 control->tbl_hdr.version, 1258 control->tbl_hdr.first_rec_offset, 1259 control->tbl_hdr.tbl_size, 1260 control->tbl_hdr.checksum); 1261 1262 data_len -= *pos; 1263 data_len = min_t(size_t, data_len, size); 1264 lpos = *pos - strlen(tbl_hdr_str); 1265 if (copy_to_user(buf, &data[lpos], data_len)) 1266 goto Out; 1267 buf += data_len; 1268 size -= data_len; 1269 *pos += data_len; 1270 } 1271 1272 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1273 if (*pos < data_len && size > 0) { 1274 loff_t lpos; 1275 1276 data_len -= *pos; 1277 data_len = min_t(size_t, data_len, size); 1278 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1279 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1280 goto Out; 1281 buf += data_len; 1282 size -= data_len; 1283 *pos += data_len; 1284 } 1285 1286 data_len = amdgpu_ras_debugfs_table_size(control); 1287 if (*pos < data_len && size > 0) { 1288 u8 dare[RAS_TABLE_RECORD_SIZE]; 1289 u8 data[rec_hdr_fmt_size + 1]; 1290 struct eeprom_table_record record; 1291 int s, r; 1292 1293 /* Find the starting record index 1294 */ 1295 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1296 strlen(rec_hdr_str); 1297 s = s / rec_hdr_fmt_size; 1298 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1299 strlen(rec_hdr_str); 1300 r = r % rec_hdr_fmt_size; 1301 1302 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1303 u32 ai = RAS_RI_TO_AI(control, s); 1304 /* Read a single record 1305 */ 1306 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1307 if (res) 1308 goto Out; 1309 __decode_table_record_from_buf(control, &record, dare); 1310 snprintf(data, sizeof(data), rec_hdr_fmt, 1311 s, 1312 RAS_INDEX_TO_OFFSET(control, ai), 1313 record_err_type_str[record.err_type], 1314 record.bank, 1315 record.ts, 1316 record.offset, 1317 record.mem_channel, 1318 record.mcumc_id, 1319 record.retired_page); 1320 1321 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1322 if (copy_to_user(buf, &data[r], data_len)) { 1323 res = -EFAULT; 1324 goto Out; 1325 } 1326 buf += data_len; 1327 size -= data_len; 1328 *pos += data_len; 1329 r = 0; 1330 } 1331 } 1332 res = 0; 1333 Out: 1334 mutex_unlock(&control->ras_tbl_mutex); 1335 return res < 0 ? res : orig_size - size; 1336 } 1337 1338 static ssize_t 1339 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1340 size_t size, loff_t *pos) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1343 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1344 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1345 u8 data[81]; 1346 int res; 1347 1348 if (!size) 1349 return size; 1350 1351 if (!ras || !control) { 1352 res = snprintf(data, sizeof(data), "Not supported\n"); 1353 if (*pos >= res) 1354 return 0; 1355 1356 res -= *pos; 1357 res = min_t(size_t, res, size); 1358 1359 if (copy_to_user(buf, &data[*pos], res)) 1360 return -EFAULT; 1361 1362 *pos += res; 1363 1364 return res; 1365 } else { 1366 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1367 } 1368 } 1369 1370 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1371 .owner = THIS_MODULE, 1372 .read = amdgpu_ras_debugfs_eeprom_table_read, 1373 .write = NULL, 1374 .llseek = default_llseek, 1375 }; 1376 1377 /** 1378 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1379 * @control: pointer to control structure 1380 * 1381 * Check the checksum of the stored in EEPROM RAS table. 1382 * 1383 * Return 0 if the checksum is correct, 1384 * positive if it is not correct, and 1385 * -errno on I/O error. 1386 */ 1387 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1388 { 1389 struct amdgpu_device *adev = to_amdgpu_device(control); 1390 int buf_size, res; 1391 u8 csum, *buf, *pp; 1392 1393 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1394 buf_size = RAS_TABLE_HEADER_SIZE + 1395 RAS_TABLE_V2_1_INFO_SIZE + 1396 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1397 else 1398 buf_size = RAS_TABLE_HEADER_SIZE + 1399 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1400 1401 buf = kzalloc(buf_size, GFP_KERNEL); 1402 if (!buf) { 1403 dev_err(adev->dev, 1404 "Out of memory checking RAS table checksum.\n"); 1405 return -ENOMEM; 1406 } 1407 1408 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1409 control->i2c_address + 1410 control->ras_header_offset, 1411 buf, buf_size); 1412 if (res < buf_size) { 1413 dev_err(adev->dev, "Partial read for checksum, res:%d\n", res); 1414 /* On partial reads, return -EIO. 1415 */ 1416 if (res >= 0) 1417 res = -EIO; 1418 goto Out; 1419 } 1420 1421 csum = 0; 1422 for (pp = buf; pp < buf + buf_size; pp++) 1423 csum += *pp; 1424 Out: 1425 kfree(buf); 1426 return res < 0 ? res : csum; 1427 } 1428 1429 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1430 { 1431 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1432 struct amdgpu_device *adev = to_amdgpu_device(control); 1433 unsigned char *buf; 1434 int res; 1435 1436 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1437 if (!buf) { 1438 dev_err(adev->dev, 1439 "Failed to alloc buf to read EEPROM table ras info\n"); 1440 return -ENOMEM; 1441 } 1442 1443 /** 1444 * EEPROM table V2_1 supports ras info, 1445 * read EEPROM table ras info 1446 */ 1447 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1448 control->i2c_address + control->ras_info_offset, 1449 buf, RAS_TABLE_V2_1_INFO_SIZE); 1450 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1451 dev_err(adev->dev, 1452 "Failed to read EEPROM table ras info, res:%d", res); 1453 res = res >= 0 ? -EIO : res; 1454 goto Out; 1455 } 1456 1457 __decode_table_ras_info_from_buf(rai, buf); 1458 1459 Out: 1460 kfree(buf); 1461 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1462 } 1463 1464 static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1465 { 1466 struct amdgpu_device *adev = to_amdgpu_device(control); 1467 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1468 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1469 uint64_t local_time; 1470 int res; 1471 1472 ras->is_rma = false; 1473 1474 if (!__is_ras_eeprom_supported(adev)) 1475 return 0; 1476 mutex_init(&control->ras_tbl_mutex); 1477 1478 res = amdgpu_ras_smu_get_table_version(adev, &(hdr->version)); 1479 if (res) 1480 return res; 1481 1482 res = amdgpu_ras_smu_get_badpage_count(adev, 1483 &(control->ras_num_recs), 100); 1484 if (res) 1485 return res; 1486 1487 local_time = (uint64_t)ktime_get_real_seconds(); 1488 res = amdgpu_ras_smu_set_timestamp(adev, local_time); 1489 if (res) 1490 return res; 1491 1492 control->ras_max_record_count = 4000; 1493 1494 control->ras_num_mca_recs = 0; 1495 control->ras_num_pa_recs = 0; 1496 1497 return 0; 1498 } 1499 1500 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1501 { 1502 struct amdgpu_device *adev = to_amdgpu_device(control); 1503 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1504 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1505 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1506 int res; 1507 1508 if (amdgpu_ras_smu_eeprom_supported(adev)) 1509 return amdgpu_ras_smu_eeprom_init(control); 1510 1511 ras->is_rma = false; 1512 1513 if (!__is_ras_eeprom_supported(adev)) 1514 return 0; 1515 1516 /* Verify i2c adapter is initialized */ 1517 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1518 return -ENOENT; 1519 1520 if (!__get_eeprom_i2c_addr(adev, control)) 1521 return -EINVAL; 1522 1523 control->ras_header_offset = RAS_HDR_START; 1524 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1525 mutex_init(&control->ras_tbl_mutex); 1526 1527 /* Read the table header from EEPROM address */ 1528 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1529 control->i2c_address + control->ras_header_offset, 1530 buf, RAS_TABLE_HEADER_SIZE); 1531 if (res < RAS_TABLE_HEADER_SIZE) { 1532 dev_err(adev->dev, "Failed to read EEPROM table header, res:%d", 1533 res); 1534 return res >= 0 ? -EIO : res; 1535 } 1536 1537 __decode_table_header_from_buf(hdr, buf); 1538 1539 if (hdr->header != RAS_TABLE_HDR_VAL && 1540 hdr->header != RAS_TABLE_HDR_BAD) { 1541 dev_info(adev->dev, "Creating a new EEPROM table"); 1542 return amdgpu_ras_eeprom_reset_table(control); 1543 } 1544 1545 switch (hdr->version) { 1546 case RAS_TABLE_VER_V2_1: 1547 case RAS_TABLE_VER_V3: 1548 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1549 control->ras_record_offset = RAS_RECORD_START_V2_1; 1550 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1551 break; 1552 case RAS_TABLE_VER_V1: 1553 control->ras_num_recs = RAS_NUM_RECS(hdr); 1554 control->ras_record_offset = RAS_RECORD_START; 1555 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1556 break; 1557 default: 1558 dev_err(adev->dev, 1559 "RAS header invalid, unsupported version: %u", 1560 hdr->version); 1561 return -EINVAL; 1562 } 1563 1564 if (control->ras_num_recs > control->ras_max_record_count) { 1565 dev_err(adev->dev, 1566 "RAS header invalid, records in header: %u max allowed :%u", 1567 control->ras_num_recs, control->ras_max_record_count); 1568 return -EINVAL; 1569 } 1570 1571 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1572 control->ras_num_mca_recs = 0; 1573 control->ras_num_pa_recs = 0; 1574 return 0; 1575 } 1576 1577 static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1578 { 1579 struct amdgpu_device *adev = to_amdgpu_device(control); 1580 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1581 1582 if (!__is_ras_eeprom_supported(adev)) 1583 return 0; 1584 1585 control->ras_num_bad_pages = ras->bad_page_num; 1586 1587 if ((ras->bad_page_cnt_threshold < control->ras_num_bad_pages) && 1588 amdgpu_bad_page_threshold != 0) { 1589 dev_warn(adev->dev, 1590 "RAS records:%d exceed threshold:%d\n", 1591 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1592 if ((amdgpu_bad_page_threshold == -1) || 1593 (amdgpu_bad_page_threshold == -2)) { 1594 dev_warn(adev->dev, 1595 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1596 } else { 1597 ras->is_rma = true; 1598 dev_warn(adev->dev, 1599 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1600 } 1601 1602 return 0; 1603 } 1604 1605 dev_dbg(adev->dev, 1606 "Found existing EEPROM table with %d records", 1607 control->ras_num_bad_pages); 1608 1609 /* Warn if we are at 90% of the threshold or above 1610 */ 1611 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1612 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1613 control->ras_num_bad_pages, 1614 ras->bad_page_cnt_threshold); 1615 return 0; 1616 } 1617 1618 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1619 { 1620 struct amdgpu_device *adev = to_amdgpu_device(control); 1621 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1622 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1623 int res = 0; 1624 1625 if (amdgpu_ras_smu_eeprom_supported(adev)) 1626 return amdgpu_ras_smu_eeprom_check(control); 1627 1628 if (!__is_ras_eeprom_supported(adev)) 1629 return 0; 1630 1631 /* Verify i2c adapter is initialized */ 1632 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1633 return -ENOENT; 1634 1635 if (!__get_eeprom_i2c_addr(adev, control)) 1636 return -EINVAL; 1637 1638 control->ras_num_bad_pages = ras->bad_page_num; 1639 1640 if (hdr->header == RAS_TABLE_HDR_VAL) { 1641 dev_dbg(adev->dev, 1642 "Found existing EEPROM table with %d records", 1643 control->ras_num_bad_pages); 1644 1645 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1646 res = __read_table_ras_info(control); 1647 if (res) 1648 return res; 1649 } 1650 1651 res = __verify_ras_table_checksum(control); 1652 if (res) 1653 dev_err(adev->dev, 1654 "RAS table incorrect checksum or error:%d\n", 1655 res); 1656 1657 /* Warn if we are at 90% of the threshold or above 1658 */ 1659 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1660 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1661 control->ras_num_bad_pages, 1662 ras->bad_page_cnt_threshold); 1663 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1664 amdgpu_bad_page_threshold != 0) { 1665 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1666 res = __read_table_ras_info(control); 1667 if (res) 1668 return res; 1669 } 1670 1671 res = __verify_ras_table_checksum(control); 1672 if (res) { 1673 dev_err(adev->dev, 1674 "RAS Table incorrect checksum or error:%d\n", 1675 res); 1676 return -EINVAL; 1677 } 1678 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { 1679 /* This means that, the threshold was increased since 1680 * the last time the system was booted, and now, 1681 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1682 * so that at least one more record can be saved, 1683 * before the page count threshold is reached. 1684 */ 1685 dev_info(adev->dev, 1686 "records:%d threshold:%d, resetting " 1687 "RAS table header signature", 1688 control->ras_num_bad_pages, 1689 ras->bad_page_cnt_threshold); 1690 res = amdgpu_ras_eeprom_correct_header_tag(control, 1691 RAS_TABLE_HDR_VAL); 1692 } else { 1693 dev_warn(adev->dev, 1694 "RAS records:%d exceed threshold:%d\n", 1695 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1696 if ((amdgpu_bad_page_threshold == -1) || 1697 (amdgpu_bad_page_threshold == -2)) { 1698 res = 0; 1699 dev_warn(adev->dev, 1700 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1701 } else { 1702 ras->is_rma = true; 1703 dev_warn(adev->dev, 1704 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1705 } 1706 } 1707 } 1708 1709 return res < 0 ? res : 0; 1710 } 1711 1712 void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev) 1713 { 1714 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1715 struct amdgpu_ras_eeprom_control *control; 1716 int res; 1717 1718 if (!__is_ras_eeprom_supported(adev) || !ras || 1719 amdgpu_ras_smu_eeprom_supported(adev)) 1720 return; 1721 control = &ras->eeprom_control; 1722 if (!control->is_eeprom_valid) 1723 return; 1724 res = __verify_ras_table_checksum(control); 1725 if (res) { 1726 dev_warn(adev->dev, 1727 "RAS table incorrect checksum or error:%d, try to recover\n", 1728 res); 1729 if (!amdgpu_ras_eeprom_reset_table(control)) 1730 if (!amdgpu_ras_save_bad_pages(adev, NULL)) 1731 if (!__verify_ras_table_checksum(control)) { 1732 dev_info(adev->dev, "RAS table recovery succeed\n"); 1733 return; 1734 } 1735 dev_err(adev->dev, "RAS table recovery failed\n"); 1736 control->is_eeprom_valid = false; 1737 } 1738 return; 1739 } 1740 1741 static const struct ras_smu_drv *amdgpu_ras_get_smu_ras_drv(struct amdgpu_device *adev) 1742 { 1743 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1744 1745 if (!ras) 1746 return NULL; 1747 1748 return ras->ras_smu_drv; 1749 } 1750 1751 static uint64_t amdgpu_ras_smu_get_feature_flags(struct amdgpu_device *adev) 1752 { 1753 const struct ras_smu_drv *ras_smu_drv = amdgpu_ras_get_smu_ras_drv(adev); 1754 uint64_t flags = 0ULL; 1755 1756 if (!ras_smu_drv) 1757 goto out; 1758 1759 if (ras_smu_drv->ras_smu_feature_flags) 1760 ras_smu_drv->ras_smu_feature_flags(adev, &flags); 1761 1762 out: 1763 return flags; 1764 } 1765 1766 bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev) 1767 { 1768 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1769 uint64_t flags = 0ULL; 1770 1771 if (!__is_ras_eeprom_supported(adev) || !smu_ras_drv) 1772 return false; 1773 1774 if (!smu_ras_drv->smu_eeprom_funcs) 1775 return false; 1776 1777 flags = amdgpu_ras_smu_get_feature_flags(adev); 1778 1779 return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM); 1780 } 1781 1782 int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, 1783 uint32_t *table_version) 1784 { 1785 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1786 1787 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1788 return -EOPNOTSUPP; 1789 1790 if (smu_ras_drv->smu_eeprom_funcs->get_ras_table_version) 1791 return smu_ras_drv->smu_eeprom_funcs->get_ras_table_version(adev, 1792 table_version); 1793 return -EOPNOTSUPP; 1794 } 1795 1796 int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, 1797 uint32_t *count, uint32_t timeout) 1798 { 1799 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1800 1801 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1802 return -EOPNOTSUPP; 1803 1804 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_count) 1805 return smu_ras_drv->smu_eeprom_funcs->get_badpage_count(adev, 1806 count, timeout); 1807 return -EOPNOTSUPP; 1808 } 1809 1810 int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, 1811 uint16_t index, uint64_t *mca_addr) 1812 { 1813 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1814 1815 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1816 return -EOPNOTSUPP; 1817 1818 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr) 1819 return smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr(adev, 1820 index, mca_addr); 1821 return -EOPNOTSUPP; 1822 } 1823 1824 int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, 1825 uint64_t timestamp) 1826 { 1827 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1828 1829 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1830 return -EOPNOTSUPP; 1831 1832 if (smu_ras_drv->smu_eeprom_funcs->set_timestamp) 1833 return smu_ras_drv->smu_eeprom_funcs->set_timestamp(adev, 1834 timestamp); 1835 return -EOPNOTSUPP; 1836 } 1837 1838 int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, 1839 uint16_t index, uint64_t *timestamp) 1840 { 1841 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1842 1843 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1844 return -EOPNOTSUPP; 1845 1846 if (smu_ras_drv->smu_eeprom_funcs->get_timestamp) 1847 return smu_ras_drv->smu_eeprom_funcs->get_timestamp(adev, 1848 index, timestamp); 1849 return -EOPNOTSUPP; 1850 } 1851 1852 int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, 1853 uint16_t index, uint64_t *ipid) 1854 { 1855 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1856 1857 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1858 return -EOPNOTSUPP; 1859 1860 if (smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid) 1861 return smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid(adev, 1862 index, ipid); 1863 return -EOPNOTSUPP; 1864 } 1865 1866 int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, 1867 uint32_t *result) 1868 { 1869 const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1870 1871 if (!amdgpu_ras_smu_eeprom_supported(adev)) 1872 return -EOPNOTSUPP; 1873 1874 if (smu_ras_drv->smu_eeprom_funcs->erase_ras_table) 1875 return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev, 1876 result); 1877 return -EOPNOTSUPP; 1878 } 1879