1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 10): 162 return true; 163 case IP_VERSION(13, 0, 6): 164 case IP_VERSION(13, 0, 14): 165 return (adev->gmc.is_app_apu) ? false : true; 166 default: 167 return false; 168 } 169 } 170 171 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 172 struct amdgpu_ras_eeprom_control *control) 173 { 174 struct atom_context *atom_ctx = adev->mode_info.atom_context; 175 u8 i2c_addr; 176 177 if (!control) 178 return false; 179 180 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 181 /* The address given by VBIOS is an 8-bit, wire-format 182 * address, i.e. the most significant byte. 183 * 184 * Normalize it to a 19-bit EEPROM address. Remove the 185 * device type identifier and make it a 7-bit address; 186 * then make it a 19-bit EEPROM address. See top of 187 * amdgpu_eeprom.c. 188 */ 189 i2c_addr = (i2c_addr & 0x0F) >> 1; 190 control->i2c_address = ((u32) i2c_addr) << 16; 191 192 return true; 193 } 194 195 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 196 case IP_VERSION(11, 0, 2): 197 /* VEGA20 and ARCTURUS */ 198 if (adev->asic_type == CHIP_VEGA20) 199 control->i2c_address = EEPROM_I2C_MADDR_0; 200 else if (strnstr(atom_ctx->vbios_pn, 201 "D342", 202 sizeof(atom_ctx->vbios_pn))) 203 control->i2c_address = EEPROM_I2C_MADDR_0; 204 else 205 control->i2c_address = EEPROM_I2C_MADDR_4; 206 return true; 207 case IP_VERSION(11, 0, 7): 208 control->i2c_address = EEPROM_I2C_MADDR_0; 209 return true; 210 case IP_VERSION(13, 0, 2): 211 if (strnstr(atom_ctx->vbios_pn, "D673", 212 sizeof(atom_ctx->vbios_pn))) 213 control->i2c_address = EEPROM_I2C_MADDR_4; 214 else 215 control->i2c_address = EEPROM_I2C_MADDR_0; 216 return true; 217 case IP_VERSION(13, 0, 0): 218 if (strnstr(atom_ctx->vbios_pn, "D707", 219 sizeof(atom_ctx->vbios_pn))) 220 control->i2c_address = EEPROM_I2C_MADDR_0; 221 else 222 control->i2c_address = EEPROM_I2C_MADDR_4; 223 return true; 224 case IP_VERSION(13, 0, 6): 225 case IP_VERSION(13, 0, 10): 226 case IP_VERSION(13, 0, 14): 227 control->i2c_address = EEPROM_I2C_MADDR_4; 228 return true; 229 default: 230 return false; 231 } 232 } 233 234 static void 235 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 236 unsigned char *buf) 237 { 238 u32 *pp = (uint32_t *)buf; 239 240 pp[0] = cpu_to_le32(hdr->header); 241 pp[1] = cpu_to_le32(hdr->version); 242 pp[2] = cpu_to_le32(hdr->first_rec_offset); 243 pp[3] = cpu_to_le32(hdr->tbl_size); 244 pp[4] = cpu_to_le32(hdr->checksum); 245 } 246 247 static void 248 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 249 unsigned char *buf) 250 { 251 u32 *pp = (uint32_t *)buf; 252 253 hdr->header = le32_to_cpu(pp[0]); 254 hdr->version = le32_to_cpu(pp[1]); 255 hdr->first_rec_offset = le32_to_cpu(pp[2]); 256 hdr->tbl_size = le32_to_cpu(pp[3]); 257 hdr->checksum = le32_to_cpu(pp[4]); 258 } 259 260 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 261 { 262 u8 buf[RAS_TABLE_HEADER_SIZE]; 263 struct amdgpu_device *adev = to_amdgpu_device(control); 264 int res; 265 266 memset(buf, 0, sizeof(buf)); 267 __encode_table_header_to_buf(&control->tbl_hdr, buf); 268 269 /* i2c may be unstable in gpu reset */ 270 down_read(&adev->reset_domain->sem); 271 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 272 control->i2c_address + 273 control->ras_header_offset, 274 buf, RAS_TABLE_HEADER_SIZE); 275 up_read(&adev->reset_domain->sem); 276 277 if (res < 0) { 278 DRM_ERROR("Failed to write EEPROM table header:%d", res); 279 } else if (res < RAS_TABLE_HEADER_SIZE) { 280 DRM_ERROR("Short write:%d out of %d\n", 281 res, RAS_TABLE_HEADER_SIZE); 282 res = -EIO; 283 } else { 284 res = 0; 285 } 286 287 return res; 288 } 289 290 static void 291 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 292 unsigned char *buf) 293 { 294 u32 *pp = (uint32_t *)buf; 295 u32 tmp; 296 297 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 298 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 299 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 300 pp[0] = cpu_to_le32(tmp); 301 } 302 303 static void 304 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 305 unsigned char *buf) 306 { 307 u32 *pp = (uint32_t *)buf; 308 u32 tmp; 309 310 tmp = le32_to_cpu(pp[0]); 311 rai->rma_status = tmp & 0xFF; 312 rai->health_percent = (tmp >> 8) & 0xFF; 313 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 314 } 315 316 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 317 { 318 struct amdgpu_device *adev = to_amdgpu_device(control); 319 u8 *buf; 320 int res; 321 322 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 323 if (!buf) { 324 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 325 return -ENOMEM; 326 } 327 328 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 329 330 /* i2c may be unstable in gpu reset */ 331 down_read(&adev->reset_domain->sem); 332 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 333 control->i2c_address + 334 control->ras_info_offset, 335 buf, RAS_TABLE_V2_1_INFO_SIZE); 336 up_read(&adev->reset_domain->sem); 337 338 if (res < 0) { 339 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 340 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 341 DRM_ERROR("Short write:%d out of %d\n", 342 res, RAS_TABLE_V2_1_INFO_SIZE); 343 res = -EIO; 344 } else { 345 res = 0; 346 } 347 348 kfree(buf); 349 350 return res; 351 } 352 353 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 354 { 355 int ii; 356 u8 *pp, csum; 357 size_t sz; 358 359 /* Header checksum, skip checksum field in the calculation */ 360 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 361 pp = (u8 *) &control->tbl_hdr; 362 csum = 0; 363 for (ii = 0; ii < sz; ii++, pp++) 364 csum += *pp; 365 366 return csum; 367 } 368 369 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 370 { 371 int ii; 372 u8 *pp, csum; 373 size_t sz; 374 375 sz = sizeof(control->tbl_rai); 376 pp = (u8 *) &control->tbl_rai; 377 csum = 0; 378 for (ii = 0; ii < sz; ii++, pp++) 379 csum += *pp; 380 381 return csum; 382 } 383 384 static int amdgpu_ras_eeprom_correct_header_tag( 385 struct amdgpu_ras_eeprom_control *control, 386 uint32_t header) 387 { 388 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 389 u8 *hh; 390 int res; 391 u8 csum; 392 393 csum = -hdr->checksum; 394 395 hh = (void *) &hdr->header; 396 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 397 hh = (void *) &header; 398 csum += hh[0] + hh[1] + hh[2] + hh[3]; 399 csum = -csum; 400 mutex_lock(&control->ras_tbl_mutex); 401 hdr->header = header; 402 hdr->checksum = csum; 403 res = __write_table_header(control); 404 mutex_unlock(&control->ras_tbl_mutex); 405 406 return res; 407 } 408 409 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 410 { 411 struct amdgpu_device *adev = to_amdgpu_device(control); 412 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 413 414 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 415 case IP_VERSION(8, 10, 0): 416 case IP_VERSION(12, 0, 0): 417 hdr->version = RAS_TABLE_VER_V2_1; 418 return; 419 default: 420 hdr->version = RAS_TABLE_VER_V1; 421 return; 422 } 423 } 424 425 /** 426 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 427 * @control: pointer to control structure 428 * 429 * Reset the contents of the header of the RAS EEPROM table. 430 * Return 0 on success, -errno on error. 431 */ 432 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 433 { 434 struct amdgpu_device *adev = to_amdgpu_device(control); 435 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 436 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 437 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 438 u8 csum; 439 int res; 440 441 mutex_lock(&control->ras_tbl_mutex); 442 443 hdr->header = RAS_TABLE_HDR_VAL; 444 amdgpu_ras_set_eeprom_table_version(control); 445 446 if (hdr->version == RAS_TABLE_VER_V2_1) { 447 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 448 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 449 RAS_TABLE_V2_1_INFO_SIZE; 450 rai->rma_status = GPU_HEALTH_USABLE; 451 /** 452 * GPU health represented as a percentage. 453 * 0 means worst health, 100 means fully health. 454 */ 455 rai->health_percent = 100; 456 /* ecc_page_threshold = 0 means disable bad page retirement */ 457 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 458 } else { 459 hdr->first_rec_offset = RAS_RECORD_START; 460 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 461 } 462 463 csum = __calc_hdr_byte_sum(control); 464 if (hdr->version == RAS_TABLE_VER_V2_1) 465 csum += __calc_ras_info_byte_sum(control); 466 csum = -csum; 467 hdr->checksum = csum; 468 res = __write_table_header(control); 469 if (!res && hdr->version > RAS_TABLE_VER_V1) 470 res = __write_table_ras_info(control); 471 472 control->ras_num_recs = 0; 473 control->ras_fri = 0; 474 475 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 476 477 control->bad_channel_bitmap = 0; 478 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 479 con->update_channel_flag = false; 480 481 amdgpu_ras_debugfs_set_ret_size(control); 482 483 mutex_unlock(&control->ras_tbl_mutex); 484 485 return res; 486 } 487 488 static void 489 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 490 struct eeprom_table_record *record, 491 unsigned char *buf) 492 { 493 __le64 tmp = 0; 494 int i = 0; 495 496 /* Next are all record fields according to EEPROM page spec in LE foramt */ 497 buf[i++] = record->err_type; 498 499 buf[i++] = record->bank; 500 501 tmp = cpu_to_le64(record->ts); 502 memcpy(buf + i, &tmp, 8); 503 i += 8; 504 505 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 506 memcpy(buf + i, &tmp, 6); 507 i += 6; 508 509 buf[i++] = record->mem_channel; 510 buf[i++] = record->mcumc_id; 511 512 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 513 memcpy(buf + i, &tmp, 6); 514 } 515 516 static void 517 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 518 struct eeprom_table_record *record, 519 unsigned char *buf) 520 { 521 __le64 tmp = 0; 522 int i = 0; 523 524 /* Next are all record fields according to EEPROM page spec in LE foramt */ 525 record->err_type = buf[i++]; 526 527 record->bank = buf[i++]; 528 529 memcpy(&tmp, buf + i, 8); 530 record->ts = le64_to_cpu(tmp); 531 i += 8; 532 533 memcpy(&tmp, buf + i, 6); 534 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 535 i += 6; 536 537 record->mem_channel = buf[i++]; 538 record->mcumc_id = buf[i++]; 539 540 memcpy(&tmp, buf + i, 6); 541 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 542 } 543 544 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 545 { 546 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 547 548 if (!__is_ras_eeprom_supported(adev) || 549 !amdgpu_bad_page_threshold) 550 return false; 551 552 /* skip check eeprom table for VEGA20 Gaming */ 553 if (!con) 554 return false; 555 else 556 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 557 return false; 558 559 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 560 if (amdgpu_bad_page_threshold == -1) { 561 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 562 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold); 563 dev_warn(adev->dev, 564 "But GPU can be operated due to bad_page_threshold = -1.\n"); 565 return false; 566 } else { 567 dev_warn(adev->dev, "This GPU is in BAD status."); 568 dev_warn(adev->dev, "Please retire it or set a larger " 569 "threshold value when reloading driver.\n"); 570 return true; 571 } 572 } 573 574 return false; 575 } 576 577 /** 578 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 579 * @control: pointer to control structure 580 * @buf: pointer to buffer containing data to write 581 * @fri: start writing at this index 582 * @num: number of records to write 583 * 584 * The caller must hold the table mutex in @control. 585 * Return 0 on success, -errno otherwise. 586 */ 587 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 588 u8 *buf, const u32 fri, const u32 num) 589 { 590 struct amdgpu_device *adev = to_amdgpu_device(control); 591 u32 buf_size; 592 int res; 593 594 /* i2c may be unstable in gpu reset */ 595 down_read(&adev->reset_domain->sem); 596 buf_size = num * RAS_TABLE_RECORD_SIZE; 597 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 598 control->i2c_address + 599 RAS_INDEX_TO_OFFSET(control, fri), 600 buf, buf_size); 601 up_read(&adev->reset_domain->sem); 602 if (res < 0) { 603 DRM_ERROR("Writing %d EEPROM table records error:%d", 604 num, res); 605 } else if (res < buf_size) { 606 /* Short write, return error. 607 */ 608 DRM_ERROR("Wrote %d records out of %d", 609 res / RAS_TABLE_RECORD_SIZE, num); 610 res = -EIO; 611 } else { 612 res = 0; 613 } 614 615 return res; 616 } 617 618 static int 619 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 620 struct eeprom_table_record *record, 621 const u32 num) 622 { 623 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 624 u32 a, b, i; 625 u8 *buf, *pp; 626 int res; 627 628 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 629 if (!buf) 630 return -ENOMEM; 631 632 /* Encode all of them in one go. 633 */ 634 pp = buf; 635 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 636 __encode_table_record_to_buf(control, &record[i], pp); 637 638 /* update bad channel bitmap */ 639 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 640 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 641 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 642 con->update_channel_flag = true; 643 } 644 } 645 646 /* a, first record index to write into. 647 * b, last record index to write into. 648 * a = first index to read (fri) + number of records in the table, 649 * b = a + @num - 1. 650 * Let N = control->ras_max_num_record_count, then we have, 651 * case 0: 0 <= a <= b < N, 652 * just append @num records starting at a; 653 * case 1: 0 <= a < N <= b, 654 * append (N - a) records starting at a, and 655 * append the remainder, b % N + 1, starting at 0. 656 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 657 * case 2a: 0 <= a <= b < N 658 * append num records starting at a; and fix fri if b overwrote it, 659 * and since a <= b, if b overwrote it then a must've also, 660 * and if b didn't overwrite it, then a didn't also. 661 * case 2b: 0 <= b < a < N 662 * write num records starting at a, which wraps around 0=N 663 * and overwrite fri unconditionally. Now from case 2a, 664 * this means that b eclipsed fri to overwrite it and wrap 665 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 666 * set fri = b + 1 (mod N). 667 * Now, since fri is updated in every case, except the trivial case 0, 668 * the number of records present in the table after writing, is, 669 * num_recs - 1 = b - fri (mod N), and we take the positive value, 670 * by adding an arbitrary multiple of N before taking the modulo N 671 * as shown below. 672 */ 673 a = control->ras_fri + control->ras_num_recs; 674 b = a + num - 1; 675 if (b < control->ras_max_record_count) { 676 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 677 } else if (a < control->ras_max_record_count) { 678 u32 g0, g1; 679 680 g0 = control->ras_max_record_count - a; 681 g1 = b % control->ras_max_record_count + 1; 682 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 683 if (res) 684 goto Out; 685 res = __amdgpu_ras_eeprom_write(control, 686 buf + g0 * RAS_TABLE_RECORD_SIZE, 687 0, g1); 688 if (res) 689 goto Out; 690 if (g1 > control->ras_fri) 691 control->ras_fri = g1 % control->ras_max_record_count; 692 } else { 693 a %= control->ras_max_record_count; 694 b %= control->ras_max_record_count; 695 696 if (a <= b) { 697 /* Note that, b - a + 1 = num. */ 698 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 699 if (res) 700 goto Out; 701 if (b >= control->ras_fri) 702 control->ras_fri = (b + 1) % control->ras_max_record_count; 703 } else { 704 u32 g0, g1; 705 706 /* b < a, which means, we write from 707 * a to the end of the table, and from 708 * the start of the table to b. 709 */ 710 g0 = control->ras_max_record_count - a; 711 g1 = b + 1; 712 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 713 if (res) 714 goto Out; 715 res = __amdgpu_ras_eeprom_write(control, 716 buf + g0 * RAS_TABLE_RECORD_SIZE, 717 0, g1); 718 if (res) 719 goto Out; 720 control->ras_fri = g1 % control->ras_max_record_count; 721 } 722 } 723 control->ras_num_recs = 1 + (control->ras_max_record_count + b 724 - control->ras_fri) 725 % control->ras_max_record_count; 726 Out: 727 kfree(buf); 728 return res; 729 } 730 731 static int 732 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 733 { 734 struct amdgpu_device *adev = to_amdgpu_device(control); 735 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 736 u8 *buf, *pp, csum; 737 u32 buf_size; 738 int res; 739 740 /* Modify the header if it exceeds. 741 */ 742 if (amdgpu_bad_page_threshold != 0 && 743 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 744 dev_warn(adev->dev, 745 "Saved bad pages %d reaches threshold value %d\n", 746 control->ras_num_recs, ras->bad_page_cnt_threshold); 747 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 748 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { 749 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 750 control->tbl_rai.health_percent = 0; 751 } 752 753 if (amdgpu_bad_page_threshold != -1) 754 ras->is_rma = true; 755 756 /* ignore the -ENOTSUPP return value */ 757 amdgpu_dpm_send_rma_reason(adev); 758 } 759 760 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 761 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 762 RAS_TABLE_V2_1_INFO_SIZE + 763 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 764 else 765 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 766 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 767 control->tbl_hdr.checksum = 0; 768 769 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 770 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 771 if (!buf) { 772 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 773 control->tbl_hdr.tbl_size); 774 res = -ENOMEM; 775 goto Out; 776 } 777 778 down_read(&adev->reset_domain->sem); 779 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 780 control->i2c_address + 781 control->ras_record_offset, 782 buf, buf_size); 783 up_read(&adev->reset_domain->sem); 784 if (res < 0) { 785 DRM_ERROR("EEPROM failed reading records:%d\n", 786 res); 787 goto Out; 788 } else if (res < buf_size) { 789 DRM_ERROR("EEPROM read %d out of %d bytes\n", 790 res, buf_size); 791 res = -EIO; 792 goto Out; 793 } 794 795 /** 796 * bad page records have been stored in eeprom, 797 * now calculate gpu health percent 798 */ 799 if (amdgpu_bad_page_threshold != 0 && 800 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && 801 control->ras_num_recs < ras->bad_page_cnt_threshold) 802 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 803 control->ras_num_recs) * 100) / 804 ras->bad_page_cnt_threshold; 805 806 /* Recalc the checksum. 807 */ 808 csum = 0; 809 for (pp = buf; pp < buf + buf_size; pp++) 810 csum += *pp; 811 812 csum += __calc_hdr_byte_sum(control); 813 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 814 csum += __calc_ras_info_byte_sum(control); 815 /* avoid sign extension when assigning to "checksum" */ 816 csum = -csum; 817 control->tbl_hdr.checksum = csum; 818 res = __write_table_header(control); 819 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 820 res = __write_table_ras_info(control); 821 Out: 822 kfree(buf); 823 return res; 824 } 825 826 /** 827 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 828 * @control: pointer to control structure 829 * @record: array of records to append 830 * @num: number of records in @record array 831 * 832 * Append @num records to the table, calculate the checksum and write 833 * the table back to EEPROM. The maximum number of records that 834 * can be appended is between 1 and control->ras_max_record_count, 835 * regardless of how many records are already stored in the table. 836 * 837 * Return 0 on success or if EEPROM is not supported, -errno on error. 838 */ 839 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 840 struct eeprom_table_record *record, 841 const u32 num) 842 { 843 struct amdgpu_device *adev = to_amdgpu_device(control); 844 int res; 845 846 if (!__is_ras_eeprom_supported(adev)) 847 return 0; 848 849 if (num == 0) { 850 DRM_ERROR("will not append 0 records\n"); 851 return -EINVAL; 852 } else if (num > control->ras_max_record_count) { 853 DRM_ERROR("cannot append %d records than the size of table %d\n", 854 num, control->ras_max_record_count); 855 return -EINVAL; 856 } 857 858 mutex_lock(&control->ras_tbl_mutex); 859 860 res = amdgpu_ras_eeprom_append_table(control, record, num); 861 if (!res) 862 res = amdgpu_ras_eeprom_update_header(control); 863 if (!res) 864 amdgpu_ras_debugfs_set_ret_size(control); 865 866 mutex_unlock(&control->ras_tbl_mutex); 867 return res; 868 } 869 870 /** 871 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 872 * @control: pointer to control structure 873 * @buf: pointer to buffer to read into 874 * @fri: first record index, start reading at this index, absolute index 875 * @num: number of records to read 876 * 877 * The caller must hold the table mutex in @control. 878 * Return 0 on success, -errno otherwise. 879 */ 880 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 881 u8 *buf, const u32 fri, const u32 num) 882 { 883 struct amdgpu_device *adev = to_amdgpu_device(control); 884 u32 buf_size; 885 int res; 886 887 /* i2c may be unstable in gpu reset */ 888 down_read(&adev->reset_domain->sem); 889 buf_size = num * RAS_TABLE_RECORD_SIZE; 890 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 891 control->i2c_address + 892 RAS_INDEX_TO_OFFSET(control, fri), 893 buf, buf_size); 894 up_read(&adev->reset_domain->sem); 895 if (res < 0) { 896 DRM_ERROR("Reading %d EEPROM table records error:%d", 897 num, res); 898 } else if (res < buf_size) { 899 /* Short read, return error. 900 */ 901 DRM_ERROR("Read %d records out of %d", 902 res / RAS_TABLE_RECORD_SIZE, num); 903 res = -EIO; 904 } else { 905 res = 0; 906 } 907 908 return res; 909 } 910 911 /** 912 * amdgpu_ras_eeprom_read -- read EEPROM 913 * @control: pointer to control structure 914 * @record: array of records to read into 915 * @num: number of records in @record 916 * 917 * Reads num records from the RAS table in EEPROM and 918 * writes the data into @record array. 919 * 920 * Returns 0 on success, -errno on error. 921 */ 922 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 923 struct eeprom_table_record *record, 924 const u32 num) 925 { 926 struct amdgpu_device *adev = to_amdgpu_device(control); 927 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 928 int i, res; 929 u8 *buf, *pp; 930 u32 g0, g1; 931 932 if (!__is_ras_eeprom_supported(adev)) 933 return 0; 934 935 if (num == 0) { 936 DRM_ERROR("will not read 0 records\n"); 937 return -EINVAL; 938 } else if (num > control->ras_num_recs) { 939 DRM_ERROR("too many records to read:%d available:%d\n", 940 num, control->ras_num_recs); 941 return -EINVAL; 942 } 943 944 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 945 if (!buf) 946 return -ENOMEM; 947 948 /* Determine how many records to read, from the first record 949 * index, fri, to the end of the table, and from the beginning 950 * of the table, such that the total number of records is 951 * @num, and we handle wrap around when fri > 0 and 952 * fri + num > RAS_MAX_RECORD_COUNT. 953 * 954 * First we compute the index of the last element 955 * which would be fetched from each region, 956 * g0 is in [fri, fri + num - 1], and 957 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 958 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 959 * the last element to fetch, we set g0 to _the number_ 960 * of elements to fetch, @num, since we know that the last 961 * indexed to be fetched does not exceed the table. 962 * 963 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 964 * we set g0 to the number of elements to read 965 * until the end of the table, and g1 to the number of 966 * elements to read from the beginning of the table. 967 */ 968 g0 = control->ras_fri + num - 1; 969 g1 = g0 % control->ras_max_record_count; 970 if (g0 < control->ras_max_record_count) { 971 g0 = num; 972 g1 = 0; 973 } else { 974 g0 = control->ras_max_record_count - control->ras_fri; 975 g1 += 1; 976 } 977 978 mutex_lock(&control->ras_tbl_mutex); 979 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 980 if (res) 981 goto Out; 982 if (g1) { 983 res = __amdgpu_ras_eeprom_read(control, 984 buf + g0 * RAS_TABLE_RECORD_SIZE, 985 0, g1); 986 if (res) 987 goto Out; 988 } 989 990 res = 0; 991 992 /* Read up everything? Then transform. 993 */ 994 pp = buf; 995 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 996 __decode_table_record_from_buf(control, &record[i], pp); 997 998 /* update bad channel bitmap */ 999 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1000 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1001 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1002 con->update_channel_flag = true; 1003 } 1004 } 1005 Out: 1006 kfree(buf); 1007 mutex_unlock(&control->ras_tbl_mutex); 1008 1009 return res; 1010 } 1011 1012 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1013 { 1014 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1015 return RAS_MAX_RECORD_COUNT_V2_1; 1016 else 1017 return RAS_MAX_RECORD_COUNT; 1018 } 1019 1020 static ssize_t 1021 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1022 size_t size, loff_t *pos) 1023 { 1024 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1025 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1026 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1027 u8 data[50]; 1028 int res; 1029 1030 if (!size) 1031 return size; 1032 1033 if (!ras || !control) { 1034 res = snprintf(data, sizeof(data), "Not supported\n"); 1035 } else { 1036 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1037 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1038 } 1039 1040 if (*pos >= res) 1041 return 0; 1042 1043 res -= *pos; 1044 res = min_t(size_t, res, size); 1045 1046 if (copy_to_user(buf, &data[*pos], res)) 1047 return -EFAULT; 1048 1049 *pos += res; 1050 1051 return res; 1052 } 1053 1054 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1055 .owner = THIS_MODULE, 1056 .read = amdgpu_ras_debugfs_eeprom_size_read, 1057 .write = NULL, 1058 .llseek = default_llseek, 1059 }; 1060 1061 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1062 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1063 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1064 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1065 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1066 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1067 1068 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1069 "ignore", 1070 "re", 1071 "ue", 1072 }; 1073 1074 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1075 { 1076 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1077 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1078 } 1079 1080 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1081 { 1082 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1083 eeprom_control); 1084 struct dentry *de = ras->de_ras_eeprom_table; 1085 1086 if (de) 1087 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1088 } 1089 1090 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1091 size_t size, loff_t *pos) 1092 { 1093 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1094 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1095 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1096 const size_t orig_size = size; 1097 int res = -EFAULT; 1098 size_t data_len; 1099 1100 mutex_lock(&control->ras_tbl_mutex); 1101 1102 /* We want *pos - data_len > 0, which means there's 1103 * bytes to be printed from data. 1104 */ 1105 data_len = strlen(tbl_hdr_str); 1106 if (*pos < data_len) { 1107 data_len -= *pos; 1108 data_len = min_t(size_t, data_len, size); 1109 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1110 goto Out; 1111 buf += data_len; 1112 size -= data_len; 1113 *pos += data_len; 1114 } 1115 1116 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1117 if (*pos < data_len && size > 0) { 1118 u8 data[tbl_hdr_fmt_size + 1]; 1119 loff_t lpos; 1120 1121 snprintf(data, sizeof(data), tbl_hdr_fmt, 1122 control->tbl_hdr.header, 1123 control->tbl_hdr.version, 1124 control->tbl_hdr.first_rec_offset, 1125 control->tbl_hdr.tbl_size, 1126 control->tbl_hdr.checksum); 1127 1128 data_len -= *pos; 1129 data_len = min_t(size_t, data_len, size); 1130 lpos = *pos - strlen(tbl_hdr_str); 1131 if (copy_to_user(buf, &data[lpos], data_len)) 1132 goto Out; 1133 buf += data_len; 1134 size -= data_len; 1135 *pos += data_len; 1136 } 1137 1138 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1139 if (*pos < data_len && size > 0) { 1140 loff_t lpos; 1141 1142 data_len -= *pos; 1143 data_len = min_t(size_t, data_len, size); 1144 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1145 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1146 goto Out; 1147 buf += data_len; 1148 size -= data_len; 1149 *pos += data_len; 1150 } 1151 1152 data_len = amdgpu_ras_debugfs_table_size(control); 1153 if (*pos < data_len && size > 0) { 1154 u8 dare[RAS_TABLE_RECORD_SIZE]; 1155 u8 data[rec_hdr_fmt_size + 1]; 1156 struct eeprom_table_record record; 1157 int s, r; 1158 1159 /* Find the starting record index 1160 */ 1161 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1162 strlen(rec_hdr_str); 1163 s = s / rec_hdr_fmt_size; 1164 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1165 strlen(rec_hdr_str); 1166 r = r % rec_hdr_fmt_size; 1167 1168 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1169 u32 ai = RAS_RI_TO_AI(control, s); 1170 /* Read a single record 1171 */ 1172 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1173 if (res) 1174 goto Out; 1175 __decode_table_record_from_buf(control, &record, dare); 1176 snprintf(data, sizeof(data), rec_hdr_fmt, 1177 s, 1178 RAS_INDEX_TO_OFFSET(control, ai), 1179 record_err_type_str[record.err_type], 1180 record.bank, 1181 record.ts, 1182 record.offset, 1183 record.mem_channel, 1184 record.mcumc_id, 1185 record.retired_page); 1186 1187 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1188 if (copy_to_user(buf, &data[r], data_len)) { 1189 res = -EFAULT; 1190 goto Out; 1191 } 1192 buf += data_len; 1193 size -= data_len; 1194 *pos += data_len; 1195 r = 0; 1196 } 1197 } 1198 res = 0; 1199 Out: 1200 mutex_unlock(&control->ras_tbl_mutex); 1201 return res < 0 ? res : orig_size - size; 1202 } 1203 1204 static ssize_t 1205 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1206 size_t size, loff_t *pos) 1207 { 1208 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1209 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1210 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1211 u8 data[81]; 1212 int res; 1213 1214 if (!size) 1215 return size; 1216 1217 if (!ras || !control) { 1218 res = snprintf(data, sizeof(data), "Not supported\n"); 1219 if (*pos >= res) 1220 return 0; 1221 1222 res -= *pos; 1223 res = min_t(size_t, res, size); 1224 1225 if (copy_to_user(buf, &data[*pos], res)) 1226 return -EFAULT; 1227 1228 *pos += res; 1229 1230 return res; 1231 } else { 1232 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1233 } 1234 } 1235 1236 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1237 .owner = THIS_MODULE, 1238 .read = amdgpu_ras_debugfs_eeprom_table_read, 1239 .write = NULL, 1240 .llseek = default_llseek, 1241 }; 1242 1243 /** 1244 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1245 * @control: pointer to control structure 1246 * 1247 * Check the checksum of the stored in EEPROM RAS table. 1248 * 1249 * Return 0 if the checksum is correct, 1250 * positive if it is not correct, and 1251 * -errno on I/O error. 1252 */ 1253 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1254 { 1255 struct amdgpu_device *adev = to_amdgpu_device(control); 1256 int buf_size, res; 1257 u8 csum, *buf, *pp; 1258 1259 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1260 buf_size = RAS_TABLE_HEADER_SIZE + 1261 RAS_TABLE_V2_1_INFO_SIZE + 1262 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1263 else 1264 buf_size = RAS_TABLE_HEADER_SIZE + 1265 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1266 1267 buf = kzalloc(buf_size, GFP_KERNEL); 1268 if (!buf) { 1269 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1270 return -ENOMEM; 1271 } 1272 1273 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1274 control->i2c_address + 1275 control->ras_header_offset, 1276 buf, buf_size); 1277 if (res < buf_size) { 1278 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1279 /* On partial reads, return -EIO. 1280 */ 1281 if (res >= 0) 1282 res = -EIO; 1283 goto Out; 1284 } 1285 1286 csum = 0; 1287 for (pp = buf; pp < buf + buf_size; pp++) 1288 csum += *pp; 1289 Out: 1290 kfree(buf); 1291 return res < 0 ? res : csum; 1292 } 1293 1294 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1295 { 1296 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1297 struct amdgpu_device *adev = to_amdgpu_device(control); 1298 unsigned char *buf; 1299 int res; 1300 1301 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1302 if (!buf) { 1303 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1304 return -ENOMEM; 1305 } 1306 1307 /** 1308 * EEPROM table V2_1 supports ras info, 1309 * read EEPROM table ras info 1310 */ 1311 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1312 control->i2c_address + control->ras_info_offset, 1313 buf, RAS_TABLE_V2_1_INFO_SIZE); 1314 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1315 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1316 res = res >= 0 ? -EIO : res; 1317 goto Out; 1318 } 1319 1320 __decode_table_ras_info_from_buf(rai, buf); 1321 1322 Out: 1323 kfree(buf); 1324 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1325 } 1326 1327 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1328 { 1329 struct amdgpu_device *adev = to_amdgpu_device(control); 1330 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1331 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1332 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1333 int res; 1334 1335 ras->is_rma = false; 1336 1337 if (!__is_ras_eeprom_supported(adev)) 1338 return 0; 1339 1340 /* Verify i2c adapter is initialized */ 1341 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1342 return -ENOENT; 1343 1344 if (!__get_eeprom_i2c_addr(adev, control)) 1345 return -EINVAL; 1346 1347 control->ras_header_offset = RAS_HDR_START; 1348 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1349 mutex_init(&control->ras_tbl_mutex); 1350 1351 /* Read the table header from EEPROM address */ 1352 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1353 control->i2c_address + control->ras_header_offset, 1354 buf, RAS_TABLE_HEADER_SIZE); 1355 if (res < RAS_TABLE_HEADER_SIZE) { 1356 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1357 return res >= 0 ? -EIO : res; 1358 } 1359 1360 __decode_table_header_from_buf(hdr, buf); 1361 1362 if (hdr->version == RAS_TABLE_VER_V2_1) { 1363 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1364 control->ras_record_offset = RAS_RECORD_START_V2_1; 1365 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1366 } else { 1367 control->ras_num_recs = RAS_NUM_RECS(hdr); 1368 control->ras_record_offset = RAS_RECORD_START; 1369 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1370 } 1371 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1372 1373 if (hdr->header == RAS_TABLE_HDR_VAL) { 1374 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1375 control->ras_num_recs); 1376 1377 if (hdr->version == RAS_TABLE_VER_V2_1) { 1378 res = __read_table_ras_info(control); 1379 if (res) 1380 return res; 1381 } 1382 1383 res = __verify_ras_table_checksum(control); 1384 if (res) 1385 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1386 res); 1387 1388 /* Warn if we are at 90% of the threshold or above 1389 */ 1390 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1391 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1392 control->ras_num_recs, 1393 ras->bad_page_cnt_threshold); 1394 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1395 amdgpu_bad_page_threshold != 0) { 1396 if (hdr->version == RAS_TABLE_VER_V2_1) { 1397 res = __read_table_ras_info(control); 1398 if (res) 1399 return res; 1400 } 1401 1402 res = __verify_ras_table_checksum(control); 1403 if (res) 1404 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1405 res); 1406 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1407 /* This means that, the threshold was increased since 1408 * the last time the system was booted, and now, 1409 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1410 * so that at least one more record can be saved, 1411 * before the page count threshold is reached. 1412 */ 1413 dev_info(adev->dev, 1414 "records:%d threshold:%d, resetting " 1415 "RAS table header signature", 1416 control->ras_num_recs, 1417 ras->bad_page_cnt_threshold); 1418 res = amdgpu_ras_eeprom_correct_header_tag(control, 1419 RAS_TABLE_HDR_VAL); 1420 } else { 1421 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1422 control->ras_num_recs, ras->bad_page_cnt_threshold); 1423 if (amdgpu_bad_page_threshold == -1) { 1424 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1."); 1425 res = 0; 1426 } else { 1427 ras->is_rma = true; 1428 dev_err(adev->dev, 1429 "RAS records:%d exceed threshold:%d, " 1430 "GPU will not be initialized. Replace this GPU or increase the threshold", 1431 control->ras_num_recs, ras->bad_page_cnt_threshold); 1432 } 1433 } 1434 } else { 1435 DRM_INFO("Creating a new EEPROM table"); 1436 1437 res = amdgpu_ras_eeprom_reset_table(control); 1438 } 1439 1440 return res < 0 ? res : 0; 1441 } 1442