1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 #include "amdgpu_ras_mgr.h" 36 37 /* These are memory addresses as would be seen by one or more EEPROM 38 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 39 * set of EEPROM devices. They form a continuous memory space. 40 * 41 * The I2C device address includes the device type identifier, 1010b, 42 * which is a reserved value and indicates that this is an I2C EEPROM 43 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 44 * address, namely bits 18, 17, and 16. This makes up the 7 bit 45 * address sent on the I2C bus with bit 0 being the direction bit, 46 * which is not represented here, and sent by the hardware directly. 47 * 48 * For instance, 49 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 50 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 51 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 52 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 53 * address memory in a device or a device on the I2C bus, depending on 54 * the status of pins 1-3. See top of amdgpu_eeprom.c. 55 * 56 * The RAS table lives either at address 0 or address 40000h of EEPROM. 57 */ 58 #define EEPROM_I2C_MADDR_0 0x0 59 #define EEPROM_I2C_MADDR_4 0x40000 60 61 /* 62 * The 2 macros below represent the actual size in bytes that 63 * those entities occupy in the EEPROM memory. 64 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 65 * uses uint64 to store 6b fields such as retired_page. 66 */ 67 #define RAS_TABLE_HEADER_SIZE 20 68 #define RAS_TABLE_RECORD_SIZE 24 69 70 /* Table hdr is 'AMDR' */ 71 #define RAS_TABLE_HDR_VAL 0x414d4452 72 73 /* Bad GPU tag ‘BADG’ */ 74 #define RAS_TABLE_HDR_BAD 0x42414447 75 76 /* 77 * EEPROM Table structure v1 78 * --------------------------------- 79 * | | 80 * | EEPROM TABLE HEADER | 81 * | ( size 20 Bytes ) | 82 * | | 83 * --------------------------------- 84 * | | 85 * | BAD PAGE RECORD AREA | 86 * | | 87 * --------------------------------- 88 */ 89 90 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 91 #define RAS_TBL_SIZE_BYTES (256 * 1024) 92 #define RAS_TABLE_START 0 93 #define RAS_HDR_START RAS_TABLE_START 94 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 95 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 96 / RAS_TABLE_RECORD_SIZE) 97 98 /* 99 * EEPROM Table structrue v2.1 100 * --------------------------------- 101 * | | 102 * | EEPROM TABLE HEADER | 103 * | ( size 20 Bytes ) | 104 * | | 105 * --------------------------------- 106 * | | 107 * | EEPROM TABLE RAS INFO | 108 * | (available info size 4 Bytes) | 109 * | ( reserved size 252 Bytes ) | 110 * | | 111 * --------------------------------- 112 * | | 113 * | BAD PAGE RECORD AREA | 114 * | | 115 * --------------------------------- 116 */ 117 118 /* EEPROM Table V2_1 */ 119 #define RAS_TABLE_V2_1_INFO_SIZE 256 120 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 121 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 122 RAS_TABLE_V2_1_INFO_SIZE) 123 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 124 RAS_TABLE_V2_1_INFO_SIZE) \ 125 / RAS_TABLE_RECORD_SIZE) 126 127 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 128 * offset off of RAS_TABLE_START. That is, this is something you can 129 * add to control->i2c_address, and then tell I2C layer to read 130 * from/write to there. _N is the so called absolute index, 131 * because it starts right after the table header. 132 */ 133 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 134 (_N) * RAS_TABLE_RECORD_SIZE) 135 136 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 137 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 138 139 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 140 * of "fri", return the absolute record index off of the end of 141 * the table header. 142 */ 143 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 144 (_C)->ras_max_record_count) 145 146 #define RAS_NUM_RECS(_tbl_hdr) \ 147 (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE) ? 0u : \ 148 (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)) 149 150 #define RAS_NUM_RECS_V2_1(_tbl_hdr) \ 151 (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE + \ 152 RAS_TABLE_V2_1_INFO_SIZE) ? 0u : \ 153 (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE - \ 154 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)) 155 156 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 157 158 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 159 { 160 if (amdgpu_sriov_vf(adev)) 161 return false; 162 163 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 164 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 165 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 166 case IP_VERSION(13, 0, 0): 167 case IP_VERSION(13, 0, 2): /* Aldebaran */ 168 case IP_VERSION(13, 0, 10): 169 return true; 170 case IP_VERSION(13, 0, 6): 171 case IP_VERSION(13, 0, 12): 172 case IP_VERSION(13, 0, 14): 173 return (adev->gmc.is_app_apu) ? false : true; 174 default: 175 return false; 176 } 177 } 178 179 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 180 struct amdgpu_ras_eeprom_control *control) 181 { 182 struct atom_context *atom_ctx = adev->mode_info.atom_context; 183 u8 i2c_addr; 184 185 if (!control) 186 return false; 187 188 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 189 /* The address given by VBIOS is an 8-bit, wire-format 190 * address, i.e. the most significant byte. 191 * 192 * Normalize it to a 19-bit EEPROM address. Remove the 193 * device type identifier and make it a 7-bit address; 194 * then make it a 19-bit EEPROM address. See top of 195 * amdgpu_eeprom.c. 196 */ 197 i2c_addr = (i2c_addr & 0x0F) >> 1; 198 control->i2c_address = ((u32) i2c_addr) << 16; 199 200 return true; 201 } 202 203 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 204 case IP_VERSION(11, 0, 2): 205 /* VEGA20 and ARCTURUS */ 206 if (adev->asic_type == CHIP_VEGA20) 207 control->i2c_address = EEPROM_I2C_MADDR_0; 208 else if (strnstr(atom_ctx->vbios_pn, 209 "D342", 210 sizeof(atom_ctx->vbios_pn))) 211 control->i2c_address = EEPROM_I2C_MADDR_0; 212 else 213 control->i2c_address = EEPROM_I2C_MADDR_4; 214 return true; 215 case IP_VERSION(11, 0, 7): 216 control->i2c_address = EEPROM_I2C_MADDR_0; 217 return true; 218 case IP_VERSION(13, 0, 2): 219 if (strnstr(atom_ctx->vbios_pn, "D673", 220 sizeof(atom_ctx->vbios_pn))) 221 control->i2c_address = EEPROM_I2C_MADDR_4; 222 else 223 control->i2c_address = EEPROM_I2C_MADDR_0; 224 return true; 225 case IP_VERSION(13, 0, 0): 226 if (strnstr(atom_ctx->vbios_pn, "D707", 227 sizeof(atom_ctx->vbios_pn))) 228 control->i2c_address = EEPROM_I2C_MADDR_0; 229 else 230 control->i2c_address = EEPROM_I2C_MADDR_4; 231 return true; 232 case IP_VERSION(13, 0, 6): 233 case IP_VERSION(13, 0, 10): 234 case IP_VERSION(13, 0, 12): 235 case IP_VERSION(13, 0, 14): 236 control->i2c_address = EEPROM_I2C_MADDR_4; 237 return true; 238 default: 239 return false; 240 } 241 } 242 243 static void 244 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 245 unsigned char *buf) 246 { 247 u32 *pp = (uint32_t *)buf; 248 249 pp[0] = cpu_to_le32(hdr->header); 250 pp[1] = cpu_to_le32(hdr->version); 251 pp[2] = cpu_to_le32(hdr->first_rec_offset); 252 pp[3] = cpu_to_le32(hdr->tbl_size); 253 pp[4] = cpu_to_le32(hdr->checksum); 254 } 255 256 static void 257 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 258 unsigned char *buf) 259 { 260 u32 *pp = (uint32_t *)buf; 261 262 hdr->header = le32_to_cpu(pp[0]); 263 hdr->version = le32_to_cpu(pp[1]); 264 hdr->first_rec_offset = le32_to_cpu(pp[2]); 265 hdr->tbl_size = le32_to_cpu(pp[3]); 266 hdr->checksum = le32_to_cpu(pp[4]); 267 } 268 269 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 270 { 271 u8 buf[RAS_TABLE_HEADER_SIZE]; 272 struct amdgpu_device *adev = to_amdgpu_device(control); 273 int res; 274 275 memset(buf, 0, sizeof(buf)); 276 __encode_table_header_to_buf(&control->tbl_hdr, buf); 277 278 /* i2c may be unstable in gpu reset */ 279 down_read(&adev->reset_domain->sem); 280 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 281 control->i2c_address + 282 control->ras_header_offset, 283 buf, RAS_TABLE_HEADER_SIZE); 284 up_read(&adev->reset_domain->sem); 285 286 if (res < 0) { 287 dev_err(adev->dev, "Failed to write EEPROM table header:%d", 288 res); 289 } else if (res < RAS_TABLE_HEADER_SIZE) { 290 dev_err(adev->dev, "Short write:%d out of %d\n", res, 291 RAS_TABLE_HEADER_SIZE); 292 res = -EIO; 293 } else { 294 res = 0; 295 } 296 297 return res; 298 } 299 300 static void 301 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 302 unsigned char *buf) 303 { 304 u32 *pp = (uint32_t *)buf; 305 u32 tmp; 306 307 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 308 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 309 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 310 pp[0] = cpu_to_le32(tmp); 311 } 312 313 static void 314 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 315 unsigned char *buf) 316 { 317 u32 *pp = (uint32_t *)buf; 318 u32 tmp; 319 320 tmp = le32_to_cpu(pp[0]); 321 rai->rma_status = tmp & 0xFF; 322 rai->health_percent = (tmp >> 8) & 0xFF; 323 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 324 } 325 326 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 327 { 328 struct amdgpu_device *adev = to_amdgpu_device(control); 329 u8 *buf; 330 int res; 331 332 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 333 if (!buf) { 334 dev_err(adev->dev, 335 "Failed to alloc buf to write table ras info\n"); 336 return -ENOMEM; 337 } 338 339 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 340 341 /* i2c may be unstable in gpu reset */ 342 down_read(&adev->reset_domain->sem); 343 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 344 control->i2c_address + 345 control->ras_info_offset, 346 buf, RAS_TABLE_V2_1_INFO_SIZE); 347 up_read(&adev->reset_domain->sem); 348 349 if (res < 0) { 350 dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", 351 res); 352 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 353 dev_err(adev->dev, "Short write:%d out of %d\n", res, 354 RAS_TABLE_V2_1_INFO_SIZE); 355 res = -EIO; 356 } else { 357 res = 0; 358 } 359 360 kfree(buf); 361 362 return res; 363 } 364 365 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 366 { 367 int ii; 368 u8 *pp, csum; 369 size_t sz; 370 371 /* Header checksum, skip checksum field in the calculation */ 372 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 373 pp = (u8 *) &control->tbl_hdr; 374 csum = 0; 375 for (ii = 0; ii < sz; ii++, pp++) 376 csum += *pp; 377 378 return csum; 379 } 380 381 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 382 { 383 int ii; 384 u8 *pp, csum; 385 size_t sz; 386 387 sz = sizeof(control->tbl_rai); 388 pp = (u8 *) &control->tbl_rai; 389 csum = 0; 390 for (ii = 0; ii < sz; ii++, pp++) 391 csum += *pp; 392 393 return csum; 394 } 395 396 static int amdgpu_ras_eeprom_correct_header_tag( 397 struct amdgpu_ras_eeprom_control *control, 398 uint32_t header) 399 { 400 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 401 u8 *hh; 402 int res; 403 u8 csum; 404 405 csum = -hdr->checksum; 406 407 hh = (void *) &hdr->header; 408 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 409 hh = (void *) &header; 410 csum += hh[0] + hh[1] + hh[2] + hh[3]; 411 csum = -csum; 412 mutex_lock(&control->ras_tbl_mutex); 413 hdr->header = header; 414 hdr->checksum = csum; 415 res = __write_table_header(control); 416 mutex_unlock(&control->ras_tbl_mutex); 417 418 return res; 419 } 420 421 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 422 { 423 struct amdgpu_device *adev = to_amdgpu_device(control); 424 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 425 426 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 427 case IP_VERSION(8, 10, 0): 428 hdr->version = RAS_TABLE_VER_V2_1; 429 return; 430 case IP_VERSION(12, 0, 0): 431 case IP_VERSION(12, 5, 0): 432 hdr->version = RAS_TABLE_VER_V3; 433 return; 434 default: 435 hdr->version = RAS_TABLE_VER_V1; 436 return; 437 } 438 } 439 440 /** 441 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 442 * @control: pointer to control structure 443 * 444 * Reset the contents of the header of the RAS EEPROM table. 445 * Return 0 on success, -errno on error. 446 */ 447 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 448 { 449 struct amdgpu_device *adev = to_amdgpu_device(control); 450 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 451 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 452 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 453 u8 csum; 454 int res; 455 456 mutex_lock(&control->ras_tbl_mutex); 457 458 hdr->header = RAS_TABLE_HDR_VAL; 459 amdgpu_ras_set_eeprom_table_version(control); 460 461 if (hdr->version >= RAS_TABLE_VER_V2_1) { 462 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 463 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 464 RAS_TABLE_V2_1_INFO_SIZE; 465 rai->rma_status = GPU_HEALTH_USABLE; 466 467 control->ras_record_offset = RAS_RECORD_START_V2_1; 468 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 469 /** 470 * GPU health represented as a percentage. 471 * 0 means worst health, 100 means fully health. 472 */ 473 rai->health_percent = 100; 474 /* ecc_page_threshold = 0 means disable bad page retirement */ 475 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 476 } else { 477 hdr->first_rec_offset = RAS_RECORD_START; 478 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 479 480 control->ras_record_offset = RAS_RECORD_START; 481 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 482 } 483 484 csum = __calc_hdr_byte_sum(control); 485 if (hdr->version >= RAS_TABLE_VER_V2_1) 486 csum += __calc_ras_info_byte_sum(control); 487 csum = -csum; 488 hdr->checksum = csum; 489 res = __write_table_header(control); 490 if (!res && hdr->version > RAS_TABLE_VER_V1) 491 res = __write_table_ras_info(control); 492 493 control->ras_num_recs = 0; 494 control->ras_num_bad_pages = 0; 495 control->ras_num_mca_recs = 0; 496 control->ras_num_pa_recs = 0; 497 control->ras_fri = 0; 498 499 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); 500 501 control->bad_channel_bitmap = 0; 502 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 503 con->update_channel_flag = false; 504 /* there is no record on eeprom now, clear the counter */ 505 if (con->eh_data) 506 con->eh_data->count_saved = 0; 507 508 amdgpu_ras_debugfs_set_ret_size(control); 509 510 mutex_unlock(&control->ras_tbl_mutex); 511 512 return res; 513 } 514 515 static void 516 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 517 struct eeprom_table_record *record, 518 unsigned char *buf) 519 { 520 __le64 tmp = 0; 521 int i = 0; 522 523 /* Next are all record fields according to EEPROM page spec in LE foramt */ 524 buf[i++] = record->err_type; 525 526 buf[i++] = record->bank; 527 528 tmp = cpu_to_le64(record->ts); 529 memcpy(buf + i, &tmp, 8); 530 i += 8; 531 532 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 533 memcpy(buf + i, &tmp, 6); 534 i += 6; 535 536 buf[i++] = record->mem_channel; 537 buf[i++] = record->mcumc_id; 538 539 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 540 memcpy(buf + i, &tmp, 6); 541 } 542 543 static void 544 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 545 struct eeprom_table_record *record, 546 unsigned char *buf) 547 { 548 __le64 tmp = 0; 549 int i = 0; 550 551 /* Next are all record fields according to EEPROM page spec in LE foramt */ 552 record->err_type = buf[i++]; 553 554 record->bank = buf[i++]; 555 556 memcpy(&tmp, buf + i, 8); 557 record->ts = le64_to_cpu(tmp); 558 i += 8; 559 560 memcpy(&tmp, buf + i, 6); 561 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 562 i += 6; 563 564 record->mem_channel = buf[i++]; 565 record->mcumc_id = buf[i++]; 566 567 memcpy(&tmp, buf + i, 6); 568 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 569 } 570 571 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 572 { 573 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 574 575 if (amdgpu_uniras_enabled(adev)) 576 return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev); 577 578 if (!__is_ras_eeprom_supported(adev) || 579 !amdgpu_bad_page_threshold) 580 return false; 581 582 /* skip check eeprom table for VEGA20 Gaming */ 583 if (!con) 584 return false; 585 else 586 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 587 return false; 588 589 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 590 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold) 591 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 592 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold); 593 if ((amdgpu_bad_page_threshold == -1) || 594 (amdgpu_bad_page_threshold == -2)) { 595 dev_warn(adev->dev, 596 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 597 return false; 598 } else { 599 dev_warn(adev->dev, 600 "Please consider adjusting the customized threshold.\n"); 601 return true; 602 } 603 } 604 605 return false; 606 } 607 608 /** 609 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 610 * @control: pointer to control structure 611 * @buf: pointer to buffer containing data to write 612 * @fri: start writing at this index 613 * @num: number of records to write 614 * 615 * The caller must hold the table mutex in @control. 616 * Return 0 on success, -errno otherwise. 617 */ 618 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 619 u8 *buf, const u32 fri, const u32 num) 620 { 621 struct amdgpu_device *adev = to_amdgpu_device(control); 622 u32 buf_size; 623 int res; 624 625 /* i2c may be unstable in gpu reset */ 626 down_read(&adev->reset_domain->sem); 627 buf_size = num * RAS_TABLE_RECORD_SIZE; 628 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 629 control->i2c_address + 630 RAS_INDEX_TO_OFFSET(control, fri), 631 buf, buf_size); 632 up_read(&adev->reset_domain->sem); 633 if (res < 0) { 634 dev_err(adev->dev, "Writing %d EEPROM table records error:%d", 635 num, res); 636 } else if (res < buf_size) { 637 /* Short write, return error. 638 */ 639 dev_err(adev->dev, "Wrote %d records out of %d", 640 res / RAS_TABLE_RECORD_SIZE, num); 641 res = -EIO; 642 } else { 643 res = 0; 644 } 645 646 return res; 647 } 648 649 static int 650 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 651 struct eeprom_table_record *record, 652 const u32 num) 653 { 654 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 655 u32 a, b, i; 656 u8 *buf, *pp; 657 int res; 658 659 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 660 if (!buf) 661 return -ENOMEM; 662 663 /* Encode all of them in one go. 664 */ 665 pp = buf; 666 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 667 __encode_table_record_to_buf(control, &record[i], pp); 668 669 /* update bad channel bitmap */ 670 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 671 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 672 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 673 con->update_channel_flag = true; 674 } 675 } 676 677 /* a, first record index to write into. 678 * b, last record index to write into. 679 * a = first index to read (fri) + number of records in the table, 680 * b = a + @num - 1. 681 * Let N = control->ras_max_num_record_count, then we have, 682 * case 0: 0 <= a <= b < N, 683 * just append @num records starting at a; 684 * case 1: 0 <= a < N <= b, 685 * append (N - a) records starting at a, and 686 * append the remainder, b % N + 1, starting at 0. 687 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 688 * case 2a: 0 <= a <= b < N 689 * append num records starting at a; and fix fri if b overwrote it, 690 * and since a <= b, if b overwrote it then a must've also, 691 * and if b didn't overwrite it, then a didn't also. 692 * case 2b: 0 <= b < a < N 693 * write num records starting at a, which wraps around 0=N 694 * and overwrite fri unconditionally. Now from case 2a, 695 * this means that b eclipsed fri to overwrite it and wrap 696 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 697 * set fri = b + 1 (mod N). 698 * Now, since fri is updated in every case, except the trivial case 0, 699 * the number of records present in the table after writing, is, 700 * num_recs - 1 = b - fri (mod N), and we take the positive value, 701 * by adding an arbitrary multiple of N before taking the modulo N 702 * as shown below. 703 */ 704 a = control->ras_fri + control->ras_num_recs; 705 b = a + num - 1; 706 if (b < control->ras_max_record_count) { 707 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 708 } else if (a < control->ras_max_record_count) { 709 u32 g0, g1; 710 711 g0 = control->ras_max_record_count - a; 712 g1 = b % control->ras_max_record_count + 1; 713 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 714 if (res) 715 goto Out; 716 res = __amdgpu_ras_eeprom_write(control, 717 buf + g0 * RAS_TABLE_RECORD_SIZE, 718 0, g1); 719 if (res) 720 goto Out; 721 if (g1 > control->ras_fri) 722 control->ras_fri = g1 % control->ras_max_record_count; 723 } else { 724 a %= control->ras_max_record_count; 725 b %= control->ras_max_record_count; 726 727 if (a <= b) { 728 /* Note that, b - a + 1 = num. */ 729 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 730 if (res) 731 goto Out; 732 if (b >= control->ras_fri) 733 control->ras_fri = (b + 1) % control->ras_max_record_count; 734 } else { 735 u32 g0, g1; 736 737 /* b < a, which means, we write from 738 * a to the end of the table, and from 739 * the start of the table to b. 740 */ 741 g0 = control->ras_max_record_count - a; 742 g1 = b + 1; 743 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 744 if (res) 745 goto Out; 746 res = __amdgpu_ras_eeprom_write(control, 747 buf + g0 * RAS_TABLE_RECORD_SIZE, 748 0, g1); 749 if (res) 750 goto Out; 751 control->ras_fri = g1 % control->ras_max_record_count; 752 } 753 } 754 control->ras_num_recs = 1 + (control->ras_max_record_count + b 755 - control->ras_fri) 756 % control->ras_max_record_count; 757 758 /*old asics only save pa to eeprom like before*/ 759 control->ras_num_pa_recs += num; 760 761 control->ras_num_bad_pages = con->bad_page_num; 762 Out: 763 kfree(buf); 764 return res; 765 } 766 767 static int 768 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 769 { 770 struct amdgpu_device *adev = to_amdgpu_device(control); 771 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 772 u8 *buf, *pp, csum; 773 u32 buf_size; 774 int res; 775 776 /* Modify the header if it exceeds. 777 */ 778 if (amdgpu_bad_page_threshold != 0 && 779 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 780 dev_warn(adev->dev, 781 "Saved bad pages %d reaches threshold value %d\n", 782 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 783 784 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev) && 785 amdgpu_cper_generate_bp_threshold_record(adev)) 786 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 787 788 if ((amdgpu_bad_page_threshold != -1) && 789 (amdgpu_bad_page_threshold != -2)) { 790 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 791 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 792 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 793 control->tbl_rai.health_percent = 0; 794 } 795 ras->is_rma = true; 796 } 797 798 /* ignore the -ENOTSUPP return value */ 799 amdgpu_dpm_send_rma_reason(adev); 800 } 801 802 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 803 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 804 RAS_TABLE_V2_1_INFO_SIZE + 805 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 806 else 807 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 808 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 809 control->tbl_hdr.checksum = 0; 810 811 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 812 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 813 if (!buf) { 814 dev_err(adev->dev, 815 "allocating memory for table of size %d bytes failed\n", 816 control->tbl_hdr.tbl_size); 817 res = -ENOMEM; 818 goto Out; 819 } 820 821 down_read(&adev->reset_domain->sem); 822 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 823 control->i2c_address + 824 control->ras_record_offset, 825 buf, buf_size); 826 up_read(&adev->reset_domain->sem); 827 if (res < 0) { 828 dev_err(adev->dev, "EEPROM failed reading records:%d\n", res); 829 goto Out; 830 } else if (res < buf_size) { 831 dev_err(adev->dev, "EEPROM read %d out of %d bytes\n", res, 832 buf_size); 833 res = -EIO; 834 goto Out; 835 } 836 837 /** 838 * bad page records have been stored in eeprom, 839 * now calculate gpu health percent 840 */ 841 if (amdgpu_bad_page_threshold != 0 && 842 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 843 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) 844 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 845 control->ras_num_bad_pages) * 100) / 846 ras->bad_page_cnt_threshold; 847 848 /* Recalc the checksum. 849 */ 850 csum = 0; 851 for (pp = buf; pp < buf + buf_size; pp++) 852 csum += *pp; 853 854 csum += __calc_hdr_byte_sum(control); 855 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 856 csum += __calc_ras_info_byte_sum(control); 857 /* avoid sign extension when assigning to "checksum" */ 858 csum = -csum; 859 control->tbl_hdr.checksum = csum; 860 res = __write_table_header(control); 861 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 862 res = __write_table_ras_info(control); 863 Out: 864 kfree(buf); 865 return res; 866 } 867 868 /** 869 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 870 * @control: pointer to control structure 871 * @record: array of records to append 872 * @num: number of records in @record array 873 * 874 * Append @num records to the table, calculate the checksum and write 875 * the table back to EEPROM. The maximum number of records that 876 * can be appended is between 1 and control->ras_max_record_count, 877 * regardless of how many records are already stored in the table. 878 * 879 * Return 0 on success or if EEPROM is not supported, -errno on error. 880 */ 881 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 882 struct eeprom_table_record *record, 883 const u32 num) 884 { 885 struct amdgpu_device *adev = to_amdgpu_device(control); 886 int res, i; 887 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 888 889 if (!__is_ras_eeprom_supported(adev)) 890 return 0; 891 892 if (num == 0) { 893 dev_err(adev->dev, "will not append 0 records\n"); 894 return -EINVAL; 895 } else if (num > control->ras_max_record_count) { 896 dev_err(adev->dev, 897 "cannot append %d records than the size of table %d\n", 898 num, control->ras_max_record_count); 899 return -EINVAL; 900 } 901 902 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 903 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 904 905 /* set the new channel index flag */ 906 for (i = 0; i < num; i++) 907 record[i].retired_page |= (nps << UMC_NPS_SHIFT); 908 909 mutex_lock(&control->ras_tbl_mutex); 910 911 res = amdgpu_ras_eeprom_append_table(control, record, num); 912 if (!res) 913 res = amdgpu_ras_eeprom_update_header(control); 914 if (!res) 915 amdgpu_ras_debugfs_set_ret_size(control); 916 917 mutex_unlock(&control->ras_tbl_mutex); 918 919 /* clear channel index flag, the flag is only saved on eeprom */ 920 for (i = 0; i < num; i++) 921 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT); 922 923 return res; 924 } 925 926 /** 927 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 928 * @control: pointer to control structure 929 * @buf: pointer to buffer to read into 930 * @fri: first record index, start reading at this index, absolute index 931 * @num: number of records to read 932 * 933 * The caller must hold the table mutex in @control. 934 * Return 0 on success, -errno otherwise. 935 */ 936 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 937 u8 *buf, const u32 fri, const u32 num) 938 { 939 struct amdgpu_device *adev = to_amdgpu_device(control); 940 u32 buf_size; 941 int res; 942 943 /* i2c may be unstable in gpu reset */ 944 down_read(&adev->reset_domain->sem); 945 buf_size = num * RAS_TABLE_RECORD_SIZE; 946 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 947 control->i2c_address + 948 RAS_INDEX_TO_OFFSET(control, fri), 949 buf, buf_size); 950 up_read(&adev->reset_domain->sem); 951 if (res < 0) { 952 dev_err(adev->dev, "Reading %d EEPROM table records error:%d", 953 num, res); 954 } else if (res < buf_size) { 955 /* Short read, return error. 956 */ 957 dev_err(adev->dev, "Read %d records out of %d", 958 res / RAS_TABLE_RECORD_SIZE, num); 959 res = -EIO; 960 } else { 961 res = 0; 962 } 963 964 return res; 965 } 966 967 /** 968 * amdgpu_ras_eeprom_read -- read EEPROM 969 * @control: pointer to control structure 970 * @record: array of records to read into 971 * @num: number of records in @record 972 * 973 * Reads num records from the RAS table in EEPROM and 974 * writes the data into @record array. 975 * 976 * Returns 0 on success, -errno on error. 977 */ 978 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 979 struct eeprom_table_record *record, 980 const u32 num) 981 { 982 struct amdgpu_device *adev = to_amdgpu_device(control); 983 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 984 int i, res; 985 u8 *buf, *pp; 986 u32 g0, g1; 987 988 if (!__is_ras_eeprom_supported(adev)) 989 return 0; 990 991 if (num == 0) { 992 dev_err(adev->dev, "will not read 0 records\n"); 993 return -EINVAL; 994 } else if (num > control->ras_num_recs) { 995 dev_err(adev->dev, "too many records to read:%d available:%d\n", 996 num, control->ras_num_recs); 997 return -EINVAL; 998 } 999 1000 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 1001 if (!buf) 1002 return -ENOMEM; 1003 1004 /* Determine how many records to read, from the first record 1005 * index, fri, to the end of the table, and from the beginning 1006 * of the table, such that the total number of records is 1007 * @num, and we handle wrap around when fri > 0 and 1008 * fri + num > RAS_MAX_RECORD_COUNT. 1009 * 1010 * First we compute the index of the last element 1011 * which would be fetched from each region, 1012 * g0 is in [fri, fri + num - 1], and 1013 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 1014 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 1015 * the last element to fetch, we set g0 to _the number_ 1016 * of elements to fetch, @num, since we know that the last 1017 * indexed to be fetched does not exceed the table. 1018 * 1019 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 1020 * we set g0 to the number of elements to read 1021 * until the end of the table, and g1 to the number of 1022 * elements to read from the beginning of the table. 1023 */ 1024 g0 = control->ras_fri + num - 1; 1025 g1 = g0 % control->ras_max_record_count; 1026 if (g0 < control->ras_max_record_count) { 1027 g0 = num; 1028 g1 = 0; 1029 } else { 1030 g0 = control->ras_max_record_count - control->ras_fri; 1031 g1 += 1; 1032 } 1033 1034 mutex_lock(&control->ras_tbl_mutex); 1035 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 1036 if (res) 1037 goto Out; 1038 if (g1) { 1039 res = __amdgpu_ras_eeprom_read(control, 1040 buf + g0 * RAS_TABLE_RECORD_SIZE, 1041 0, g1); 1042 if (res) 1043 goto Out; 1044 } 1045 1046 res = 0; 1047 1048 /* Read up everything? Then transform. 1049 */ 1050 pp = buf; 1051 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 1052 __decode_table_record_from_buf(control, &record[i], pp); 1053 1054 /* update bad channel bitmap */ 1055 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 1056 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 1057 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 1058 con->update_channel_flag = true; 1059 } 1060 } 1061 Out: 1062 kfree(buf); 1063 mutex_unlock(&control->ras_tbl_mutex); 1064 1065 return res; 1066 } 1067 1068 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1069 { 1070 /* get available eeprom table version first before eeprom table init */ 1071 amdgpu_ras_set_eeprom_table_version(control); 1072 1073 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1074 return RAS_MAX_RECORD_COUNT_V2_1; 1075 else 1076 return RAS_MAX_RECORD_COUNT; 1077 } 1078 1079 static ssize_t 1080 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1081 size_t size, loff_t *pos) 1082 { 1083 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1084 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1085 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1086 u8 data[50]; 1087 int res; 1088 1089 if (!size) 1090 return size; 1091 1092 if (!ras || !control) { 1093 res = snprintf(data, sizeof(data), "Not supported\n"); 1094 } else { 1095 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1096 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1097 } 1098 1099 if (*pos >= res) 1100 return 0; 1101 1102 res -= *pos; 1103 res = min_t(size_t, res, size); 1104 1105 if (copy_to_user(buf, &data[*pos], res)) 1106 return -EFAULT; 1107 1108 *pos += res; 1109 1110 return res; 1111 } 1112 1113 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1114 .owner = THIS_MODULE, 1115 .read = amdgpu_ras_debugfs_eeprom_size_read, 1116 .write = NULL, 1117 .llseek = default_llseek, 1118 }; 1119 1120 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1121 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1122 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1123 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1124 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1125 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1126 1127 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1128 "ignore", 1129 "re", 1130 "ue", 1131 }; 1132 1133 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1134 { 1135 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1136 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1137 } 1138 1139 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1140 { 1141 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1142 eeprom_control); 1143 struct dentry *de = ras->de_ras_eeprom_table; 1144 1145 if (de) 1146 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1147 } 1148 1149 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1150 size_t size, loff_t *pos) 1151 { 1152 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1153 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1154 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1155 const size_t orig_size = size; 1156 int res = -EFAULT; 1157 size_t data_len; 1158 1159 mutex_lock(&control->ras_tbl_mutex); 1160 1161 /* We want *pos - data_len > 0, which means there's 1162 * bytes to be printed from data. 1163 */ 1164 data_len = strlen(tbl_hdr_str); 1165 if (*pos < data_len) { 1166 data_len -= *pos; 1167 data_len = min_t(size_t, data_len, size); 1168 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1169 goto Out; 1170 buf += data_len; 1171 size -= data_len; 1172 *pos += data_len; 1173 } 1174 1175 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1176 if (*pos < data_len && size > 0) { 1177 u8 data[tbl_hdr_fmt_size + 1]; 1178 loff_t lpos; 1179 1180 snprintf(data, sizeof(data), tbl_hdr_fmt, 1181 control->tbl_hdr.header, 1182 control->tbl_hdr.version, 1183 control->tbl_hdr.first_rec_offset, 1184 control->tbl_hdr.tbl_size, 1185 control->tbl_hdr.checksum); 1186 1187 data_len -= *pos; 1188 data_len = min_t(size_t, data_len, size); 1189 lpos = *pos - strlen(tbl_hdr_str); 1190 if (copy_to_user(buf, &data[lpos], data_len)) 1191 goto Out; 1192 buf += data_len; 1193 size -= data_len; 1194 *pos += data_len; 1195 } 1196 1197 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1198 if (*pos < data_len && size > 0) { 1199 loff_t lpos; 1200 1201 data_len -= *pos; 1202 data_len = min_t(size_t, data_len, size); 1203 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1204 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1205 goto Out; 1206 buf += data_len; 1207 size -= data_len; 1208 *pos += data_len; 1209 } 1210 1211 data_len = amdgpu_ras_debugfs_table_size(control); 1212 if (*pos < data_len && size > 0) { 1213 u8 dare[RAS_TABLE_RECORD_SIZE]; 1214 u8 data[rec_hdr_fmt_size + 1]; 1215 struct eeprom_table_record record; 1216 int s, r; 1217 1218 /* Find the starting record index 1219 */ 1220 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1221 strlen(rec_hdr_str); 1222 s = s / rec_hdr_fmt_size; 1223 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1224 strlen(rec_hdr_str); 1225 r = r % rec_hdr_fmt_size; 1226 1227 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1228 u32 ai = RAS_RI_TO_AI(control, s); 1229 /* Read a single record 1230 */ 1231 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1232 if (res) 1233 goto Out; 1234 __decode_table_record_from_buf(control, &record, dare); 1235 snprintf(data, sizeof(data), rec_hdr_fmt, 1236 s, 1237 RAS_INDEX_TO_OFFSET(control, ai), 1238 record_err_type_str[record.err_type], 1239 record.bank, 1240 record.ts, 1241 record.offset, 1242 record.mem_channel, 1243 record.mcumc_id, 1244 record.retired_page); 1245 1246 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1247 if (copy_to_user(buf, &data[r], data_len)) { 1248 res = -EFAULT; 1249 goto Out; 1250 } 1251 buf += data_len; 1252 size -= data_len; 1253 *pos += data_len; 1254 r = 0; 1255 } 1256 } 1257 res = 0; 1258 Out: 1259 mutex_unlock(&control->ras_tbl_mutex); 1260 return res < 0 ? res : orig_size - size; 1261 } 1262 1263 static ssize_t 1264 amdgpu_ras_debugfs_table_read_uniras(struct amdgpu_device *adev, 1265 char __user *buf, 1266 size_t size, loff_t *pos) 1267 { 1268 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 1269 struct ras_core_context *ras_core = ras_mgr ? ras_mgr->ras_core : NULL; 1270 struct eeprom_umc_record *records = NULL; 1271 struct ras_eeprom_control *control; 1272 size_t bufsz, len = 0; 1273 u32 num_recs; 1274 char *kbuf; 1275 ssize_t res; 1276 int i; 1277 1278 if (!ras_core) 1279 return 0; 1280 1281 /* pmfw manages eeprom data by itself */ 1282 if (ras_fw_eeprom_supported(ras_core)) 1283 return 0; 1284 1285 control = &ras_core->ras_eeprom; 1286 num_recs = ras_eeprom_get_record_count(ras_core); 1287 1288 bufsz = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1289 strlen(rec_hdr_str) + (size_t)rec_hdr_fmt_size * num_recs + 1; 1290 1291 kbuf = kvmalloc(bufsz, GFP_KERNEL); 1292 if (!kbuf) 1293 return -ENOMEM; 1294 1295 if (num_recs) { 1296 records = kvcalloc(num_recs, sizeof(*records), GFP_KERNEL); 1297 if (!records) { 1298 res = -ENOMEM; 1299 goto out; 1300 } 1301 1302 res = ras_eeprom_read(ras_core, records, num_recs); 1303 if (res) 1304 goto out; 1305 } 1306 1307 len += scnprintf(kbuf + len, bufsz - len, "%s", tbl_hdr_str); 1308 len += scnprintf(kbuf + len, bufsz - len, tbl_hdr_fmt, 1309 control->tbl_hdr.header, 1310 control->tbl_hdr.version, 1311 control->tbl_hdr.first_rec_offset, 1312 control->tbl_hdr.tbl_size, 1313 control->tbl_hdr.checksum); 1314 len += scnprintf(kbuf + len, bufsz - len, "%s", rec_hdr_str); 1315 1316 for (i = 0; i < num_recs; i++) { 1317 u32 ai = RAS_RI_TO_AI(control, i); 1318 int et = records[i].err_type; 1319 const char *ets = (et >= 0 && et < AMDGPU_RAS_EEPROM_ERR_COUNT) ? 1320 record_err_type_str[et] : "na"; 1321 1322 len += scnprintf(kbuf + len, bufsz - len, rec_hdr_fmt, 1323 i, 1324 RAS_INDEX_TO_OFFSET(control, ai), 1325 ets, 1326 records[i].bank, 1327 records[i].ts, 1328 records[i].offset, 1329 records[i].mem_channel, 1330 records[i].mcumc_id, 1331 records[i].retired_row_pfn); 1332 } 1333 1334 res = simple_read_from_buffer(buf, size, pos, kbuf, len); 1335 1336 out: 1337 kvfree(records); 1338 kvfree(kbuf); 1339 1340 return res; 1341 } 1342 1343 static ssize_t 1344 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1345 size_t size, loff_t *pos) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1348 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1349 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1350 u8 data[81]; 1351 int res; 1352 1353 if (!size) 1354 return size; 1355 1356 if (amdgpu_uniras_enabled(adev)) 1357 return amdgpu_ras_debugfs_table_read_uniras(adev, buf, 1358 size, pos); 1359 1360 if (!ras || !control) { 1361 res = snprintf(data, sizeof(data), "Not supported\n"); 1362 if (*pos >= res) 1363 return 0; 1364 1365 res -= *pos; 1366 res = min_t(size_t, res, size); 1367 1368 if (copy_to_user(buf, &data[*pos], res)) 1369 return -EFAULT; 1370 1371 *pos += res; 1372 1373 return res; 1374 } else { 1375 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1376 } 1377 } 1378 1379 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1380 .owner = THIS_MODULE, 1381 .read = amdgpu_ras_debugfs_eeprom_table_read, 1382 .write = NULL, 1383 .llseek = default_llseek, 1384 }; 1385 1386 /** 1387 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1388 * @control: pointer to control structure 1389 * 1390 * Check the checksum of the stored in EEPROM RAS table. 1391 * 1392 * Return 0 if the checksum is correct, 1393 * positive if it is not correct, and 1394 * -errno on I/O error. 1395 */ 1396 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1397 { 1398 struct amdgpu_device *adev = to_amdgpu_device(control); 1399 int buf_size, res; 1400 u8 csum, *buf, *pp; 1401 1402 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1403 buf_size = RAS_TABLE_HEADER_SIZE + 1404 RAS_TABLE_V2_1_INFO_SIZE + 1405 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1406 else 1407 buf_size = RAS_TABLE_HEADER_SIZE + 1408 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1409 1410 buf = kzalloc(buf_size, GFP_KERNEL); 1411 if (!buf) { 1412 dev_err(adev->dev, 1413 "Out of memory checking RAS table checksum.\n"); 1414 return -ENOMEM; 1415 } 1416 1417 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1418 control->i2c_address + 1419 control->ras_header_offset, 1420 buf, buf_size); 1421 if (res < buf_size) { 1422 dev_err(adev->dev, "Partial read for checksum, res:%d\n", res); 1423 /* On partial reads, return -EIO. 1424 */ 1425 if (res >= 0) 1426 res = -EIO; 1427 goto Out; 1428 } 1429 1430 csum = 0; 1431 for (pp = buf; pp < buf + buf_size; pp++) 1432 csum += *pp; 1433 Out: 1434 kfree(buf); 1435 return res < 0 ? res : csum; 1436 } 1437 1438 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1439 { 1440 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1441 struct amdgpu_device *adev = to_amdgpu_device(control); 1442 unsigned char *buf; 1443 int res; 1444 1445 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1446 if (!buf) { 1447 dev_err(adev->dev, 1448 "Failed to alloc buf to read EEPROM table ras info\n"); 1449 return -ENOMEM; 1450 } 1451 1452 /** 1453 * EEPROM table V2_1 supports ras info, 1454 * read EEPROM table ras info 1455 */ 1456 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1457 control->i2c_address + control->ras_info_offset, 1458 buf, RAS_TABLE_V2_1_INFO_SIZE); 1459 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1460 dev_err(adev->dev, 1461 "Failed to read EEPROM table ras info, res:%d", res); 1462 res = res >= 0 ? -EIO : res; 1463 goto Out; 1464 } 1465 1466 __decode_table_ras_info_from_buf(rai, buf); 1467 1468 Out: 1469 kfree(buf); 1470 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1471 } 1472 1473 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1474 { 1475 struct amdgpu_device *adev = to_amdgpu_device(control); 1476 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1477 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1478 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1479 int dev_var = adev->pdev->device & 0xF; 1480 uint32_t vram_type = adev->gmc.vram_type; 1481 int res; 1482 1483 ras->is_rma = false; 1484 1485 if (!__is_ras_eeprom_supported(adev)) 1486 return 0; 1487 1488 /* Verify i2c adapter is initialized */ 1489 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1490 return -ENOENT; 1491 1492 if (!__get_eeprom_i2c_addr(adev, control)) 1493 return -EINVAL; 1494 1495 control->ras_header_offset = RAS_HDR_START; 1496 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1497 mutex_init(&control->ras_tbl_mutex); 1498 1499 /* Read the table header from EEPROM address */ 1500 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1501 control->i2c_address + control->ras_header_offset, 1502 buf, RAS_TABLE_HEADER_SIZE); 1503 if (res < RAS_TABLE_HEADER_SIZE) { 1504 dev_err(adev->dev, "Failed to read EEPROM table header, res:%d", 1505 res); 1506 return res >= 0 ? -EIO : res; 1507 } 1508 1509 __decode_table_header_from_buf(hdr, buf); 1510 1511 if (hdr->header != RAS_TABLE_HDR_VAL && 1512 hdr->header != RAS_TABLE_HDR_BAD) { 1513 dev_info(adev->dev, "Creating a new EEPROM table"); 1514 return amdgpu_ras_eeprom_reset_table(control); 1515 } 1516 1517 if (!(adev->flags & AMD_IS_APU) && (dev_var == 0x5) && 1518 (vram_type == AMDGPU_VRAM_TYPE_HBM3E) && 1519 (hdr->version < RAS_TABLE_VER_V3)) { 1520 return amdgpu_ras_eeprom_reset_table(control); 1521 } 1522 1523 switch (hdr->version) { 1524 case RAS_TABLE_VER_V2_1: 1525 case RAS_TABLE_VER_V3: 1526 if (hdr->tbl_size < RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE) { 1527 dev_err(adev->dev, 1528 "RAS header invalid, tbl_size %u smaller than minimum %u, resetting table\n", 1529 hdr->tbl_size, 1530 RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE); 1531 return amdgpu_ras_eeprom_reset_table(control); 1532 } 1533 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1534 control->ras_record_offset = RAS_RECORD_START_V2_1; 1535 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1536 break; 1537 case RAS_TABLE_VER_V1: 1538 if (hdr->tbl_size < RAS_TABLE_HEADER_SIZE) { 1539 dev_err(adev->dev, 1540 "RAS header invalid, tbl_size %u smaller than minimum %u, resetting table\n", 1541 hdr->tbl_size, RAS_TABLE_HEADER_SIZE); 1542 return amdgpu_ras_eeprom_reset_table(control); 1543 } 1544 control->ras_num_recs = RAS_NUM_RECS(hdr); 1545 control->ras_record_offset = RAS_RECORD_START; 1546 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1547 break; 1548 default: 1549 dev_err(adev->dev, 1550 "RAS header invalid, unsupported version: %u", 1551 hdr->version); 1552 return -EINVAL; 1553 } 1554 1555 if (control->ras_num_recs > control->ras_max_record_count) { 1556 dev_err(adev->dev, 1557 "RAS header invalid, records in header: %u max allowed :%u", 1558 control->ras_num_recs, control->ras_max_record_count); 1559 return -EINVAL; 1560 } 1561 1562 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1563 if (hdr->first_rec_offset < control->ras_record_offset || 1564 control->ras_fri >= control->ras_max_record_count) { 1565 dev_err(adev->dev, 1566 "RAS header invalid, ras_fri: %u, first_rec_offset:0x%x", 1567 control->ras_fri, hdr->first_rec_offset); 1568 return -EINVAL; 1569 } 1570 1571 control->ras_num_mca_recs = 0; 1572 control->ras_num_pa_recs = 0; 1573 return 0; 1574 } 1575 1576 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1577 { 1578 struct amdgpu_device *adev = to_amdgpu_device(control); 1579 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1580 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1581 int res = 0; 1582 1583 if (!__is_ras_eeprom_supported(adev)) 1584 return 0; 1585 1586 /* Verify i2c adapter is initialized */ 1587 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1588 return -ENOENT; 1589 1590 if (!__get_eeprom_i2c_addr(adev, control)) 1591 return -EINVAL; 1592 1593 control->ras_num_bad_pages = ras->bad_page_num; 1594 1595 if (hdr->header == RAS_TABLE_HDR_VAL) { 1596 dev_dbg(adev->dev, 1597 "Found existing EEPROM table with %d records", 1598 control->ras_num_bad_pages); 1599 1600 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1601 res = __read_table_ras_info(control); 1602 if (res) 1603 return res; 1604 } 1605 1606 res = __verify_ras_table_checksum(control); 1607 if (res) { 1608 dev_err(adev->dev, 1609 "RAS table incorrect checksum or error:%d\n", 1610 res); 1611 return -EINVAL; 1612 } 1613 1614 /* Warn if we are at 90% of the threshold or above 1615 */ 1616 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1617 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1618 control->ras_num_bad_pages, 1619 ras->bad_page_cnt_threshold); 1620 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1621 amdgpu_bad_page_threshold != 0) { 1622 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1623 res = __read_table_ras_info(control); 1624 if (res) 1625 return res; 1626 } 1627 1628 res = __verify_ras_table_checksum(control); 1629 if (res) { 1630 dev_err(adev->dev, 1631 "RAS Table incorrect checksum or error:%d\n", 1632 res); 1633 return -EINVAL; 1634 } 1635 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { 1636 /* This means that, the threshold was increased since 1637 * the last time the system was booted, and now, 1638 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1639 * so that at least one more record can be saved, 1640 * before the page count threshold is reached. 1641 */ 1642 dev_info(adev->dev, 1643 "records:%d threshold:%d, resetting " 1644 "RAS table header signature", 1645 control->ras_num_bad_pages, 1646 ras->bad_page_cnt_threshold); 1647 res = amdgpu_ras_eeprom_correct_header_tag(control, 1648 RAS_TABLE_HDR_VAL); 1649 } else { 1650 dev_warn(adev->dev, 1651 "RAS records:%d exceed threshold:%d\n", 1652 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1653 if ((amdgpu_bad_page_threshold == -1) || 1654 (amdgpu_bad_page_threshold == -2)) { 1655 res = 0; 1656 dev_warn(adev->dev, 1657 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1658 } else { 1659 ras->is_rma = true; 1660 dev_warn(adev->dev, 1661 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1662 } 1663 } 1664 } 1665 1666 return res < 0 ? res : 0; 1667 } 1668 1669 void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev) 1670 { 1671 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1672 struct amdgpu_ras_eeprom_control *control; 1673 int res; 1674 1675 if (!__is_ras_eeprom_supported(adev) || !ras) 1676 return; 1677 control = &ras->eeprom_control; 1678 if (!control->is_eeprom_valid) 1679 return; 1680 res = __verify_ras_table_checksum(control); 1681 if (res) { 1682 dev_warn(adev->dev, 1683 "RAS table incorrect checksum or error:%d, try to recover\n", 1684 res); 1685 if (!amdgpu_ras_eeprom_reset_table(control)) 1686 if (!amdgpu_ras_save_bad_pages(adev, NULL)) 1687 if (!__verify_ras_table_checksum(control)) { 1688 dev_info(adev->dev, "RAS table recovery succeed\n"); 1689 return; 1690 } 1691 dev_err(adev->dev, "RAS table recovery failed\n"); 1692 control->is_eeprom_valid = false; 1693 } 1694 return; 1695 } 1696 1697 void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) 1698 { 1699 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1700 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1701 1702 if (!__is_ras_eeprom_supported(adev) || !control || amdgpu_bad_page_threshold == 0) 1703 return; 1704 1705 if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { 1706 if (amdgpu_dpm_send_rma_reason(adev)) 1707 dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); 1708 else 1709 dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); 1710 1711 if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { 1712 if (amdgpu_cper_generate_bp_threshold_record(adev)) 1713 dev_warn(adev->dev, "Unable to send in-band RMA CPER"); 1714 else 1715 dev_dbg(adev->dev, "Sent in-band RMA CPER"); 1716 } 1717 } 1718 } 1719