1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 10): 162 return true; 163 case IP_VERSION(13, 0, 6): 164 return (adev->gmc.is_app_apu) ? false : true; 165 default: 166 return false; 167 } 168 } 169 170 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 171 struct amdgpu_ras_eeprom_control *control) 172 { 173 struct atom_context *atom_ctx = adev->mode_info.atom_context; 174 u8 i2c_addr; 175 176 if (!control) 177 return false; 178 179 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 180 /* The address given by VBIOS is an 8-bit, wire-format 181 * address, i.e. the most significant byte. 182 * 183 * Normalize it to a 19-bit EEPROM address. Remove the 184 * device type identifier and make it a 7-bit address; 185 * then make it a 19-bit EEPROM address. See top of 186 * amdgpu_eeprom.c. 187 */ 188 i2c_addr = (i2c_addr & 0x0F) >> 1; 189 control->i2c_address = ((u32) i2c_addr) << 16; 190 191 return true; 192 } 193 194 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 195 case IP_VERSION(11, 0, 2): 196 /* VEGA20 and ARCTURUS */ 197 if (adev->asic_type == CHIP_VEGA20) 198 control->i2c_address = EEPROM_I2C_MADDR_0; 199 else if (strnstr(atom_ctx->vbios_pn, 200 "D342", 201 sizeof(atom_ctx->vbios_pn))) 202 control->i2c_address = EEPROM_I2C_MADDR_0; 203 else 204 control->i2c_address = EEPROM_I2C_MADDR_4; 205 return true; 206 case IP_VERSION(11, 0, 7): 207 control->i2c_address = EEPROM_I2C_MADDR_0; 208 return true; 209 case IP_VERSION(13, 0, 2): 210 if (strnstr(atom_ctx->vbios_pn, "D673", 211 sizeof(atom_ctx->vbios_pn))) 212 control->i2c_address = EEPROM_I2C_MADDR_4; 213 else 214 control->i2c_address = EEPROM_I2C_MADDR_0; 215 return true; 216 case IP_VERSION(13, 0, 0): 217 if (strnstr(atom_ctx->vbios_pn, "D707", 218 sizeof(atom_ctx->vbios_pn))) 219 control->i2c_address = EEPROM_I2C_MADDR_0; 220 else 221 control->i2c_address = EEPROM_I2C_MADDR_4; 222 return true; 223 case IP_VERSION(13, 0, 6): 224 case IP_VERSION(13, 0, 10): 225 control->i2c_address = EEPROM_I2C_MADDR_4; 226 return true; 227 default: 228 return false; 229 } 230 } 231 232 static void 233 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 234 unsigned char *buf) 235 { 236 u32 *pp = (uint32_t *)buf; 237 238 pp[0] = cpu_to_le32(hdr->header); 239 pp[1] = cpu_to_le32(hdr->version); 240 pp[2] = cpu_to_le32(hdr->first_rec_offset); 241 pp[3] = cpu_to_le32(hdr->tbl_size); 242 pp[4] = cpu_to_le32(hdr->checksum); 243 } 244 245 static void 246 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 247 unsigned char *buf) 248 { 249 u32 *pp = (uint32_t *)buf; 250 251 hdr->header = le32_to_cpu(pp[0]); 252 hdr->version = le32_to_cpu(pp[1]); 253 hdr->first_rec_offset = le32_to_cpu(pp[2]); 254 hdr->tbl_size = le32_to_cpu(pp[3]); 255 hdr->checksum = le32_to_cpu(pp[4]); 256 } 257 258 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 259 { 260 u8 buf[RAS_TABLE_HEADER_SIZE]; 261 struct amdgpu_device *adev = to_amdgpu_device(control); 262 int res; 263 264 memset(buf, 0, sizeof(buf)); 265 __encode_table_header_to_buf(&control->tbl_hdr, buf); 266 267 /* i2c may be unstable in gpu reset */ 268 down_read(&adev->reset_domain->sem); 269 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 270 control->i2c_address + 271 control->ras_header_offset, 272 buf, RAS_TABLE_HEADER_SIZE); 273 up_read(&adev->reset_domain->sem); 274 275 if (res < 0) { 276 DRM_ERROR("Failed to write EEPROM table header:%d", res); 277 } else if (res < RAS_TABLE_HEADER_SIZE) { 278 DRM_ERROR("Short write:%d out of %d\n", 279 res, RAS_TABLE_HEADER_SIZE); 280 res = -EIO; 281 } else { 282 res = 0; 283 } 284 285 return res; 286 } 287 288 static void 289 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 290 unsigned char *buf) 291 { 292 u32 *pp = (uint32_t *)buf; 293 u32 tmp; 294 295 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 296 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 297 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 298 pp[0] = cpu_to_le32(tmp); 299 } 300 301 static void 302 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 303 unsigned char *buf) 304 { 305 u32 *pp = (uint32_t *)buf; 306 u32 tmp; 307 308 tmp = le32_to_cpu(pp[0]); 309 rai->rma_status = tmp & 0xFF; 310 rai->health_percent = (tmp >> 8) & 0xFF; 311 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 312 } 313 314 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 315 { 316 struct amdgpu_device *adev = to_amdgpu_device(control); 317 u8 *buf; 318 int res; 319 320 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 321 if (!buf) { 322 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 323 return -ENOMEM; 324 } 325 326 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 327 328 /* i2c may be unstable in gpu reset */ 329 down_read(&adev->reset_domain->sem); 330 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 331 control->i2c_address + 332 control->ras_info_offset, 333 buf, RAS_TABLE_V2_1_INFO_SIZE); 334 up_read(&adev->reset_domain->sem); 335 336 if (res < 0) { 337 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 338 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 339 DRM_ERROR("Short write:%d out of %d\n", 340 res, RAS_TABLE_V2_1_INFO_SIZE); 341 res = -EIO; 342 } else { 343 res = 0; 344 } 345 346 kfree(buf); 347 348 return res; 349 } 350 351 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 352 { 353 int ii; 354 u8 *pp, csum; 355 size_t sz; 356 357 /* Header checksum, skip checksum field in the calculation */ 358 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 359 pp = (u8 *) &control->tbl_hdr; 360 csum = 0; 361 for (ii = 0; ii < sz; ii++, pp++) 362 csum += *pp; 363 364 return csum; 365 } 366 367 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 368 { 369 int ii; 370 u8 *pp, csum; 371 size_t sz; 372 373 sz = sizeof(control->tbl_rai); 374 pp = (u8 *) &control->tbl_rai; 375 csum = 0; 376 for (ii = 0; ii < sz; ii++, pp++) 377 csum += *pp; 378 379 return csum; 380 } 381 382 static int amdgpu_ras_eeprom_correct_header_tag( 383 struct amdgpu_ras_eeprom_control *control, 384 uint32_t header) 385 { 386 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 387 u8 *hh; 388 int res; 389 u8 csum; 390 391 csum = -hdr->checksum; 392 393 hh = (void *) &hdr->header; 394 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 395 hh = (void *) &header; 396 csum += hh[0] + hh[1] + hh[2] + hh[3]; 397 csum = -csum; 398 mutex_lock(&control->ras_tbl_mutex); 399 hdr->header = header; 400 hdr->checksum = csum; 401 res = __write_table_header(control); 402 mutex_unlock(&control->ras_tbl_mutex); 403 404 return res; 405 } 406 407 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 408 { 409 struct amdgpu_device *adev = to_amdgpu_device(control); 410 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 411 412 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 413 case IP_VERSION(8, 10, 0): 414 case IP_VERSION(12, 0, 0): 415 hdr->version = RAS_TABLE_VER_V2_1; 416 return; 417 default: 418 hdr->version = RAS_TABLE_VER_V1; 419 return; 420 } 421 } 422 423 /** 424 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 425 * @control: pointer to control structure 426 * 427 * Reset the contents of the header of the RAS EEPROM table. 428 * Return 0 on success, -errno on error. 429 */ 430 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 431 { 432 struct amdgpu_device *adev = to_amdgpu_device(control); 433 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 434 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 435 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 436 u8 csum; 437 int res; 438 439 mutex_lock(&control->ras_tbl_mutex); 440 441 hdr->header = RAS_TABLE_HDR_VAL; 442 amdgpu_ras_set_eeprom_table_version(control); 443 444 if (hdr->version == RAS_TABLE_VER_V2_1) { 445 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 446 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 447 RAS_TABLE_V2_1_INFO_SIZE; 448 rai->rma_status = GPU_HEALTH_USABLE; 449 /** 450 * GPU health represented as a percentage. 451 * 0 means worst health, 100 means fully health. 452 */ 453 rai->health_percent = 100; 454 /* ecc_page_threshold = 0 means disable bad page retirement */ 455 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 456 } else { 457 hdr->first_rec_offset = RAS_RECORD_START; 458 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 459 } 460 461 csum = __calc_hdr_byte_sum(control); 462 if (hdr->version == RAS_TABLE_VER_V2_1) 463 csum += __calc_ras_info_byte_sum(control); 464 csum = -csum; 465 hdr->checksum = csum; 466 res = __write_table_header(control); 467 if (!res && hdr->version > RAS_TABLE_VER_V1) 468 res = __write_table_ras_info(control); 469 470 control->ras_num_recs = 0; 471 control->ras_fri = 0; 472 473 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 474 475 control->bad_channel_bitmap = 0; 476 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 477 con->update_channel_flag = false; 478 479 amdgpu_ras_debugfs_set_ret_size(control); 480 481 mutex_unlock(&control->ras_tbl_mutex); 482 483 return res; 484 } 485 486 static void 487 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 488 struct eeprom_table_record *record, 489 unsigned char *buf) 490 { 491 __le64 tmp = 0; 492 int i = 0; 493 494 /* Next are all record fields according to EEPROM page spec in LE foramt */ 495 buf[i++] = record->err_type; 496 497 buf[i++] = record->bank; 498 499 tmp = cpu_to_le64(record->ts); 500 memcpy(buf + i, &tmp, 8); 501 i += 8; 502 503 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 504 memcpy(buf + i, &tmp, 6); 505 i += 6; 506 507 buf[i++] = record->mem_channel; 508 buf[i++] = record->mcumc_id; 509 510 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 511 memcpy(buf + i, &tmp, 6); 512 } 513 514 static void 515 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 516 struct eeprom_table_record *record, 517 unsigned char *buf) 518 { 519 __le64 tmp = 0; 520 int i = 0; 521 522 /* Next are all record fields according to EEPROM page spec in LE foramt */ 523 record->err_type = buf[i++]; 524 525 record->bank = buf[i++]; 526 527 memcpy(&tmp, buf + i, 8); 528 record->ts = le64_to_cpu(tmp); 529 i += 8; 530 531 memcpy(&tmp, buf + i, 6); 532 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 533 i += 6; 534 535 record->mem_channel = buf[i++]; 536 record->mcumc_id = buf[i++]; 537 538 memcpy(&tmp, buf + i, 6); 539 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 540 } 541 542 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 543 { 544 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 545 546 if (!__is_ras_eeprom_supported(adev) || 547 !amdgpu_bad_page_threshold) 548 return false; 549 550 /* skip check eeprom table for VEGA20 Gaming */ 551 if (!con) 552 return false; 553 else 554 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 555 return false; 556 557 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 558 if (amdgpu_bad_page_threshold == -1) { 559 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 560 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold); 561 dev_warn(adev->dev, 562 "But GPU can be operated due to bad_page_threshold = -1.\n"); 563 return false; 564 } else { 565 dev_warn(adev->dev, "This GPU is in BAD status."); 566 dev_warn(adev->dev, "Please retire it or set a larger " 567 "threshold value when reloading driver.\n"); 568 return true; 569 } 570 } 571 572 return false; 573 } 574 575 /** 576 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 577 * @control: pointer to control structure 578 * @buf: pointer to buffer containing data to write 579 * @fri: start writing at this index 580 * @num: number of records to write 581 * 582 * The caller must hold the table mutex in @control. 583 * Return 0 on success, -errno otherwise. 584 */ 585 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 586 u8 *buf, const u32 fri, const u32 num) 587 { 588 struct amdgpu_device *adev = to_amdgpu_device(control); 589 u32 buf_size; 590 int res; 591 592 /* i2c may be unstable in gpu reset */ 593 down_read(&adev->reset_domain->sem); 594 buf_size = num * RAS_TABLE_RECORD_SIZE; 595 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 596 control->i2c_address + 597 RAS_INDEX_TO_OFFSET(control, fri), 598 buf, buf_size); 599 up_read(&adev->reset_domain->sem); 600 if (res < 0) { 601 DRM_ERROR("Writing %d EEPROM table records error:%d", 602 num, res); 603 } else if (res < buf_size) { 604 /* Short write, return error. 605 */ 606 DRM_ERROR("Wrote %d records out of %d", 607 res / RAS_TABLE_RECORD_SIZE, num); 608 res = -EIO; 609 } else { 610 res = 0; 611 } 612 613 return res; 614 } 615 616 static int 617 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 618 struct eeprom_table_record *record, 619 const u32 num) 620 { 621 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 622 u32 a, b, i; 623 u8 *buf, *pp; 624 int res; 625 626 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 627 if (!buf) 628 return -ENOMEM; 629 630 /* Encode all of them in one go. 631 */ 632 pp = buf; 633 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 634 __encode_table_record_to_buf(control, &record[i], pp); 635 636 /* update bad channel bitmap */ 637 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 638 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 639 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 640 con->update_channel_flag = true; 641 } 642 } 643 644 /* a, first record index to write into. 645 * b, last record index to write into. 646 * a = first index to read (fri) + number of records in the table, 647 * b = a + @num - 1. 648 * Let N = control->ras_max_num_record_count, then we have, 649 * case 0: 0 <= a <= b < N, 650 * just append @num records starting at a; 651 * case 1: 0 <= a < N <= b, 652 * append (N - a) records starting at a, and 653 * append the remainder, b % N + 1, starting at 0. 654 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 655 * case 2a: 0 <= a <= b < N 656 * append num records starting at a; and fix fri if b overwrote it, 657 * and since a <= b, if b overwrote it then a must've also, 658 * and if b didn't overwrite it, then a didn't also. 659 * case 2b: 0 <= b < a < N 660 * write num records starting at a, which wraps around 0=N 661 * and overwrite fri unconditionally. Now from case 2a, 662 * this means that b eclipsed fri to overwrite it and wrap 663 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 664 * set fri = b + 1 (mod N). 665 * Now, since fri is updated in every case, except the trivial case 0, 666 * the number of records present in the table after writing, is, 667 * num_recs - 1 = b - fri (mod N), and we take the positive value, 668 * by adding an arbitrary multiple of N before taking the modulo N 669 * as shown below. 670 */ 671 a = control->ras_fri + control->ras_num_recs; 672 b = a + num - 1; 673 if (b < control->ras_max_record_count) { 674 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 675 } else if (a < control->ras_max_record_count) { 676 u32 g0, g1; 677 678 g0 = control->ras_max_record_count - a; 679 g1 = b % control->ras_max_record_count + 1; 680 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 681 if (res) 682 goto Out; 683 res = __amdgpu_ras_eeprom_write(control, 684 buf + g0 * RAS_TABLE_RECORD_SIZE, 685 0, g1); 686 if (res) 687 goto Out; 688 if (g1 > control->ras_fri) 689 control->ras_fri = g1 % control->ras_max_record_count; 690 } else { 691 a %= control->ras_max_record_count; 692 b %= control->ras_max_record_count; 693 694 if (a <= b) { 695 /* Note that, b - a + 1 = num. */ 696 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 697 if (res) 698 goto Out; 699 if (b >= control->ras_fri) 700 control->ras_fri = (b + 1) % control->ras_max_record_count; 701 } else { 702 u32 g0, g1; 703 704 /* b < a, which means, we write from 705 * a to the end of the table, and from 706 * the start of the table to b. 707 */ 708 g0 = control->ras_max_record_count - a; 709 g1 = b + 1; 710 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 711 if (res) 712 goto Out; 713 res = __amdgpu_ras_eeprom_write(control, 714 buf + g0 * RAS_TABLE_RECORD_SIZE, 715 0, g1); 716 if (res) 717 goto Out; 718 control->ras_fri = g1 % control->ras_max_record_count; 719 } 720 } 721 control->ras_num_recs = 1 + (control->ras_max_record_count + b 722 - control->ras_fri) 723 % control->ras_max_record_count; 724 Out: 725 kfree(buf); 726 return res; 727 } 728 729 static int 730 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 731 { 732 struct amdgpu_device *adev = to_amdgpu_device(control); 733 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 734 u8 *buf, *pp, csum; 735 u32 buf_size; 736 int res; 737 738 /* Modify the header if it exceeds. 739 */ 740 if (amdgpu_bad_page_threshold != 0 && 741 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 742 dev_warn(adev->dev, 743 "Saved bad pages %d reaches threshold value %d\n", 744 control->ras_num_recs, ras->bad_page_cnt_threshold); 745 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 746 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { 747 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 748 control->tbl_rai.health_percent = 0; 749 } 750 751 /* ignore the -ENOTSUPP return value */ 752 amdgpu_dpm_send_rma_reason(adev); 753 } 754 755 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 756 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 757 RAS_TABLE_V2_1_INFO_SIZE + 758 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 759 else 760 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 761 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 762 control->tbl_hdr.checksum = 0; 763 764 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 765 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 766 if (!buf) { 767 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 768 control->tbl_hdr.tbl_size); 769 res = -ENOMEM; 770 goto Out; 771 } 772 773 down_read(&adev->reset_domain->sem); 774 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 775 control->i2c_address + 776 control->ras_record_offset, 777 buf, buf_size); 778 up_read(&adev->reset_domain->sem); 779 if (res < 0) { 780 DRM_ERROR("EEPROM failed reading records:%d\n", 781 res); 782 goto Out; 783 } else if (res < buf_size) { 784 DRM_ERROR("EEPROM read %d out of %d bytes\n", 785 res, buf_size); 786 res = -EIO; 787 goto Out; 788 } 789 790 /** 791 * bad page records have been stored in eeprom, 792 * now calculate gpu health percent 793 */ 794 if (amdgpu_bad_page_threshold != 0 && 795 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && 796 control->ras_num_recs < ras->bad_page_cnt_threshold) 797 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 798 control->ras_num_recs) * 100) / 799 ras->bad_page_cnt_threshold; 800 801 /* Recalc the checksum. 802 */ 803 csum = 0; 804 for (pp = buf; pp < buf + buf_size; pp++) 805 csum += *pp; 806 807 csum += __calc_hdr_byte_sum(control); 808 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 809 csum += __calc_ras_info_byte_sum(control); 810 /* avoid sign extension when assigning to "checksum" */ 811 csum = -csum; 812 control->tbl_hdr.checksum = csum; 813 res = __write_table_header(control); 814 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 815 res = __write_table_ras_info(control); 816 Out: 817 kfree(buf); 818 return res; 819 } 820 821 /** 822 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 823 * @control: pointer to control structure 824 * @record: array of records to append 825 * @num: number of records in @record array 826 * 827 * Append @num records to the table, calculate the checksum and write 828 * the table back to EEPROM. The maximum number of records that 829 * can be appended is between 1 and control->ras_max_record_count, 830 * regardless of how many records are already stored in the table. 831 * 832 * Return 0 on success or if EEPROM is not supported, -errno on error. 833 */ 834 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 835 struct eeprom_table_record *record, 836 const u32 num) 837 { 838 struct amdgpu_device *adev = to_amdgpu_device(control); 839 int res; 840 841 if (!__is_ras_eeprom_supported(adev)) 842 return 0; 843 844 if (num == 0) { 845 DRM_ERROR("will not append 0 records\n"); 846 return -EINVAL; 847 } else if (num > control->ras_max_record_count) { 848 DRM_ERROR("cannot append %d records than the size of table %d\n", 849 num, control->ras_max_record_count); 850 return -EINVAL; 851 } 852 853 mutex_lock(&control->ras_tbl_mutex); 854 855 res = amdgpu_ras_eeprom_append_table(control, record, num); 856 if (!res) 857 res = amdgpu_ras_eeprom_update_header(control); 858 if (!res) 859 amdgpu_ras_debugfs_set_ret_size(control); 860 861 mutex_unlock(&control->ras_tbl_mutex); 862 return res; 863 } 864 865 /** 866 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 867 * @control: pointer to control structure 868 * @buf: pointer to buffer to read into 869 * @fri: first record index, start reading at this index, absolute index 870 * @num: number of records to read 871 * 872 * The caller must hold the table mutex in @control. 873 * Return 0 on success, -errno otherwise. 874 */ 875 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 876 u8 *buf, const u32 fri, const u32 num) 877 { 878 struct amdgpu_device *adev = to_amdgpu_device(control); 879 u32 buf_size; 880 int res; 881 882 /* i2c may be unstable in gpu reset */ 883 down_read(&adev->reset_domain->sem); 884 buf_size = num * RAS_TABLE_RECORD_SIZE; 885 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 886 control->i2c_address + 887 RAS_INDEX_TO_OFFSET(control, fri), 888 buf, buf_size); 889 up_read(&adev->reset_domain->sem); 890 if (res < 0) { 891 DRM_ERROR("Reading %d EEPROM table records error:%d", 892 num, res); 893 } else if (res < buf_size) { 894 /* Short read, return error. 895 */ 896 DRM_ERROR("Read %d records out of %d", 897 res / RAS_TABLE_RECORD_SIZE, num); 898 res = -EIO; 899 } else { 900 res = 0; 901 } 902 903 return res; 904 } 905 906 /** 907 * amdgpu_ras_eeprom_read -- read EEPROM 908 * @control: pointer to control structure 909 * @record: array of records to read into 910 * @num: number of records in @record 911 * 912 * Reads num records from the RAS table in EEPROM and 913 * writes the data into @record array. 914 * 915 * Returns 0 on success, -errno on error. 916 */ 917 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 918 struct eeprom_table_record *record, 919 const u32 num) 920 { 921 struct amdgpu_device *adev = to_amdgpu_device(control); 922 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 923 int i, res; 924 u8 *buf, *pp; 925 u32 g0, g1; 926 927 if (!__is_ras_eeprom_supported(adev)) 928 return 0; 929 930 if (num == 0) { 931 DRM_ERROR("will not read 0 records\n"); 932 return -EINVAL; 933 } else if (num > control->ras_num_recs) { 934 DRM_ERROR("too many records to read:%d available:%d\n", 935 num, control->ras_num_recs); 936 return -EINVAL; 937 } 938 939 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 940 if (!buf) 941 return -ENOMEM; 942 943 /* Determine how many records to read, from the first record 944 * index, fri, to the end of the table, and from the beginning 945 * of the table, such that the total number of records is 946 * @num, and we handle wrap around when fri > 0 and 947 * fri + num > RAS_MAX_RECORD_COUNT. 948 * 949 * First we compute the index of the last element 950 * which would be fetched from each region, 951 * g0 is in [fri, fri + num - 1], and 952 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 953 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 954 * the last element to fetch, we set g0 to _the number_ 955 * of elements to fetch, @num, since we know that the last 956 * indexed to be fetched does not exceed the table. 957 * 958 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 959 * we set g0 to the number of elements to read 960 * until the end of the table, and g1 to the number of 961 * elements to read from the beginning of the table. 962 */ 963 g0 = control->ras_fri + num - 1; 964 g1 = g0 % control->ras_max_record_count; 965 if (g0 < control->ras_max_record_count) { 966 g0 = num; 967 g1 = 0; 968 } else { 969 g0 = control->ras_max_record_count - control->ras_fri; 970 g1 += 1; 971 } 972 973 mutex_lock(&control->ras_tbl_mutex); 974 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 975 if (res) 976 goto Out; 977 if (g1) { 978 res = __amdgpu_ras_eeprom_read(control, 979 buf + g0 * RAS_TABLE_RECORD_SIZE, 980 0, g1); 981 if (res) 982 goto Out; 983 } 984 985 res = 0; 986 987 /* Read up everything? Then transform. 988 */ 989 pp = buf; 990 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 991 __decode_table_record_from_buf(control, &record[i], pp); 992 993 /* update bad channel bitmap */ 994 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 995 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 996 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 997 con->update_channel_flag = true; 998 } 999 } 1000 Out: 1001 kfree(buf); 1002 mutex_unlock(&control->ras_tbl_mutex); 1003 1004 return res; 1005 } 1006 1007 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 1008 { 1009 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1010 return RAS_MAX_RECORD_COUNT_V2_1; 1011 else 1012 return RAS_MAX_RECORD_COUNT; 1013 } 1014 1015 static ssize_t 1016 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 1017 size_t size, loff_t *pos) 1018 { 1019 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1020 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1021 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1022 u8 data[50]; 1023 int res; 1024 1025 if (!size) 1026 return size; 1027 1028 if (!ras || !control) { 1029 res = snprintf(data, sizeof(data), "Not supported\n"); 1030 } else { 1031 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1032 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1033 } 1034 1035 if (*pos >= res) 1036 return 0; 1037 1038 res -= *pos; 1039 res = min_t(size_t, res, size); 1040 1041 if (copy_to_user(buf, &data[*pos], res)) 1042 return -EFAULT; 1043 1044 *pos += res; 1045 1046 return res; 1047 } 1048 1049 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1050 .owner = THIS_MODULE, 1051 .read = amdgpu_ras_debugfs_eeprom_size_read, 1052 .write = NULL, 1053 .llseek = default_llseek, 1054 }; 1055 1056 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1057 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1058 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1059 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1060 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1061 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1062 1063 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1064 "ignore", 1065 "re", 1066 "ue", 1067 }; 1068 1069 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1070 { 1071 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1072 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1073 } 1074 1075 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1076 { 1077 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1078 eeprom_control); 1079 struct dentry *de = ras->de_ras_eeprom_table; 1080 1081 if (de) 1082 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1083 } 1084 1085 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1086 size_t size, loff_t *pos) 1087 { 1088 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1089 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1090 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1091 const size_t orig_size = size; 1092 int res = -EFAULT; 1093 size_t data_len; 1094 1095 mutex_lock(&control->ras_tbl_mutex); 1096 1097 /* We want *pos - data_len > 0, which means there's 1098 * bytes to be printed from data. 1099 */ 1100 data_len = strlen(tbl_hdr_str); 1101 if (*pos < data_len) { 1102 data_len -= *pos; 1103 data_len = min_t(size_t, data_len, size); 1104 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1105 goto Out; 1106 buf += data_len; 1107 size -= data_len; 1108 *pos += data_len; 1109 } 1110 1111 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1112 if (*pos < data_len && size > 0) { 1113 u8 data[tbl_hdr_fmt_size + 1]; 1114 loff_t lpos; 1115 1116 snprintf(data, sizeof(data), tbl_hdr_fmt, 1117 control->tbl_hdr.header, 1118 control->tbl_hdr.version, 1119 control->tbl_hdr.first_rec_offset, 1120 control->tbl_hdr.tbl_size, 1121 control->tbl_hdr.checksum); 1122 1123 data_len -= *pos; 1124 data_len = min_t(size_t, data_len, size); 1125 lpos = *pos - strlen(tbl_hdr_str); 1126 if (copy_to_user(buf, &data[lpos], data_len)) 1127 goto Out; 1128 buf += data_len; 1129 size -= data_len; 1130 *pos += data_len; 1131 } 1132 1133 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1134 if (*pos < data_len && size > 0) { 1135 loff_t lpos; 1136 1137 data_len -= *pos; 1138 data_len = min_t(size_t, data_len, size); 1139 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1140 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1141 goto Out; 1142 buf += data_len; 1143 size -= data_len; 1144 *pos += data_len; 1145 } 1146 1147 data_len = amdgpu_ras_debugfs_table_size(control); 1148 if (*pos < data_len && size > 0) { 1149 u8 dare[RAS_TABLE_RECORD_SIZE]; 1150 u8 data[rec_hdr_fmt_size + 1]; 1151 struct eeprom_table_record record; 1152 int s, r; 1153 1154 /* Find the starting record index 1155 */ 1156 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1157 strlen(rec_hdr_str); 1158 s = s / rec_hdr_fmt_size; 1159 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1160 strlen(rec_hdr_str); 1161 r = r % rec_hdr_fmt_size; 1162 1163 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1164 u32 ai = RAS_RI_TO_AI(control, s); 1165 /* Read a single record 1166 */ 1167 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1168 if (res) 1169 goto Out; 1170 __decode_table_record_from_buf(control, &record, dare); 1171 snprintf(data, sizeof(data), rec_hdr_fmt, 1172 s, 1173 RAS_INDEX_TO_OFFSET(control, ai), 1174 record_err_type_str[record.err_type], 1175 record.bank, 1176 record.ts, 1177 record.offset, 1178 record.mem_channel, 1179 record.mcumc_id, 1180 record.retired_page); 1181 1182 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1183 if (copy_to_user(buf, &data[r], data_len)) { 1184 res = -EFAULT; 1185 goto Out; 1186 } 1187 buf += data_len; 1188 size -= data_len; 1189 *pos += data_len; 1190 r = 0; 1191 } 1192 } 1193 res = 0; 1194 Out: 1195 mutex_unlock(&control->ras_tbl_mutex); 1196 return res < 0 ? res : orig_size - size; 1197 } 1198 1199 static ssize_t 1200 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1201 size_t size, loff_t *pos) 1202 { 1203 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1204 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1205 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1206 u8 data[81]; 1207 int res; 1208 1209 if (!size) 1210 return size; 1211 1212 if (!ras || !control) { 1213 res = snprintf(data, sizeof(data), "Not supported\n"); 1214 if (*pos >= res) 1215 return 0; 1216 1217 res -= *pos; 1218 res = min_t(size_t, res, size); 1219 1220 if (copy_to_user(buf, &data[*pos], res)) 1221 return -EFAULT; 1222 1223 *pos += res; 1224 1225 return res; 1226 } else { 1227 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1228 } 1229 } 1230 1231 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1232 .owner = THIS_MODULE, 1233 .read = amdgpu_ras_debugfs_eeprom_table_read, 1234 .write = NULL, 1235 .llseek = default_llseek, 1236 }; 1237 1238 /** 1239 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1240 * @control: pointer to control structure 1241 * 1242 * Check the checksum of the stored in EEPROM RAS table. 1243 * 1244 * Return 0 if the checksum is correct, 1245 * positive if it is not correct, and 1246 * -errno on I/O error. 1247 */ 1248 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1249 { 1250 struct amdgpu_device *adev = to_amdgpu_device(control); 1251 int buf_size, res; 1252 u8 csum, *buf, *pp; 1253 1254 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1255 buf_size = RAS_TABLE_HEADER_SIZE + 1256 RAS_TABLE_V2_1_INFO_SIZE + 1257 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1258 else 1259 buf_size = RAS_TABLE_HEADER_SIZE + 1260 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1261 1262 buf = kzalloc(buf_size, GFP_KERNEL); 1263 if (!buf) { 1264 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1265 return -ENOMEM; 1266 } 1267 1268 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1269 control->i2c_address + 1270 control->ras_header_offset, 1271 buf, buf_size); 1272 if (res < buf_size) { 1273 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1274 /* On partial reads, return -EIO. 1275 */ 1276 if (res >= 0) 1277 res = -EIO; 1278 goto Out; 1279 } 1280 1281 csum = 0; 1282 for (pp = buf; pp < buf + buf_size; pp++) 1283 csum += *pp; 1284 Out: 1285 kfree(buf); 1286 return res < 0 ? res : csum; 1287 } 1288 1289 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1290 { 1291 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1292 struct amdgpu_device *adev = to_amdgpu_device(control); 1293 unsigned char *buf; 1294 int res; 1295 1296 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1297 if (!buf) { 1298 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1299 return -ENOMEM; 1300 } 1301 1302 /** 1303 * EEPROM table V2_1 supports ras info, 1304 * read EEPROM table ras info 1305 */ 1306 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1307 control->i2c_address + control->ras_info_offset, 1308 buf, RAS_TABLE_V2_1_INFO_SIZE); 1309 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1310 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1311 res = res >= 0 ? -EIO : res; 1312 goto Out; 1313 } 1314 1315 __decode_table_ras_info_from_buf(rai, buf); 1316 1317 Out: 1318 kfree(buf); 1319 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1320 } 1321 1322 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 1323 bool *exceed_err_limit) 1324 { 1325 struct amdgpu_device *adev = to_amdgpu_device(control); 1326 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1327 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1328 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1329 int res; 1330 1331 *exceed_err_limit = false; 1332 1333 if (!__is_ras_eeprom_supported(adev)) 1334 return 0; 1335 1336 /* Verify i2c adapter is initialized */ 1337 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1338 return -ENOENT; 1339 1340 if (!__get_eeprom_i2c_addr(adev, control)) 1341 return -EINVAL; 1342 1343 control->ras_header_offset = RAS_HDR_START; 1344 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1345 mutex_init(&control->ras_tbl_mutex); 1346 1347 /* Read the table header from EEPROM address */ 1348 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1349 control->i2c_address + control->ras_header_offset, 1350 buf, RAS_TABLE_HEADER_SIZE); 1351 if (res < RAS_TABLE_HEADER_SIZE) { 1352 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1353 return res >= 0 ? -EIO : res; 1354 } 1355 1356 __decode_table_header_from_buf(hdr, buf); 1357 1358 if (hdr->version == RAS_TABLE_VER_V2_1) { 1359 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1360 control->ras_record_offset = RAS_RECORD_START_V2_1; 1361 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1362 } else { 1363 control->ras_num_recs = RAS_NUM_RECS(hdr); 1364 control->ras_record_offset = RAS_RECORD_START; 1365 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1366 } 1367 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1368 1369 if (hdr->header == RAS_TABLE_HDR_VAL) { 1370 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1371 control->ras_num_recs); 1372 1373 if (hdr->version == RAS_TABLE_VER_V2_1) { 1374 res = __read_table_ras_info(control); 1375 if (res) 1376 return res; 1377 } 1378 1379 res = __verify_ras_table_checksum(control); 1380 if (res) 1381 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1382 res); 1383 1384 /* Warn if we are at 90% of the threshold or above 1385 */ 1386 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1387 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1388 control->ras_num_recs, 1389 ras->bad_page_cnt_threshold); 1390 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1391 amdgpu_bad_page_threshold != 0) { 1392 if (hdr->version == RAS_TABLE_VER_V2_1) { 1393 res = __read_table_ras_info(control); 1394 if (res) 1395 return res; 1396 } 1397 1398 res = __verify_ras_table_checksum(control); 1399 if (res) 1400 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1401 res); 1402 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1403 /* This means that, the threshold was increased since 1404 * the last time the system was booted, and now, 1405 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1406 * so that at least one more record can be saved, 1407 * before the page count threshold is reached. 1408 */ 1409 dev_info(adev->dev, 1410 "records:%d threshold:%d, resetting " 1411 "RAS table header signature", 1412 control->ras_num_recs, 1413 ras->bad_page_cnt_threshold); 1414 res = amdgpu_ras_eeprom_correct_header_tag(control, 1415 RAS_TABLE_HDR_VAL); 1416 } else { 1417 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1418 control->ras_num_recs, ras->bad_page_cnt_threshold); 1419 if (amdgpu_bad_page_threshold == -1) { 1420 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1."); 1421 res = 0; 1422 } else { 1423 *exceed_err_limit = true; 1424 dev_err(adev->dev, 1425 "RAS records:%d exceed threshold:%d, " 1426 "GPU will not be initialized. Replace this GPU or increase the threshold", 1427 control->ras_num_recs, ras->bad_page_cnt_threshold); 1428 } 1429 } 1430 } else { 1431 DRM_INFO("Creating a new EEPROM table"); 1432 1433 res = amdgpu_ras_eeprom_reset_table(control); 1434 } 1435 1436 return res < 0 ? res : 0; 1437 } 1438