1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Intel Tangier GPIO functions 4 * 5 * Copyright (c) 2016, 2021, 2023 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Pandith N <pandith.n@intel.com> 9 * Raag Jadav <raag.jadav@intel.com> 10 */ 11 12 #ifndef _GPIO_TANGIER_H_ 13 #define _GPIO_TANGIER_H_ 14 15 #include <linux/gpio/driver.h> 16 #include <linux/spinlock_types.h> 17 #include <linux/types.h> 18 19 struct device; 20 21 struct tng_gpio_context; 22 23 /** 24 * struct tng_wake_regs - Platform specific wake registers 25 * @gwmr: Wake mask 26 * @gwsr: Wake source 27 * @gsir: Secure input 28 */ 29 struct tng_wake_regs { 30 u32 gwmr; 31 u32 gwsr; 32 u32 gsir; 33 }; 34 35 /** 36 * struct tng_gpio_pinrange - Map pin numbers to gpio numbers 37 * @gpio_base: Starting GPIO number of this range 38 * @pin_base: Starting pin number of this range 39 * @npins: Number of pins in this range 40 */ 41 struct tng_gpio_pinrange { 42 unsigned int gpio_base; 43 unsigned int pin_base; 44 unsigned int npins; 45 }; 46 47 #define GPIO_PINRANGE(gstart, gend, pstart) \ 48 (struct tng_gpio_pinrange) { \ 49 .gpio_base = (gstart), \ 50 .pin_base = (pstart), \ 51 .npins = (gend) - (gstart) + 1, \ 52 } 53 54 /** 55 * struct tng_gpio_pin_info - Platform specific pinout information 56 * @pin_ranges: Pin to GPIO mapping 57 * @nranges: Number of pin ranges 58 * @name: Respective pinctrl device name 59 */ 60 struct tng_gpio_pin_info { 61 const struct tng_gpio_pinrange *pin_ranges; 62 unsigned int nranges; 63 const char *name; 64 }; 65 66 /** 67 * struct tng_gpio_info - Platform specific GPIO and IRQ information 68 * @base: GPIO base to start numbering with 69 * @ngpio: Amount of GPIOs supported by the controller 70 * @first: First IRQ to start numbering with 71 */ 72 struct tng_gpio_info { 73 int base; 74 u16 ngpio; 75 unsigned int first; 76 }; 77 78 /** 79 * struct tng_gpio - Platform specific private data 80 * @chip: Instance of the struct gpio_chip 81 * @reg_base: Base address of MMIO registers 82 * @irq: Interrupt for the GPIO device 83 * @lock: Synchronization lock to prevent I/O race conditions 84 * @dev: The GPIO device 85 * @ctx: Context to be saved during suspend-resume 86 * @wake_regs: Platform specific wake registers 87 * @pin_info: Platform specific pinout information 88 * @info: Platform specific GPIO and IRQ information 89 */ 90 struct tng_gpio { 91 struct gpio_chip chip; 92 void __iomem *reg_base; 93 int irq; 94 raw_spinlock_t lock; 95 struct device *dev; 96 struct tng_gpio_context *ctx; 97 struct tng_wake_regs wake_regs; 98 struct tng_gpio_pin_info pin_info; 99 struct tng_gpio_info info; 100 }; 101 102 int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio); 103 104 int tng_gpio_suspend(struct device *dev); 105 int tng_gpio_resume(struct device *dev); 106 107 #endif /* _GPIO_TANGIER_H_ */ 108