1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Realtek DHC RTD1625 gpio driver 4 * 5 * Copyright (c) 2023-2026 Realtek Semiconductor Corp. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/gpio/regmap.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/spinlock.h> 22 #include <linux/types.h> 23 24 #define RTD1625_GPIO_DIR BIT(0) 25 #define RTD1625_GPIO_OUT BIT(2) 26 #define RTD1625_GPIO_IN BIT(4) 27 #define RTD1625_GPIO_EDGE_INT_DP BIT(6) 28 #define RTD1625_GPIO_EDGE_INT_EN BIT(8) 29 #define RTD1625_GPIO_LEVEL_INT_EN BIT(16) 30 #define RTD1625_GPIO_LEVEL_INT_DP BIT(18) 31 #define RTD1625_GPIO_DEBOUNCE GENMASK(30, 28) 32 #define RTD1625_GPIO_DEBOUNCE_WREN BIT(31) 33 34 #define RTD1625_GPIO_WREN(x) ((x) << 1) 35 36 /* Write-enable masks for all GPIO configs and reserved hardware bits */ 37 #define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a 38 #define RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a 39 40 #define RTD1625_GPIO_DEBOUNCE_1US 0 41 #define RTD1625_GPIO_DEBOUNCE_10US 1 42 #define RTD1625_GPIO_DEBOUNCE_100US 2 43 #define RTD1625_GPIO_DEBOUNCE_1MS 3 44 #define RTD1625_GPIO_DEBOUNCE_10MS 4 45 #define RTD1625_GPIO_DEBOUNCE_20MS 5 46 #define RTD1625_GPIO_DEBOUNCE_30MS 6 47 #define RTD1625_GPIO_DEBOUNCE_50MS 7 48 49 #define GPIO_CONTROL(gpio) ((gpio) * 4) 50 51 static struct lock_class_key rtd1625_gpio_irq_lock_class; 52 static struct lock_class_key rtd1625_gpio_irq_request_class; 53 54 enum rtd1625_irq_index { 55 RTD1625_IRQ_ASSERT, 56 RTD1625_IRQ_DEASSERT, 57 RTD1625_IRQ_LEVEL, 58 RTD1625_MAX_IRQS 59 }; 60 61 /** 62 * struct rtd1625_gpio_info - Specific GPIO register information 63 * @num_gpios: The number of GPIOs 64 * @irq_type_support: Supported IRQ types 65 * @base_offset: Offset for GPIO controller register 66 * @gpa_offset: Offset for GPIO assert interrupt status register 67 * @gpda_offset: Offset for GPIO deassert interrupt status register 68 * @level_offset: Offset of level interrupt status register 69 * @write_en_all: Write-enable mask for all configurable bits 70 */ 71 struct rtd1625_gpio_info { 72 unsigned int num_gpios; 73 unsigned int irq_type_support; 74 unsigned int base_offset; 75 unsigned int gpa_offset; 76 unsigned int gpda_offset; 77 unsigned int level_offset; 78 unsigned int write_en_all; 79 }; 80 81 struct rtd1625_gpio { 82 struct gpio_regmap *gpio_reg; 83 const struct rtd1625_gpio_info *info; 84 struct regmap *regmap; 85 unsigned int irqs[RTD1625_MAX_IRQS]; 86 raw_spinlock_t lock; 87 struct irq_domain *domain; 88 unsigned int *save_regs; 89 }; 90 91 static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio *data, unsigned int offset) 92 { 93 return data->info->gpa_offset + ((offset / 32) * 4); 94 } 95 96 static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio *data, unsigned int offset) 97 { 98 return data->info->gpda_offset + ((offset / 32) * 4); 99 } 100 101 static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio *data, unsigned int offset) 102 { 103 return data->info->level_offset + ((offset / 32) * 4); 104 } 105 106 static int rtd1625_reg_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap_operation op, 107 unsigned int base, unsigned int offset, unsigned int *reg, 108 unsigned int *mask) 109 { 110 /* Each GPIO has its own dedicated 32-bit register */ 111 struct rtd1625_gpio *data = gpio_regmap_get_drvdata(gpio); 112 int val = 0, ret = 0; 113 *reg = base + offset * 4; 114 115 switch (op) { 116 case GPIO_REGMAP_SET_OP: 117 *mask = RTD1625_GPIO_OUT; 118 return 0; 119 120 case GPIO_REGMAP_GET_OP: 121 ret = regmap_read(data->regmap, *reg, &val); 122 if (ret) 123 return ret; 124 125 if (val & RTD1625_GPIO_DIR) 126 *mask = RTD1625_GPIO_OUT; 127 else 128 *mask = RTD1625_GPIO_IN; 129 return 0; 130 131 case GPIO_REGMAP_GET_DIR_OP: 132 case GPIO_REGMAP_SET_DIR_OP: 133 *mask = RTD1625_GPIO_DIR; 134 return 0; 135 136 default: 137 return -ENOTSUPP; 138 } 139 } 140 141 static int rtd1625_value_xlate(struct gpio_regmap *gpio, 142 enum gpio_regmap_operation op, 143 unsigned int base, unsigned int offset, 144 unsigned int reg, unsigned int *mask, 145 unsigned int *val) 146 { 147 switch (op) { 148 case GPIO_REGMAP_SET_OP: 149 *val |= RTD1625_GPIO_WREN(RTD1625_GPIO_OUT); 150 *mask |= RTD1625_GPIO_WREN(RTD1625_GPIO_OUT); 151 return 0; 152 153 case GPIO_REGMAP_SET_DIR_OP: 154 *val |= RTD1625_GPIO_WREN(RTD1625_GPIO_DIR); 155 *mask |= RTD1625_GPIO_WREN(RTD1625_GPIO_DIR); 156 return 0; 157 158 default: 159 return -ENOTSUPP; 160 } 161 } 162 163 static int rtd1625_gpio_set_debounce(struct rtd1625_gpio *data, unsigned int offset, 164 unsigned int debounce) 165 { 166 u8 deb_val; 167 u32 val; 168 169 switch (debounce) { 170 case 1: 171 deb_val = RTD1625_GPIO_DEBOUNCE_1US; 172 break; 173 case 10: 174 deb_val = RTD1625_GPIO_DEBOUNCE_10US; 175 break; 176 case 100: 177 deb_val = RTD1625_GPIO_DEBOUNCE_100US; 178 break; 179 case 1000: 180 deb_val = RTD1625_GPIO_DEBOUNCE_1MS; 181 break; 182 case 10000: 183 deb_val = RTD1625_GPIO_DEBOUNCE_10MS; 184 break; 185 case 20000: 186 deb_val = RTD1625_GPIO_DEBOUNCE_20MS; 187 break; 188 case 30000: 189 deb_val = RTD1625_GPIO_DEBOUNCE_30MS; 190 break; 191 case 50000: 192 deb_val = RTD1625_GPIO_DEBOUNCE_50MS; 193 break; 194 default: 195 return -ENOTSUPP; 196 } 197 198 val = FIELD_PREP(RTD1625_GPIO_DEBOUNCE, deb_val) | RTD1625_GPIO_DEBOUNCE_WREN; 199 200 guard(raw_spinlock_irqsave)(&data->lock); 201 202 return regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(offset), val); 203 } 204 205 static int rtd1625_gpio_set_config(struct gpio_regmap *gpio, struct gpio_chip *chip, 206 unsigned int offset, unsigned long config) 207 { 208 struct rtd1625_gpio *data = gpio_regmap_get_drvdata(gpio); 209 u32 debounce; 210 211 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { 212 debounce = pinconf_to_config_argument(config); 213 return rtd1625_gpio_set_debounce(data, offset, debounce); 214 } 215 216 return gpiochip_generic_config(chip, offset, config); 217 } 218 219 static void rtd1625_gpio_irq_handle(struct irq_desc *desc) 220 { 221 unsigned int (*get_reg_offset)(struct rtd1625_gpio *gpio, unsigned int offset); 222 struct rtd1625_gpio *data = irq_desc_get_handler_data(desc); 223 struct irq_chip *chip = irq_desc_get_chip(desc); 224 unsigned int irq = irq_desc_get_irq(desc); 225 struct irq_domain *domain = data->domain; 226 unsigned int reg_offset, i, j, val; 227 irq_hw_number_t hwirq; 228 unsigned long status; 229 u32 irq_type; 230 int ret; 231 232 if (irq == data->irqs[RTD1625_IRQ_ASSERT]) 233 get_reg_offset = &rtd1625_gpio_gpa_offset; 234 else if (irq == data->irqs[RTD1625_IRQ_DEASSERT]) 235 get_reg_offset = &rtd1625_gpio_gpda_offset; 236 else if (irq == data->irqs[RTD1625_IRQ_LEVEL]) 237 get_reg_offset = &rtd1625_gpio_level_offset; 238 else 239 return; 240 241 chained_irq_enter(chip, desc); 242 243 for (i = 0; i < data->info->num_gpios; i += 32) { 244 reg_offset = get_reg_offset(data, i); 245 ret = regmap_read(data->regmap, reg_offset, &val); 246 if (ret) { 247 pr_err_ratelimited("Failed to read IRQ status for GPIO %u: %d\n", i, ret); 248 continue; 249 } 250 251 status = val; 252 253 /* 254 * Hardware quirk: The controller fires both "assert" and "de-assert" 255 * interrupts simultaneously on any edge toggle. 256 * We must pre-clear edge interrupts here. If we drop an unwanted 257 * de-assert interrupt below, it will never reach the IRQ core 258 * (generic_handle_domain_irq), meaning ->irq_ack() won't be called. 259 * Failing to clear it here leads to an interrupt storm. 260 */ 261 if (irq != data->irqs[RTD1625_IRQ_LEVEL]) { 262 ret = regmap_write(data->regmap, reg_offset, status); 263 if (ret) 264 pr_err_ratelimited("Failed to clear edge IRQ for GPIO %u: %d\n", 265 i, ret); 266 } 267 268 for_each_set_bit(j, &status, 32) { 269 hwirq = i + j; 270 irq_type = irq_get_trigger_type(irq_find_mapping(domain, hwirq)); 271 272 /* 273 * Filter out the hardware-forced de-assert interrupt unless 274 * the user explicitly requested IRQ_TYPE_EDGE_BOTH. 275 */ 276 if (irq == data->irqs[RTD1625_IRQ_DEASSERT] && 277 irq_type != IRQ_TYPE_EDGE_BOTH) 278 continue; 279 280 generic_handle_domain_irq(domain, hwirq); 281 } 282 } 283 284 chained_irq_exit(chip, desc); 285 } 286 287 static void rtd1625_gpio_ack_irq(struct irq_data *d) 288 { 289 struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d); 290 irq_hw_number_t hwirq = irqd_to_hwirq(d); 291 u32 irq_type = irqd_get_trigger_type(d); 292 u32 bit_mask = BIT(hwirq % 32); 293 int reg_offset; 294 295 if (irq_type & IRQ_TYPE_LEVEL_MASK) { 296 reg_offset = rtd1625_gpio_level_offset(data, hwirq); 297 regmap_write(data->regmap, reg_offset, bit_mask); 298 } 299 } 300 301 static void rtd1625_gpio_enable_edge_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq) 302 { 303 int gpda_reg_offset = rtd1625_gpio_gpda_offset(data, hwirq); 304 int gpa_reg_offset = rtd1625_gpio_gpa_offset(data, hwirq); 305 u32 clr_mask = BIT(hwirq % 32); 306 u32 val; 307 308 guard(raw_spinlock_irqsave)(&data->lock); 309 310 regmap_write(data->regmap, gpa_reg_offset, clr_mask); 311 regmap_write(data->regmap, gpda_reg_offset, clr_mask); 312 val = RTD1625_GPIO_EDGE_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_EN); 313 regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq), val); 314 } 315 316 static void rtd1625_gpio_disable_edge_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq) 317 { 318 u32 val; 319 320 guard(raw_spinlock_irqsave)(&data->lock); 321 322 val = RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_EN); 323 regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq), val); 324 } 325 326 static void rtd1625_gpio_enable_level_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq) 327 { 328 int level_reg_offset = rtd1625_gpio_level_offset(data, hwirq); 329 u32 clr_mask = BIT(hwirq % 32); 330 u32 val; 331 332 guard(raw_spinlock_irqsave)(&data->lock); 333 334 regmap_write(data->regmap, level_reg_offset, clr_mask); 335 val = RTD1625_GPIO_LEVEL_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_EN); 336 regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq), val); 337 } 338 339 static void rtd1625_gpio_disable_level_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq) 340 { 341 u32 val; 342 343 guard(raw_spinlock_irqsave)(&data->lock); 344 345 val = RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_EN); 346 regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq), val); 347 } 348 349 static void rtd1625_gpio_enable_irq(struct irq_data *d) 350 { 351 struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d); 352 irq_hw_number_t hwirq = irqd_to_hwirq(d); 353 u32 irq_type = irqd_get_trigger_type(d); 354 355 gpio_regmap_enable_irq(data->gpio_reg, hwirq); 356 357 if (irq_type & IRQ_TYPE_EDGE_BOTH) 358 rtd1625_gpio_enable_edge_irq(data, hwirq); 359 else if (irq_type & IRQ_TYPE_LEVEL_MASK) 360 rtd1625_gpio_enable_level_irq(data, hwirq); 361 } 362 363 static void rtd1625_gpio_disable_irq(struct irq_data *d) 364 { 365 struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d); 366 irq_hw_number_t hwirq = irqd_to_hwirq(d); 367 u32 irq_type = irqd_get_trigger_type(d); 368 369 if (irq_type & IRQ_TYPE_EDGE_BOTH) 370 rtd1625_gpio_disable_edge_irq(data, hwirq); 371 else if (irq_type & IRQ_TYPE_LEVEL_MASK) 372 rtd1625_gpio_disable_level_irq(data, hwirq); 373 374 gpio_regmap_disable_irq(data->gpio_reg, hwirq); 375 } 376 377 static int rtd1625_gpio_irq_set_level_type(struct irq_data *d, bool level) 378 { 379 u32 val = RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_DP); 380 irq_hw_number_t hwirq = irqd_to_hwirq(d); 381 struct rtd1625_gpio *data; 382 int ret; 383 384 data = irq_data_get_irq_chip_data(d); 385 if (!(data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK)) 386 return -EINVAL; 387 388 if (level) 389 val |= RTD1625_GPIO_LEVEL_INT_DP; 390 391 scoped_guard(raw_spinlock_irqsave, &data->lock) { 392 ret = regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq), 393 val); 394 if (ret) 395 return ret; 396 } 397 398 irq_set_handler_locked(d, handle_level_irq); 399 400 return 0; 401 } 402 403 static int rtd1625_gpio_irq_set_edge_type(struct irq_data *d, bool polarity) 404 { 405 struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d); 406 u32 val = RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_DP); 407 irq_hw_number_t hwirq = irqd_to_hwirq(d); 408 int ret; 409 410 if (!(data->info->irq_type_support & IRQ_TYPE_EDGE_BOTH)) 411 return -EINVAL; 412 413 if (polarity) 414 val |= RTD1625_GPIO_EDGE_INT_DP; 415 416 scoped_guard(raw_spinlock_irqsave, &data->lock) { 417 ret = regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq), 418 val); 419 if (ret) 420 return ret; 421 } 422 423 irq_set_handler_locked(d, handle_edge_irq); 424 425 return 0; 426 } 427 428 static int rtd1625_gpio_irq_set_type(struct irq_data *d, unsigned int type) 429 { 430 switch (type & IRQ_TYPE_SENSE_MASK) { 431 case IRQ_TYPE_EDGE_RISING: 432 return rtd1625_gpio_irq_set_edge_type(d, 1); 433 434 case IRQ_TYPE_EDGE_FALLING: 435 return rtd1625_gpio_irq_set_edge_type(d, 0); 436 437 case IRQ_TYPE_EDGE_BOTH: 438 return rtd1625_gpio_irq_set_edge_type(d, 1); 439 440 case IRQ_TYPE_LEVEL_HIGH: 441 return rtd1625_gpio_irq_set_level_type(d, 0); 442 443 case IRQ_TYPE_LEVEL_LOW: 444 return rtd1625_gpio_irq_set_level_type(d, 1); 445 446 default: 447 return -EINVAL; 448 } 449 } 450 451 static int rtd1625_gpio_irq_request_resources(struct irq_data *d) 452 { 453 struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d); 454 455 return gpio_regmap_reqres_irq(data->gpio_reg, d->hwirq); 456 } 457 458 static void rtd1625_gpio_irq_release_resources(struct irq_data *d) 459 { 460 struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d); 461 462 gpio_regmap_relres_irq(data->gpio_reg, d->hwirq); 463 } 464 465 static struct irq_chip rtd1625_iso_gpio_irq_chip = { 466 .name = "rtd1625-gpio", 467 .irq_ack = rtd1625_gpio_ack_irq, 468 .irq_mask = rtd1625_gpio_disable_irq, 469 .irq_unmask = rtd1625_gpio_enable_irq, 470 .irq_set_type = rtd1625_gpio_irq_set_type, 471 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE, 472 .irq_request_resources = rtd1625_gpio_irq_request_resources, 473 .irq_release_resources = rtd1625_gpio_irq_release_resources, 474 }; 475 476 static int rtd1625_gpio_setup_irq(struct platform_device *pdev, struct rtd1625_gpio *data) 477 { 478 unsigned int num_irqs; 479 int irq; 480 481 /* IRQ is optional; operate as basic GPIO if absent */ 482 irq = platform_get_irq_optional(pdev, 0); 483 if (irq == -ENXIO) 484 return 0; 485 if (irq < 0) 486 return irq; 487 488 num_irqs = (data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK) ? 3 : 2; 489 490 for (unsigned int i = 0; i < num_irqs; i++) { 491 irq = platform_get_irq(pdev, i); 492 if (irq < 0) 493 return irq; 494 495 data->irqs[i] = irq; 496 irq_set_chained_handler_and_data(data->irqs[i], rtd1625_gpio_irq_handle, data); 497 } 498 499 return 0; 500 } 501 502 static int rtd1625_gpio_irq_map(struct irq_domain *domain, unsigned int irq, 503 irq_hw_number_t hwirq) 504 { 505 struct rtd1625_gpio *data = domain->host_data; 506 507 irq_set_chip_data(irq, data); 508 509 irq_set_chip_and_handler(irq, &rtd1625_iso_gpio_irq_chip, handle_bad_irq); 510 511 irq_set_noprobe(irq); 512 513 irq_set_lockdep_class(irq, &rtd1625_gpio_irq_lock_class, 514 &rtd1625_gpio_irq_request_class); 515 516 return 0; 517 } 518 519 static const struct irq_domain_ops rtd1625_gpio_irq_domain_ops = { 520 .map = rtd1625_gpio_irq_map, 521 .xlate = irq_domain_xlate_twocell, 522 }; 523 524 static const struct regmap_config rtd1625_gpio_regmap_config = { 525 .reg_bits = 32, 526 .reg_stride = 4, 527 .val_bits = 32, 528 #ifndef CONFIG_DEBUG_GPIO 529 .disable_locking = true, 530 #endif 531 }; 532 533 static int rtd1625_gpio_probe(struct platform_device *pdev) 534 { 535 struct gpio_regmap_config config = {}; 536 struct irq_domain_info d_info = {}; 537 struct device *dev = &pdev->dev; 538 struct gpio_regmap *gpio_reg; 539 struct rtd1625_gpio *data; 540 void __iomem *irq_base; 541 int ret; 542 543 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 544 if (!data) 545 return -ENOMEM; 546 547 data->info = device_get_match_data(dev); 548 if (!data->info) 549 return -ENODATA; 550 551 irq_base = devm_platform_ioremap_resource(pdev, 0); 552 if (IS_ERR(irq_base)) 553 return PTR_ERR(irq_base); 554 555 data->regmap = devm_regmap_init_mmio(dev, irq_base, &rtd1625_gpio_regmap_config); 556 if (IS_ERR(data->regmap)) 557 return PTR_ERR(data->regmap); 558 559 raw_spin_lock_init(&data->lock); 560 platform_set_drvdata(pdev, data); 561 562 data->save_regs = devm_kcalloc(dev, data->info->num_gpios, sizeof(*data->save_regs), 563 GFP_KERNEL); 564 if (!data->save_regs) 565 return -ENOMEM; 566 567 config.parent = dev; 568 config.regmap = data->regmap; 569 config.ngpio = data->info->num_gpios; 570 config.reg_dat_base = data->info->base_offset; 571 config.reg_set_base = data->info->base_offset; 572 config.reg_dir_out_base = data->info->base_offset; 573 574 config.reg_mask_xlate = rtd1625_reg_mask_xlate; 575 config.set_config = rtd1625_gpio_set_config; 576 config.value_xlate = rtd1625_value_xlate; 577 578 d_info.fwnode = dev_fwnode(&pdev->dev); 579 d_info.size = data->info->num_gpios; 580 d_info.hwirq_max = data->info->num_gpios; 581 d_info.ops = &rtd1625_gpio_irq_domain_ops; 582 d_info.host_data = data; 583 584 data->domain = devm_irq_domain_instantiate(dev, &d_info); 585 if (IS_ERR(data->domain)) 586 return PTR_ERR(data->domain); 587 588 ret = rtd1625_gpio_setup_irq(pdev, data); 589 if (ret) 590 return ret; 591 592 config.irq_domain = data->domain; 593 config.drvdata = data; 594 595 gpio_reg = devm_gpio_regmap_register(dev, &config); 596 if (IS_ERR(gpio_reg)) 597 return PTR_ERR(gpio_reg); 598 599 data->gpio_reg = gpio_reg; 600 601 return 0; 602 } 603 604 static const struct rtd1625_gpio_info rtd1625_iso_gpio_info = { 605 .num_gpios = 166, 606 .irq_type_support = IRQ_TYPE_EDGE_BOTH, 607 .base_offset = 0x100, 608 .gpa_offset = 0x000, 609 .gpda_offset = 0x020, 610 .write_en_all = RTD1625_ISO_GPIO_WREN_ALL, 611 }; 612 613 static const struct rtd1625_gpio_info rtd1625_isom_gpio_info = { 614 .num_gpios = 4, 615 .irq_type_support = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_LOW | 616 IRQ_TYPE_LEVEL_HIGH, 617 .base_offset = 0x20, 618 .gpa_offset = 0x00, 619 .gpda_offset = 0x04, 620 .level_offset = 0x18, 621 .write_en_all = RTD1625_ISOM_GPIO_WREN_ALL, 622 }; 623 624 static int rtd1625_gpio_suspend(struct device *dev) 625 { 626 struct rtd1625_gpio *data = dev_get_drvdata(dev); 627 const struct rtd1625_gpio_info *info = data->info; 628 int ret; 629 630 for (unsigned int i = 0; i < info->num_gpios; i++) { 631 ret = regmap_read(data->regmap, data->info->base_offset + GPIO_CONTROL(i), 632 &data->save_regs[i]); 633 if (ret) 634 return ret; 635 } 636 637 return 0; 638 } 639 640 static int rtd1625_gpio_resume(struct device *dev) 641 { 642 struct rtd1625_gpio *data = dev_get_drvdata(dev); 643 const struct rtd1625_gpio_info *info = data->info; 644 int ret; 645 646 for (unsigned int i = 0; i < info->num_gpios; i++) { 647 ret = regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(i), 648 data->save_regs[i] | info->write_en_all); 649 if (ret) 650 return ret; 651 } 652 653 return 0; 654 } 655 656 static DEFINE_NOIRQ_DEV_PM_OPS(rtd1625_gpio_pm_ops, rtd1625_gpio_suspend, rtd1625_gpio_resume); 657 658 static const struct of_device_id rtd1625_gpio_of_matches[] = { 659 { .compatible = "realtek,rtd1625-iso-gpio", .data = &rtd1625_iso_gpio_info }, 660 { .compatible = "realtek,rtd1625-isom-gpio", .data = &rtd1625_isom_gpio_info }, 661 { } 662 }; 663 MODULE_DEVICE_TABLE(of, rtd1625_gpio_of_matches); 664 665 static struct platform_driver rtd1625_gpio_platform_driver = { 666 .driver = { 667 .name = "gpio-rtd1625", 668 .of_match_table = rtd1625_gpio_of_matches, 669 .pm = pm_sleep_ptr(&rtd1625_gpio_pm_ops), 670 }, 671 .probe = rtd1625_gpio_probe, 672 }; 673 module_platform_driver(rtd1625_gpio_platform_driver); 674 675 MODULE_LICENSE("GPL"); 676 MODULE_AUTHOR("Realtek Semiconductor Corporation"); 677 MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 gpio driver"); 678