1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 #include "packet-header-definitions.h" 44 #include "phy-packet-definitions.h" 45 46 #include <trace/events/firewire.h> 47 48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/firewire_ohci.h> 52 53 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 54 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 55 56 #define DESCRIPTOR_OUTPUT_MORE 0 57 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 58 #define DESCRIPTOR_INPUT_MORE (2 << 12) 59 #define DESCRIPTOR_INPUT_LAST (3 << 12) 60 #define DESCRIPTOR_STATUS (1 << 11) 61 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 62 #define DESCRIPTOR_PING (1 << 7) 63 #define DESCRIPTOR_YY (1 << 6) 64 #define DESCRIPTOR_NO_IRQ (0 << 4) 65 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 66 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 67 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 68 #define DESCRIPTOR_WAIT (3 << 0) 69 70 #define DESCRIPTOR_CMD (0xf << 12) 71 72 struct descriptor { 73 __le16 req_count; 74 __le16 control; 75 __le32 data_address; 76 __le32 branch_address; 77 __le16 res_count; 78 __le16 transfer_status; 79 } __aligned(16); 80 81 #define CONTROL_SET(regs) (regs) 82 #define CONTROL_CLEAR(regs) ((regs) + 4) 83 #define COMMAND_PTR(regs) ((regs) + 12) 84 #define CONTEXT_MATCH(regs) ((regs) + 16) 85 86 #define AR_BUFFER_SIZE (32*1024) 87 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 88 /* we need at least two pages for proper list management */ 89 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 90 91 #define MAX_ASYNC_PAYLOAD 4096 92 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 93 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 94 95 struct ar_context { 96 struct fw_ohci *ohci; 97 struct page *pages[AR_BUFFERS]; 98 void *buffer; 99 struct descriptor *descriptors; 100 dma_addr_t descriptors_bus; 101 void *pointer; 102 unsigned int last_buffer_index; 103 u32 regs; 104 struct work_struct work; 105 }; 106 107 struct context; 108 109 typedef int (*descriptor_callback_t)(struct context *ctx, 110 struct descriptor *d, 111 struct descriptor *last); 112 113 /* 114 * A buffer that contains a block of DMA-able coherent memory used for 115 * storing a portion of a DMA descriptor program. 116 */ 117 struct descriptor_buffer { 118 struct list_head list; 119 dma_addr_t buffer_bus; 120 size_t buffer_size; 121 size_t used; 122 struct descriptor buffer[]; 123 }; 124 125 struct context { 126 struct fw_ohci *ohci; 127 u32 regs; 128 int total_allocation; 129 u32 current_bus; 130 bool running; 131 132 /* 133 * List of page-sized buffers for storing DMA descriptors. 134 * Head of list contains buffers in use and tail of list contains 135 * free buffers. 136 */ 137 struct list_head buffer_list; 138 139 /* 140 * Pointer to a buffer inside buffer_list that contains the tail 141 * end of the current DMA program. 142 */ 143 struct descriptor_buffer *buffer_tail; 144 145 /* 146 * The descriptor containing the branch address of the first 147 * descriptor that has not yet been filled by the device. 148 */ 149 struct descriptor *last; 150 151 /* 152 * The last descriptor block in the DMA program. It contains the branch 153 * address that must be updated upon appending a new descriptor. 154 */ 155 struct descriptor *prev; 156 int prev_z; 157 158 descriptor_callback_t callback; 159 }; 160 161 struct at_context { 162 struct context context; 163 struct work_struct work; 164 bool flushing; 165 }; 166 167 struct iso_context { 168 struct fw_iso_context base; 169 struct context context; 170 void *header; 171 size_t header_length; 172 unsigned long flushing_completions; 173 u32 mc_buffer_bus; 174 u16 mc_completed; 175 u16 last_timestamp; 176 u8 sync; 177 u8 tags; 178 }; 179 180 #define CONFIG_ROM_SIZE (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM) 181 182 struct fw_ohci { 183 struct fw_card card; 184 185 __iomem char *registers; 186 int node_id; 187 int generation; 188 int request_generation; /* for timestamping incoming requests */ 189 unsigned quirks; 190 unsigned int pri_req_max; 191 u32 bus_time; 192 bool bus_time_running; 193 bool is_root; 194 bool csr_state_setclear_abdicate; 195 int n_ir; 196 int n_it; 197 /* 198 * Spinlock for accessing fw_ohci data. Never call out of 199 * this driver with this lock held. 200 */ 201 spinlock_t lock; 202 203 struct mutex phy_reg_mutex; 204 205 void *misc_buffer; 206 dma_addr_t misc_buffer_bus; 207 208 struct ar_context ar_request_ctx; 209 struct ar_context ar_response_ctx; 210 struct at_context at_request_ctx; 211 struct at_context at_response_ctx; 212 213 u32 it_context_support; 214 u32 it_context_mask; /* unoccupied IT contexts */ 215 struct iso_context *it_context_list; 216 u64 ir_context_channels; /* unoccupied channels */ 217 u32 ir_context_support; 218 u32 ir_context_mask; /* unoccupied IR contexts */ 219 struct iso_context *ir_context_list; 220 u64 mc_channels; /* channels in use by the multichannel IR context */ 221 bool mc_allocated; 222 223 __be32 *config_rom; 224 dma_addr_t config_rom_bus; 225 __be32 *next_config_rom; 226 dma_addr_t next_config_rom_bus; 227 __be32 next_header; 228 229 __le32 *self_id; 230 dma_addr_t self_id_bus; 231 struct work_struct bus_reset_work; 232 233 u32 self_id_buffer[512]; 234 }; 235 236 static struct workqueue_struct *selfid_workqueue; 237 238 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 239 { 240 return container_of(card, struct fw_ohci, card); 241 } 242 243 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 244 #define IR_CONTEXT_BUFFER_FILL 0x80000000 245 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 246 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 247 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 248 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 249 250 #define CONTEXT_RUN 0x8000 251 #define CONTEXT_WAKE 0x1000 252 #define CONTEXT_DEAD 0x0800 253 #define CONTEXT_ACTIVE 0x0400 254 255 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 256 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 257 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 258 259 #define OHCI1394_REGISTER_SIZE 0x800 260 #define OHCI1394_PCI_HCI_Control 0x40 261 #define SELF_ID_BUF_SIZE 0x800 262 #define OHCI_VERSION_1_1 0x010010 263 264 static char ohci_driver_name[] = KBUILD_MODNAME; 265 266 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 267 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 268 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 269 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 270 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 271 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 272 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 273 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 274 #define PCI_REV_ID_VIA_VT6306 0x46 275 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 276 277 #define QUIRK_CYCLE_TIMER 0x1 278 #define QUIRK_RESET_PACKET 0x2 279 #define QUIRK_BE_HEADERS 0x4 280 #define QUIRK_NO_1394A 0x8 281 #define QUIRK_NO_MSI 0x10 282 #define QUIRK_TI_SLLZ059 0x20 283 #define QUIRK_IR_WAKE 0x40 284 285 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 286 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 287 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 288 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 289 // while it is probable due to detection of any type of PCIe error. 290 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 291 292 #if IS_ENABLED(CONFIG_X86) 293 294 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 295 { 296 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 297 } 298 299 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 300 301 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 302 { 303 const struct pci_dev *pcie_to_pci_bridge; 304 305 // Detect any type of AMD Ryzen machine. 306 if (!static_cpu_has(X86_FEATURE_ZEN)) 307 return false; 308 309 // Detect VIA VT6306/6307/6308. 310 if (pdev->vendor != PCI_VENDOR_ID_VIA) 311 return false; 312 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 313 return false; 314 315 // Detect Asmedia ASM1083/1085. 316 pcie_to_pci_bridge = pdev->bus->self; 317 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 318 return false; 319 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 320 return false; 321 322 return true; 323 } 324 325 #else 326 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 327 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 328 #endif 329 330 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 331 static const struct { 332 unsigned short vendor, device, revision, flags; 333 } ohci_quirks[] = { 334 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 335 QUIRK_CYCLE_TIMER}, 336 337 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 338 QUIRK_BE_HEADERS}, 339 340 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 341 QUIRK_NO_MSI}, 342 343 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 344 QUIRK_RESET_PACKET}, 345 346 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 347 QUIRK_NO_MSI}, 348 349 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 350 QUIRK_CYCLE_TIMER}, 351 352 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 353 QUIRK_NO_MSI}, 354 355 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 356 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 357 358 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 359 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 360 361 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 362 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 363 364 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 365 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 366 367 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 368 QUIRK_RESET_PACKET}, 369 370 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 371 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 372 373 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 374 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 375 376 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 377 QUIRK_NO_MSI}, 378 379 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 380 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 381 }; 382 383 /* This overrides anything that was found in ohci_quirks[]. */ 384 static int param_quirks; 385 module_param_named(quirks, param_quirks, int, 0644); 386 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 387 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 388 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 389 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 390 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 391 ", disable MSI = " __stringify(QUIRK_NO_MSI) 392 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 393 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 394 ")"); 395 396 #define OHCI_PARAM_DEBUG_AT_AR 1 397 #define OHCI_PARAM_DEBUG_SELFIDS 2 398 #define OHCI_PARAM_DEBUG_IRQS 4 399 400 static int param_debug; 401 module_param_named(debug, param_debug, int, 0644); 402 MODULE_PARM_DESC(debug, "Verbose logging, deprecated in v6.11 kernel or later. (default = 0" 403 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 404 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 405 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 406 ", or a combination, or all = -1)"); 407 408 static bool param_remote_dma; 409 module_param_named(remote_dma, param_remote_dma, bool, 0444); 410 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 411 412 static void log_irqs(struct fw_ohci *ohci, u32 evt) 413 { 414 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) 415 return; 416 417 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 418 evt & OHCI1394_selfIDComplete ? " selfID" : "", 419 evt & OHCI1394_RQPkt ? " AR_req" : "", 420 evt & OHCI1394_RSPkt ? " AR_resp" : "", 421 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 422 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 423 evt & OHCI1394_isochRx ? " IR" : "", 424 evt & OHCI1394_isochTx ? " IT" : "", 425 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 426 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 427 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 428 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 429 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 430 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 431 evt & OHCI1394_busReset ? " busReset" : "", 432 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 433 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 434 OHCI1394_respTxComplete | OHCI1394_isochRx | 435 OHCI1394_isochTx | OHCI1394_postedWriteErr | 436 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 437 OHCI1394_cycleInconsistent | 438 OHCI1394_regAccessFail | OHCI1394_busReset) 439 ? " ?" : ""); 440 } 441 442 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 443 { 444 static const char *const speed[] = { 445 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 446 }; 447 static const char *const power[] = { 448 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 449 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 450 }; 451 static const char port[] = { 452 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.', 453 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-', 454 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p', 455 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c', 456 }; 457 struct self_id_sequence_enumerator enumerator = { 458 .cursor = ohci->self_id_buffer, 459 .quadlet_count = self_id_count, 460 }; 461 462 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 463 return; 464 465 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 466 self_id_count, generation, ohci->node_id); 467 468 while (enumerator.quadlet_count > 0) { 469 unsigned int quadlet_count; 470 unsigned int port_index; 471 const u32 *s; 472 int i; 473 474 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count); 475 if (IS_ERR(s)) 476 break; 477 478 ohci_notice(ohci, 479 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 480 *s, 481 phy_packet_self_id_get_phy_id(*s), 482 port[self_id_sequence_get_port_status(s, quadlet_count, 0)], 483 port[self_id_sequence_get_port_status(s, quadlet_count, 1)], 484 port[self_id_sequence_get_port_status(s, quadlet_count, 2)], 485 speed[*s >> 14 & 3], *s >> 16 & 63, 486 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 487 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 488 489 port_index = 3; 490 for (i = 1; i < quadlet_count; ++i) { 491 ohci_notice(ohci, 492 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 493 s[i], 494 phy_packet_self_id_get_phy_id(s[i]), 495 port[self_id_sequence_get_port_status(s, quadlet_count, port_index)], 496 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)], 497 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)], 498 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)], 499 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)], 500 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)], 501 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)], 502 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)] 503 ); 504 505 port_index += 8; 506 } 507 } 508 } 509 510 static const char *evts[] = { 511 [0x00] = "evt_no_status", [0x01] = "-reserved-", 512 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 513 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 514 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 515 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 516 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 517 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 518 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 519 [0x10] = "-reserved-", [0x11] = "ack_complete", 520 [0x12] = "ack_pending ", [0x13] = "-reserved-", 521 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 522 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 523 [0x18] = "-reserved-", [0x19] = "-reserved-", 524 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 525 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 526 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 527 [0x20] = "pending/cancelled", 528 }; 529 530 static void log_ar_at_event(struct fw_ohci *ohci, 531 char dir, int speed, u32 *header, int evt) 532 { 533 static const char *const tcodes[] = { 534 [TCODE_WRITE_QUADLET_REQUEST] = "QW req", 535 [TCODE_WRITE_BLOCK_REQUEST] = "BW req", 536 [TCODE_WRITE_RESPONSE] = "W resp", 537 [0x3] = "-reserved-", 538 [TCODE_READ_QUADLET_REQUEST] = "QR req", 539 [TCODE_READ_BLOCK_REQUEST] = "BR req", 540 [TCODE_READ_QUADLET_RESPONSE] = "QR resp", 541 [TCODE_READ_BLOCK_RESPONSE] = "BR resp", 542 [TCODE_CYCLE_START] = "cycle start", 543 [TCODE_LOCK_REQUEST] = "Lk req", 544 [TCODE_STREAM_DATA] = "async stream packet", 545 [TCODE_LOCK_RESPONSE] = "Lk resp", 546 [0xc] = "-reserved-", 547 [0xd] = "-reserved-", 548 [TCODE_LINK_INTERNAL] = "link internal", 549 [0xf] = "-reserved-", 550 }; 551 int tcode = async_header_get_tcode(header); 552 char specific[12]; 553 554 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 555 return; 556 557 if (unlikely(evt >= ARRAY_SIZE(evts))) 558 evt = 0x1f; 559 560 if (evt == OHCI1394_evt_bus_reset) { 561 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 562 dir, (header[2] >> 16) & 0xff); 563 return; 564 } 565 566 switch (tcode) { 567 case TCODE_WRITE_QUADLET_REQUEST: 568 case TCODE_READ_QUADLET_RESPONSE: 569 case TCODE_CYCLE_START: 570 snprintf(specific, sizeof(specific), " = %08x", 571 be32_to_cpu((__force __be32)header[3])); 572 break; 573 case TCODE_WRITE_BLOCK_REQUEST: 574 case TCODE_READ_BLOCK_REQUEST: 575 case TCODE_READ_BLOCK_RESPONSE: 576 case TCODE_LOCK_REQUEST: 577 case TCODE_LOCK_RESPONSE: 578 snprintf(specific, sizeof(specific), " %x,%x", 579 async_header_get_data_length(header), 580 async_header_get_extended_tcode(header)); 581 break; 582 default: 583 specific[0] = '\0'; 584 } 585 586 switch (tcode) { 587 case TCODE_STREAM_DATA: 588 ohci_notice(ohci, "A%c %s, %s\n", 589 dir, evts[evt], tcodes[tcode]); 590 break; 591 case TCODE_LINK_INTERNAL: 592 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 593 dir, evts[evt], header[1], header[2]); 594 break; 595 case TCODE_WRITE_QUADLET_REQUEST: 596 case TCODE_WRITE_BLOCK_REQUEST: 597 case TCODE_READ_QUADLET_REQUEST: 598 case TCODE_READ_BLOCK_REQUEST: 599 case TCODE_LOCK_REQUEST: 600 ohci_notice(ohci, 601 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n", 602 dir, speed, async_header_get_tlabel(header), 603 async_header_get_source(header), async_header_get_destination(header), 604 evts[evt], tcodes[tcode], async_header_get_offset(header), specific); 605 break; 606 default: 607 ohci_notice(ohci, 608 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 609 dir, speed, async_header_get_tlabel(header), 610 async_header_get_source(header), async_header_get_destination(header), 611 evts[evt], tcodes[tcode], specific); 612 } 613 } 614 615 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 616 { 617 writel(data, ohci->registers + offset); 618 } 619 620 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 621 { 622 return readl(ohci->registers + offset); 623 } 624 625 static inline void flush_writes(const struct fw_ohci *ohci) 626 { 627 /* Do a dummy read to flush writes. */ 628 reg_read(ohci, OHCI1394_Version); 629 } 630 631 /* 632 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 633 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 634 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 635 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 636 */ 637 static int read_phy_reg(struct fw_ohci *ohci, int addr) 638 { 639 u32 val; 640 int i; 641 642 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 643 for (i = 0; i < 3 + 100; i++) { 644 val = reg_read(ohci, OHCI1394_PhyControl); 645 if (!~val) 646 return -ENODEV; /* Card was ejected. */ 647 648 if (val & OHCI1394_PhyControl_ReadDone) 649 return OHCI1394_PhyControl_ReadData(val); 650 651 /* 652 * Try a few times without waiting. Sleeping is necessary 653 * only when the link/PHY interface is busy. 654 */ 655 if (i >= 3) 656 msleep(1); 657 } 658 ohci_err(ohci, "failed to read phy reg %d\n", addr); 659 dump_stack(); 660 661 return -EBUSY; 662 } 663 664 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 665 { 666 int i; 667 668 reg_write(ohci, OHCI1394_PhyControl, 669 OHCI1394_PhyControl_Write(addr, val)); 670 for (i = 0; i < 3 + 100; i++) { 671 val = reg_read(ohci, OHCI1394_PhyControl); 672 if (!~val) 673 return -ENODEV; /* Card was ejected. */ 674 675 if (!(val & OHCI1394_PhyControl_WritePending)) 676 return 0; 677 678 if (i >= 3) 679 msleep(1); 680 } 681 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 682 dump_stack(); 683 684 return -EBUSY; 685 } 686 687 static int update_phy_reg(struct fw_ohci *ohci, int addr, 688 int clear_bits, int set_bits) 689 { 690 int ret = read_phy_reg(ohci, addr); 691 if (ret < 0) 692 return ret; 693 694 /* 695 * The interrupt status bits are cleared by writing a one bit. 696 * Avoid clearing them unless explicitly requested in set_bits. 697 */ 698 if (addr == 5) 699 clear_bits |= PHY_INT_STATUS_BITS; 700 701 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 702 } 703 704 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 705 { 706 int ret; 707 708 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 709 if (ret < 0) 710 return ret; 711 712 return read_phy_reg(ohci, addr); 713 } 714 715 static int ohci_read_phy_reg(struct fw_card *card, int addr) 716 { 717 struct fw_ohci *ohci = fw_ohci(card); 718 719 guard(mutex)(&ohci->phy_reg_mutex); 720 721 return read_phy_reg(ohci, addr); 722 } 723 724 static int ohci_update_phy_reg(struct fw_card *card, int addr, 725 int clear_bits, int set_bits) 726 { 727 struct fw_ohci *ohci = fw_ohci(card); 728 729 guard(mutex)(&ohci->phy_reg_mutex); 730 731 return update_phy_reg(ohci, addr, clear_bits, set_bits); 732 } 733 734 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 735 { 736 return page_private(ctx->pages[i]); 737 } 738 739 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 740 { 741 struct descriptor *d; 742 743 d = &ctx->descriptors[index]; 744 d->branch_address &= cpu_to_le32(~0xf); 745 d->res_count = cpu_to_le16(PAGE_SIZE); 746 d->transfer_status = 0; 747 748 wmb(); /* finish init of new descriptors before branch_address update */ 749 d = &ctx->descriptors[ctx->last_buffer_index]; 750 d->branch_address |= cpu_to_le32(1); 751 752 ctx->last_buffer_index = index; 753 754 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 755 } 756 757 static void ar_context_release(struct ar_context *ctx) 758 { 759 struct device *dev = ctx->ohci->card.device; 760 unsigned int i; 761 762 if (!ctx->buffer) 763 return; 764 765 vunmap(ctx->buffer); 766 767 for (i = 0; i < AR_BUFFERS; i++) { 768 if (ctx->pages[i]) 769 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 770 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 771 } 772 } 773 774 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 775 { 776 struct fw_ohci *ohci = ctx->ohci; 777 778 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 779 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 780 flush_writes(ohci); 781 782 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 783 } 784 /* FIXME: restart? */ 785 } 786 787 static inline unsigned int ar_next_buffer_index(unsigned int index) 788 { 789 return (index + 1) % AR_BUFFERS; 790 } 791 792 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 793 { 794 return ar_next_buffer_index(ctx->last_buffer_index); 795 } 796 797 /* 798 * We search for the buffer that contains the last AR packet DMA data written 799 * by the controller. 800 */ 801 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 802 unsigned int *buffer_offset) 803 { 804 unsigned int i, next_i, last = ctx->last_buffer_index; 805 __le16 res_count, next_res_count; 806 807 i = ar_first_buffer_index(ctx); 808 res_count = READ_ONCE(ctx->descriptors[i].res_count); 809 810 /* A buffer that is not yet completely filled must be the last one. */ 811 while (i != last && res_count == 0) { 812 813 /* Peek at the next descriptor. */ 814 next_i = ar_next_buffer_index(i); 815 rmb(); /* read descriptors in order */ 816 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 817 /* 818 * If the next descriptor is still empty, we must stop at this 819 * descriptor. 820 */ 821 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 822 /* 823 * The exception is when the DMA data for one packet is 824 * split over three buffers; in this case, the middle 825 * buffer's descriptor might be never updated by the 826 * controller and look still empty, and we have to peek 827 * at the third one. 828 */ 829 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 830 next_i = ar_next_buffer_index(next_i); 831 rmb(); 832 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 833 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 834 goto next_buffer_is_active; 835 } 836 837 break; 838 } 839 840 next_buffer_is_active: 841 i = next_i; 842 res_count = next_res_count; 843 } 844 845 rmb(); /* read res_count before the DMA data */ 846 847 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 848 if (*buffer_offset > PAGE_SIZE) { 849 *buffer_offset = 0; 850 ar_context_abort(ctx, "corrupted descriptor"); 851 } 852 853 return i; 854 } 855 856 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 857 unsigned int end_buffer_index, 858 unsigned int end_buffer_offset) 859 { 860 unsigned int i; 861 862 i = ar_first_buffer_index(ctx); 863 while (i != end_buffer_index) { 864 dma_sync_single_for_cpu(ctx->ohci->card.device, 865 ar_buffer_bus(ctx, i), 866 PAGE_SIZE, DMA_FROM_DEVICE); 867 i = ar_next_buffer_index(i); 868 } 869 if (end_buffer_offset > 0) 870 dma_sync_single_for_cpu(ctx->ohci->card.device, 871 ar_buffer_bus(ctx, i), 872 end_buffer_offset, DMA_FROM_DEVICE); 873 } 874 875 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 876 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk) 877 { 878 return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value); 879 } 880 881 static bool has_be_header_quirk(const struct fw_ohci *ohci) 882 { 883 return !!(ohci->quirks & QUIRK_BE_HEADERS); 884 } 885 #else 886 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused) 887 { 888 return le32_to_cpu(value); 889 } 890 891 static bool has_be_header_quirk(const struct fw_ohci *ohci) 892 { 893 return false; 894 } 895 #endif 896 897 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 898 { 899 struct fw_ohci *ohci = ctx->ohci; 900 struct fw_packet p; 901 u32 status, length, tcode; 902 int evt; 903 904 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); 905 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); 906 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); 907 908 tcode = async_header_get_tcode(p.header); 909 switch (tcode) { 910 case TCODE_WRITE_QUADLET_REQUEST: 911 case TCODE_READ_QUADLET_RESPONSE: 912 p.header[3] = (__force __u32) buffer[3]; 913 p.header_length = 16; 914 p.payload_length = 0; 915 break; 916 917 case TCODE_READ_BLOCK_REQUEST : 918 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 919 p.header_length = 16; 920 p.payload_length = 0; 921 break; 922 923 case TCODE_WRITE_BLOCK_REQUEST: 924 case TCODE_READ_BLOCK_RESPONSE: 925 case TCODE_LOCK_REQUEST: 926 case TCODE_LOCK_RESPONSE: 927 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 928 p.header_length = 16; 929 p.payload_length = async_header_get_data_length(p.header); 930 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 931 ar_context_abort(ctx, "invalid packet length"); 932 return NULL; 933 } 934 break; 935 936 case TCODE_WRITE_RESPONSE: 937 case TCODE_READ_QUADLET_REQUEST: 938 case TCODE_LINK_INTERNAL: 939 p.header_length = 12; 940 p.payload_length = 0; 941 break; 942 943 default: 944 ar_context_abort(ctx, "invalid tcode"); 945 return NULL; 946 } 947 948 p.payload = (void *) buffer + p.header_length; 949 950 /* FIXME: What to do about evt_* errors? */ 951 length = (p.header_length + p.payload_length + 3) / 4; 952 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); 953 evt = (status >> 16) & 0x1f; 954 955 p.ack = evt - 16; 956 p.speed = (status >> 21) & 0x7; 957 p.timestamp = status & 0xffff; 958 p.generation = ohci->request_generation; 959 960 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 961 962 /* 963 * Several controllers, notably from NEC and VIA, forget to 964 * write ack_complete status at PHY packet reception. 965 */ 966 if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL) 967 p.ack = ACK_COMPLETE; 968 969 /* 970 * The OHCI bus reset handler synthesizes a PHY packet with 971 * the new generation number when a bus reset happens (see 972 * section 8.4.2.3). This helps us determine when a request 973 * was received and make sure we send the response in the same 974 * generation. We only need this for requests; for responses 975 * we use the unique tlabel for finding the matching 976 * request. 977 * 978 * Alas some chips sometimes emit bus reset packets with a 979 * wrong generation. We set the correct generation for these 980 * at a slightly incorrect time (in bus_reset_work). 981 */ 982 if (evt == OHCI1394_evt_bus_reset) { 983 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 984 ohci->request_generation = (p.header[2] >> 16) & 0xff; 985 } else if (ctx == &ohci->ar_request_ctx) { 986 fw_core_handle_request(&ohci->card, &p); 987 } else { 988 fw_core_handle_response(&ohci->card, &p); 989 } 990 991 return buffer + length + 1; 992 } 993 994 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 995 { 996 void *next; 997 998 while (p < end) { 999 next = handle_ar_packet(ctx, p); 1000 if (!next) 1001 return p; 1002 p = next; 1003 } 1004 1005 return p; 1006 } 1007 1008 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 1009 { 1010 unsigned int i; 1011 1012 i = ar_first_buffer_index(ctx); 1013 while (i != end_buffer) { 1014 dma_sync_single_for_device(ctx->ohci->card.device, 1015 ar_buffer_bus(ctx, i), 1016 PAGE_SIZE, DMA_FROM_DEVICE); 1017 ar_context_link_page(ctx, i); 1018 i = ar_next_buffer_index(i); 1019 } 1020 } 1021 1022 static void ohci_ar_context_work(struct work_struct *work) 1023 { 1024 struct ar_context *ctx = from_work(ctx, work, work); 1025 unsigned int end_buffer_index, end_buffer_offset; 1026 void *p, *end; 1027 1028 p = ctx->pointer; 1029 if (!p) 1030 return; 1031 1032 end_buffer_index = ar_search_last_active_buffer(ctx, &end_buffer_offset); 1033 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 1034 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 1035 1036 if (end_buffer_index < ar_first_buffer_index(ctx)) { 1037 // The filled part of the overall buffer wraps around; handle all packets up to the 1038 // buffer end here. If the last packet wraps around, its tail will be visible after 1039 // the buffer end because the buffer start pages are mapped there again. 1040 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 1041 p = handle_ar_packets(ctx, p, buffer_end); 1042 if (p < buffer_end) 1043 goto error; 1044 // adjust p to point back into the actual buffer 1045 p -= AR_BUFFERS * PAGE_SIZE; 1046 } 1047 1048 p = handle_ar_packets(ctx, p, end); 1049 if (p != end) { 1050 if (p > end) 1051 ar_context_abort(ctx, "inconsistent descriptor"); 1052 goto error; 1053 } 1054 1055 ctx->pointer = p; 1056 ar_recycle_buffers(ctx, end_buffer_index); 1057 1058 return; 1059 error: 1060 ctx->pointer = NULL; 1061 } 1062 1063 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1064 unsigned int descriptors_offset, u32 regs) 1065 { 1066 struct device *dev = ohci->card.device; 1067 unsigned int i; 1068 dma_addr_t dma_addr; 1069 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1070 struct descriptor *d; 1071 1072 ctx->regs = regs; 1073 ctx->ohci = ohci; 1074 INIT_WORK(&ctx->work, ohci_ar_context_work); 1075 1076 for (i = 0; i < AR_BUFFERS; i++) { 1077 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1078 DMA_FROM_DEVICE, GFP_KERNEL); 1079 if (!ctx->pages[i]) 1080 goto out_of_memory; 1081 set_page_private(ctx->pages[i], dma_addr); 1082 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1083 DMA_FROM_DEVICE); 1084 } 1085 1086 for (i = 0; i < AR_BUFFERS; i++) 1087 pages[i] = ctx->pages[i]; 1088 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1089 pages[AR_BUFFERS + i] = ctx->pages[i]; 1090 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1091 if (!ctx->buffer) 1092 goto out_of_memory; 1093 1094 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1095 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1096 1097 for (i = 0; i < AR_BUFFERS; i++) { 1098 d = &ctx->descriptors[i]; 1099 d->req_count = cpu_to_le16(PAGE_SIZE); 1100 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1101 DESCRIPTOR_STATUS | 1102 DESCRIPTOR_BRANCH_ALWAYS); 1103 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1104 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1105 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1106 } 1107 1108 return 0; 1109 1110 out_of_memory: 1111 ar_context_release(ctx); 1112 1113 return -ENOMEM; 1114 } 1115 1116 static void ar_context_run(struct ar_context *ctx) 1117 { 1118 unsigned int i; 1119 1120 for (i = 0; i < AR_BUFFERS; i++) 1121 ar_context_link_page(ctx, i); 1122 1123 ctx->pointer = ctx->buffer; 1124 1125 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1126 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1127 } 1128 1129 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1130 { 1131 __le16 branch; 1132 1133 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1134 1135 /* figure out which descriptor the branch address goes in */ 1136 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1137 return d; 1138 else 1139 return d + z - 1; 1140 } 1141 1142 static void context_retire_descriptors(struct context *ctx) 1143 { 1144 struct descriptor *d, *last; 1145 u32 address; 1146 int z; 1147 struct descriptor_buffer *desc; 1148 1149 desc = list_entry(ctx->buffer_list.next, 1150 struct descriptor_buffer, list); 1151 last = ctx->last; 1152 while (last->branch_address != 0) { 1153 struct descriptor_buffer *old_desc = desc; 1154 address = le32_to_cpu(last->branch_address); 1155 z = address & 0xf; 1156 address &= ~0xf; 1157 ctx->current_bus = address; 1158 1159 /* If the branch address points to a buffer outside of the 1160 * current buffer, advance to the next buffer. */ 1161 if (address < desc->buffer_bus || 1162 address >= desc->buffer_bus + desc->used) 1163 desc = list_entry(desc->list.next, 1164 struct descriptor_buffer, list); 1165 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1166 last = find_branch_descriptor(d, z); 1167 1168 if (!ctx->callback(ctx, d, last)) 1169 break; 1170 1171 if (old_desc != desc) { 1172 // If we've advanced to the next buffer, move the previous buffer to the 1173 // free list. 1174 old_desc->used = 0; 1175 guard(spinlock_irqsave)(&ctx->ohci->lock); 1176 list_move_tail(&old_desc->list, &ctx->buffer_list); 1177 } 1178 ctx->last = last; 1179 } 1180 } 1181 1182 static void ohci_at_context_work(struct work_struct *work) 1183 { 1184 struct at_context *ctx = from_work(ctx, work, work); 1185 1186 context_retire_descriptors(&ctx->context); 1187 } 1188 1189 static void ohci_isoc_context_work(struct work_struct *work) 1190 { 1191 struct fw_iso_context *base = from_work(base, work, work); 1192 struct iso_context *isoc_ctx = container_of(base, struct iso_context, base); 1193 1194 context_retire_descriptors(&isoc_ctx->context); 1195 } 1196 1197 /* 1198 * Allocate a new buffer and add it to the list of free buffers for this 1199 * context. Must be called with ohci->lock held. 1200 */ 1201 static int context_add_buffer(struct context *ctx) 1202 { 1203 struct descriptor_buffer *desc; 1204 dma_addr_t bus_addr; 1205 int offset; 1206 1207 /* 1208 * 16MB of descriptors should be far more than enough for any DMA 1209 * program. This will catch run-away userspace or DoS attacks. 1210 */ 1211 if (ctx->total_allocation >= 16*1024*1024) 1212 return -ENOMEM; 1213 1214 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1215 if (!desc) 1216 return -ENOMEM; 1217 1218 offset = (void *)&desc->buffer - (void *)desc; 1219 /* 1220 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1221 * for descriptors, even 0x10-byte ones. This can cause page faults when 1222 * an IOMMU is in use and the oversized read crosses a page boundary. 1223 * Work around this by always leaving at least 0x10 bytes of padding. 1224 */ 1225 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1226 desc->buffer_bus = bus_addr + offset; 1227 desc->used = 0; 1228 1229 list_add_tail(&desc->list, &ctx->buffer_list); 1230 ctx->total_allocation += PAGE_SIZE; 1231 1232 return 0; 1233 } 1234 1235 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1236 u32 regs, descriptor_callback_t callback) 1237 { 1238 ctx->ohci = ohci; 1239 ctx->regs = regs; 1240 ctx->total_allocation = 0; 1241 1242 INIT_LIST_HEAD(&ctx->buffer_list); 1243 if (context_add_buffer(ctx) < 0) 1244 return -ENOMEM; 1245 1246 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1247 struct descriptor_buffer, list); 1248 1249 ctx->callback = callback; 1250 1251 /* 1252 * We put a dummy descriptor in the buffer that has a NULL 1253 * branch address and looks like it's been sent. That way we 1254 * have a descriptor to append DMA programs to. 1255 */ 1256 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1257 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1258 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1259 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1260 ctx->last = ctx->buffer_tail->buffer; 1261 ctx->prev = ctx->buffer_tail->buffer; 1262 ctx->prev_z = 1; 1263 1264 return 0; 1265 } 1266 1267 static void context_release(struct context *ctx) 1268 { 1269 struct fw_card *card = &ctx->ohci->card; 1270 struct descriptor_buffer *desc, *tmp; 1271 1272 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1273 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1274 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1275 } 1276 } 1277 1278 /* Must be called with ohci->lock held */ 1279 static struct descriptor *context_get_descriptors(struct context *ctx, 1280 int z, dma_addr_t *d_bus) 1281 { 1282 struct descriptor *d = NULL; 1283 struct descriptor_buffer *desc = ctx->buffer_tail; 1284 1285 if (z * sizeof(*d) > desc->buffer_size) 1286 return NULL; 1287 1288 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1289 /* No room for the descriptor in this buffer, so advance to the 1290 * next one. */ 1291 1292 if (desc->list.next == &ctx->buffer_list) { 1293 /* If there is no free buffer next in the list, 1294 * allocate one. */ 1295 if (context_add_buffer(ctx) < 0) 1296 return NULL; 1297 } 1298 desc = list_entry(desc->list.next, 1299 struct descriptor_buffer, list); 1300 ctx->buffer_tail = desc; 1301 } 1302 1303 d = desc->buffer + desc->used / sizeof(*d); 1304 memset(d, 0, z * sizeof(*d)); 1305 *d_bus = desc->buffer_bus + desc->used; 1306 1307 return d; 1308 } 1309 1310 static void context_run(struct context *ctx, u32 extra) 1311 { 1312 struct fw_ohci *ohci = ctx->ohci; 1313 1314 reg_write(ohci, COMMAND_PTR(ctx->regs), 1315 le32_to_cpu(ctx->last->branch_address)); 1316 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1317 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1318 ctx->running = true; 1319 flush_writes(ohci); 1320 } 1321 1322 static void context_append(struct context *ctx, 1323 struct descriptor *d, int z, int extra) 1324 { 1325 dma_addr_t d_bus; 1326 struct descriptor_buffer *desc = ctx->buffer_tail; 1327 struct descriptor *d_branch; 1328 1329 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1330 1331 desc->used += (z + extra) * sizeof(*d); 1332 1333 wmb(); /* finish init of new descriptors before branch_address update */ 1334 1335 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1336 d_branch->branch_address = cpu_to_le32(d_bus | z); 1337 1338 /* 1339 * VT6306 incorrectly checks only the single descriptor at the 1340 * CommandPtr when the wake bit is written, so if it's a 1341 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1342 * the branch address in the first descriptor. 1343 * 1344 * Not doing this for transmit contexts since not sure how it interacts 1345 * with skip addresses. 1346 */ 1347 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1348 d_branch != ctx->prev && 1349 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1350 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1351 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1352 } 1353 1354 ctx->prev = d; 1355 ctx->prev_z = z; 1356 } 1357 1358 static void context_stop(struct context *ctx) 1359 { 1360 struct fw_ohci *ohci = ctx->ohci; 1361 u32 reg; 1362 int i; 1363 1364 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1365 ctx->running = false; 1366 1367 for (i = 0; i < 1000; i++) { 1368 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1369 if ((reg & CONTEXT_ACTIVE) == 0) 1370 return; 1371 1372 if (i) 1373 udelay(10); 1374 } 1375 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1376 } 1377 1378 struct driver_data { 1379 u8 inline_data[8]; 1380 struct fw_packet *packet; 1381 }; 1382 1383 /* 1384 * This function appends a packet to the DMA queue for transmission. 1385 * Must always be called with the ochi->lock held to ensure proper 1386 * generation handling and locking around packet queue manipulation. 1387 */ 1388 static int at_context_queue_packet(struct at_context *ctx, struct fw_packet *packet) 1389 { 1390 struct context *context = &ctx->context; 1391 struct fw_ohci *ohci = context->ohci; 1392 dma_addr_t d_bus, payload_bus; 1393 struct driver_data *driver_data; 1394 struct descriptor *d, *last; 1395 __le32 *header; 1396 int z, tcode; 1397 1398 d = context_get_descriptors(context, 4, &d_bus); 1399 if (d == NULL) { 1400 packet->ack = RCODE_SEND_ERROR; 1401 return -1; 1402 } 1403 1404 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1405 d[0].res_count = cpu_to_le16(packet->timestamp); 1406 1407 tcode = async_header_get_tcode(packet->header); 1408 header = (__le32 *) &d[1]; 1409 switch (tcode) { 1410 case TCODE_WRITE_QUADLET_REQUEST: 1411 case TCODE_WRITE_BLOCK_REQUEST: 1412 case TCODE_WRITE_RESPONSE: 1413 case TCODE_READ_QUADLET_REQUEST: 1414 case TCODE_READ_BLOCK_REQUEST: 1415 case TCODE_READ_QUADLET_RESPONSE: 1416 case TCODE_READ_BLOCK_RESPONSE: 1417 case TCODE_LOCK_REQUEST: 1418 case TCODE_LOCK_RESPONSE: 1419 ohci1394_at_data_set_src_bus_id(header, false); 1420 ohci1394_at_data_set_speed(header, packet->speed); 1421 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header)); 1422 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header)); 1423 ohci1394_at_data_set_tcode(header, tcode); 1424 1425 ohci1394_at_data_set_destination_id(header, 1426 async_header_get_destination(packet->header)); 1427 1428 if (ctx == &ohci->at_response_ctx) { 1429 ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header)); 1430 } else { 1431 ohci1394_at_data_set_destination_offset(header, 1432 async_header_get_offset(packet->header)); 1433 } 1434 1435 if (tcode_is_block_packet(tcode)) 1436 header[3] = cpu_to_le32(packet->header[3]); 1437 else 1438 header[3] = (__force __le32) packet->header[3]; 1439 1440 d[0].req_count = cpu_to_le16(packet->header_length); 1441 break; 1442 case TCODE_LINK_INTERNAL: 1443 ohci1394_at_data_set_speed(header, packet->speed); 1444 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL); 1445 1446 header[1] = cpu_to_le32(packet->header[1]); 1447 header[2] = cpu_to_le32(packet->header[2]); 1448 d[0].req_count = cpu_to_le16(12); 1449 1450 if (is_ping_packet(&packet->header[1])) 1451 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1452 break; 1453 1454 case TCODE_STREAM_DATA: 1455 ohci1394_it_data_set_speed(header, packet->speed); 1456 ohci1394_it_data_set_tag(header, isoc_header_get_tag(packet->header[0])); 1457 ohci1394_it_data_set_channel(header, isoc_header_get_channel(packet->header[0])); 1458 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 1459 ohci1394_it_data_set_sync(header, isoc_header_get_sy(packet->header[0])); 1460 1461 ohci1394_it_data_set_data_length(header, isoc_header_get_data_length(packet->header[0])); 1462 1463 d[0].req_count = cpu_to_le16(8); 1464 break; 1465 1466 default: 1467 /* BUG(); */ 1468 packet->ack = RCODE_SEND_ERROR; 1469 return -1; 1470 } 1471 1472 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1473 driver_data = (struct driver_data *) &d[3]; 1474 driver_data->packet = packet; 1475 packet->driver_data = driver_data; 1476 1477 if (packet->payload_length > 0) { 1478 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1479 payload_bus = dma_map_single(ohci->card.device, 1480 packet->payload, 1481 packet->payload_length, 1482 DMA_TO_DEVICE); 1483 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1484 packet->ack = RCODE_SEND_ERROR; 1485 return -1; 1486 } 1487 packet->payload_bus = payload_bus; 1488 packet->payload_mapped = true; 1489 } else { 1490 memcpy(driver_data->inline_data, packet->payload, 1491 packet->payload_length); 1492 payload_bus = d_bus + 3 * sizeof(*d); 1493 } 1494 1495 d[2].req_count = cpu_to_le16(packet->payload_length); 1496 d[2].data_address = cpu_to_le32(payload_bus); 1497 last = &d[2]; 1498 z = 3; 1499 } else { 1500 last = &d[0]; 1501 z = 2; 1502 } 1503 1504 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1505 DESCRIPTOR_IRQ_ALWAYS | 1506 DESCRIPTOR_BRANCH_ALWAYS); 1507 1508 /* FIXME: Document how the locking works. */ 1509 if (ohci->generation != packet->generation) { 1510 if (packet->payload_mapped) 1511 dma_unmap_single(ohci->card.device, payload_bus, 1512 packet->payload_length, DMA_TO_DEVICE); 1513 packet->ack = RCODE_GENERATION; 1514 return -1; 1515 } 1516 1517 context_append(context, d, z, 4 - z); 1518 1519 if (context->running) 1520 reg_write(ohci, CONTROL_SET(context->regs), CONTEXT_WAKE); 1521 else 1522 context_run(context, 0); 1523 1524 return 0; 1525 } 1526 1527 static void at_context_flush(struct at_context *ctx) 1528 { 1529 // Avoid dead lock due to programming mistake. 1530 if (WARN_ON_ONCE(current_work() == &ctx->work)) 1531 return; 1532 1533 disable_work_sync(&ctx->work); 1534 1535 WRITE_ONCE(ctx->flushing, true); 1536 ohci_at_context_work(&ctx->work); 1537 WRITE_ONCE(ctx->flushing, false); 1538 1539 enable_work(&ctx->work); 1540 } 1541 1542 static int handle_at_packet(struct context *context, 1543 struct descriptor *d, 1544 struct descriptor *last) 1545 { 1546 struct at_context *ctx = container_of(context, struct at_context, context); 1547 struct fw_ohci *ohci = ctx->context.ohci; 1548 struct driver_data *driver_data; 1549 struct fw_packet *packet; 1550 int evt; 1551 1552 if (last->transfer_status == 0 && !READ_ONCE(ctx->flushing)) 1553 /* This descriptor isn't done yet, stop iteration. */ 1554 return 0; 1555 1556 driver_data = (struct driver_data *) &d[3]; 1557 packet = driver_data->packet; 1558 if (packet == NULL) 1559 /* This packet was cancelled, just continue. */ 1560 return 1; 1561 1562 if (packet->payload_mapped) 1563 dma_unmap_single(ohci->card.device, packet->payload_bus, 1564 packet->payload_length, DMA_TO_DEVICE); 1565 1566 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1567 packet->timestamp = le16_to_cpu(last->res_count); 1568 1569 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1570 1571 switch (evt) { 1572 case OHCI1394_evt_timeout: 1573 /* Async response transmit timed out. */ 1574 packet->ack = RCODE_CANCELLED; 1575 break; 1576 1577 case OHCI1394_evt_flushed: 1578 /* 1579 * The packet was flushed should give same error as 1580 * when we try to use a stale generation count. 1581 */ 1582 packet->ack = RCODE_GENERATION; 1583 break; 1584 1585 case OHCI1394_evt_missing_ack: 1586 if (READ_ONCE(ctx->flushing)) 1587 packet->ack = RCODE_GENERATION; 1588 else { 1589 /* 1590 * Using a valid (current) generation count, but the 1591 * node is not on the bus or not sending acks. 1592 */ 1593 packet->ack = RCODE_NO_ACK; 1594 } 1595 break; 1596 1597 case ACK_COMPLETE + 0x10: 1598 case ACK_PENDING + 0x10: 1599 case ACK_BUSY_X + 0x10: 1600 case ACK_BUSY_A + 0x10: 1601 case ACK_BUSY_B + 0x10: 1602 case ACK_DATA_ERROR + 0x10: 1603 case ACK_TYPE_ERROR + 0x10: 1604 packet->ack = evt - 0x10; 1605 break; 1606 1607 case OHCI1394_evt_no_status: 1608 if (READ_ONCE(ctx->flushing)) { 1609 packet->ack = RCODE_GENERATION; 1610 break; 1611 } 1612 fallthrough; 1613 1614 default: 1615 packet->ack = RCODE_SEND_ERROR; 1616 break; 1617 } 1618 1619 packet->callback(packet, &ohci->card, packet->ack); 1620 1621 return 1; 1622 } 1623 1624 static u32 get_cycle_time(struct fw_ohci *ohci); 1625 1626 static void handle_local_rom(struct fw_ohci *ohci, 1627 struct fw_packet *packet, u32 csr) 1628 { 1629 struct fw_packet response; 1630 int tcode, length, i; 1631 1632 tcode = async_header_get_tcode(packet->header); 1633 if (tcode_is_block_packet(tcode)) 1634 length = async_header_get_data_length(packet->header); 1635 else 1636 length = 4; 1637 1638 i = csr - CSR_CONFIG_ROM; 1639 if (i + length > CONFIG_ROM_SIZE) { 1640 fw_fill_response(&response, packet->header, 1641 RCODE_ADDRESS_ERROR, NULL, 0); 1642 } else if (!tcode_is_read_request(tcode)) { 1643 fw_fill_response(&response, packet->header, 1644 RCODE_TYPE_ERROR, NULL, 0); 1645 } else { 1646 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1647 (void *) ohci->config_rom + i, length); 1648 } 1649 1650 // Timestamping on behalf of the hardware. 1651 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1652 fw_core_handle_response(&ohci->card, &response); 1653 } 1654 1655 static void handle_local_lock(struct fw_ohci *ohci, 1656 struct fw_packet *packet, u32 csr) 1657 { 1658 struct fw_packet response; 1659 int tcode, length, ext_tcode, sel, try; 1660 __be32 *payload, lock_old; 1661 u32 lock_arg, lock_data; 1662 1663 tcode = async_header_get_tcode(packet->header); 1664 length = async_header_get_data_length(packet->header); 1665 payload = packet->payload; 1666 ext_tcode = async_header_get_extended_tcode(packet->header); 1667 1668 if (tcode == TCODE_LOCK_REQUEST && 1669 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1670 lock_arg = be32_to_cpu(payload[0]); 1671 lock_data = be32_to_cpu(payload[1]); 1672 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1673 lock_arg = 0; 1674 lock_data = 0; 1675 } else { 1676 fw_fill_response(&response, packet->header, 1677 RCODE_TYPE_ERROR, NULL, 0); 1678 goto out; 1679 } 1680 1681 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1682 reg_write(ohci, OHCI1394_CSRData, lock_data); 1683 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1684 reg_write(ohci, OHCI1394_CSRControl, sel); 1685 1686 for (try = 0; try < 20; try++) 1687 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1688 lock_old = cpu_to_be32(reg_read(ohci, 1689 OHCI1394_CSRData)); 1690 fw_fill_response(&response, packet->header, 1691 RCODE_COMPLETE, 1692 &lock_old, sizeof(lock_old)); 1693 goto out; 1694 } 1695 1696 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1697 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1698 1699 out: 1700 // Timestamping on behalf of the hardware. 1701 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1702 fw_core_handle_response(&ohci->card, &response); 1703 } 1704 1705 static void handle_local_request(struct at_context *ctx, struct fw_packet *packet) 1706 { 1707 struct fw_ohci *ohci = ctx->context.ohci; 1708 u64 offset, csr; 1709 1710 if (ctx == &ohci->at_request_ctx) { 1711 packet->ack = ACK_PENDING; 1712 packet->callback(packet, &ohci->card, packet->ack); 1713 } 1714 1715 offset = async_header_get_offset(packet->header); 1716 csr = offset - CSR_REGISTER_BASE; 1717 1718 /* Handle config rom reads. */ 1719 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1720 handle_local_rom(ohci, packet, csr); 1721 else switch (csr) { 1722 case CSR_BUS_MANAGER_ID: 1723 case CSR_BANDWIDTH_AVAILABLE: 1724 case CSR_CHANNELS_AVAILABLE_HI: 1725 case CSR_CHANNELS_AVAILABLE_LO: 1726 handle_local_lock(ohci, packet, csr); 1727 break; 1728 default: 1729 if (ctx == &ohci->at_request_ctx) 1730 fw_core_handle_request(&ohci->card, packet); 1731 else 1732 fw_core_handle_response(&ohci->card, packet); 1733 break; 1734 } 1735 1736 if (ctx == &ohci->at_response_ctx) { 1737 packet->ack = ACK_COMPLETE; 1738 packet->callback(packet, &ohci->card, packet->ack); 1739 } 1740 } 1741 1742 static void at_context_transmit(struct at_context *ctx, struct fw_packet *packet) 1743 { 1744 struct fw_ohci *ohci = ctx->context.ohci; 1745 unsigned long flags; 1746 int ret; 1747 1748 spin_lock_irqsave(&ohci->lock, flags); 1749 1750 if (async_header_get_destination(packet->header) == ohci->node_id && 1751 ohci->generation == packet->generation) { 1752 spin_unlock_irqrestore(&ohci->lock, flags); 1753 1754 // Timestamping on behalf of the hardware. 1755 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1756 1757 handle_local_request(ctx, packet); 1758 return; 1759 } 1760 1761 ret = at_context_queue_packet(ctx, packet); 1762 spin_unlock_irqrestore(&ohci->lock, flags); 1763 1764 if (ret < 0) { 1765 // Timestamping on behalf of the hardware. 1766 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1767 1768 packet->callback(packet, &ohci->card, packet->ack); 1769 } 1770 } 1771 1772 static void detect_dead_context(struct fw_ohci *ohci, 1773 const char *name, unsigned int regs) 1774 { 1775 u32 ctl; 1776 1777 ctl = reg_read(ohci, CONTROL_SET(regs)); 1778 if (ctl & CONTEXT_DEAD) 1779 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1780 name, evts[ctl & 0x1f]); 1781 } 1782 1783 static void handle_dead_contexts(struct fw_ohci *ohci) 1784 { 1785 unsigned int i; 1786 char name[8]; 1787 1788 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1789 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1790 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1791 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1792 for (i = 0; i < 32; ++i) { 1793 if (!(ohci->it_context_support & (1 << i))) 1794 continue; 1795 sprintf(name, "IT%u", i); 1796 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1797 } 1798 for (i = 0; i < 32; ++i) { 1799 if (!(ohci->ir_context_support & (1 << i))) 1800 continue; 1801 sprintf(name, "IR%u", i); 1802 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1803 } 1804 /* TODO: maybe try to flush and restart the dead contexts */ 1805 } 1806 1807 static u32 cycle_timer_ticks(u32 cycle_timer) 1808 { 1809 u32 ticks; 1810 1811 ticks = cycle_timer & 0xfff; 1812 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1813 ticks += (3072 * 8000) * (cycle_timer >> 25); 1814 1815 return ticks; 1816 } 1817 1818 /* 1819 * Some controllers exhibit one or more of the following bugs when updating the 1820 * iso cycle timer register: 1821 * - When the lowest six bits are wrapping around to zero, a read that happens 1822 * at the same time will return garbage in the lowest ten bits. 1823 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1824 * not incremented for about 60 ns. 1825 * - Occasionally, the entire register reads zero. 1826 * 1827 * To catch these, we read the register three times and ensure that the 1828 * difference between each two consecutive reads is approximately the same, i.e. 1829 * less than twice the other. Furthermore, any negative difference indicates an 1830 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1831 * execute, so we have enough precision to compute the ratio of the differences.) 1832 */ 1833 static u32 get_cycle_time(struct fw_ohci *ohci) 1834 { 1835 u32 c0, c1, c2; 1836 u32 t0, t1, t2; 1837 s32 diff01, diff12; 1838 int i; 1839 1840 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1841 return 0; 1842 1843 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1844 1845 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1846 i = 0; 1847 c1 = c2; 1848 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1849 do { 1850 c0 = c1; 1851 c1 = c2; 1852 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1853 t0 = cycle_timer_ticks(c0); 1854 t1 = cycle_timer_ticks(c1); 1855 t2 = cycle_timer_ticks(c2); 1856 diff01 = t1 - t0; 1857 diff12 = t2 - t1; 1858 } while ((diff01 <= 0 || diff12 <= 0 || 1859 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1860 && i++ < 20); 1861 } 1862 1863 return c2; 1864 } 1865 1866 /* 1867 * This function has to be called at least every 64 seconds. The bus_time 1868 * field stores not only the upper 25 bits of the BUS_TIME register but also 1869 * the most significant bit of the cycle timer in bit 6 so that we can detect 1870 * changes in this bit. 1871 */ 1872 static u32 update_bus_time(struct fw_ohci *ohci) 1873 { 1874 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1875 1876 if (unlikely(!ohci->bus_time_running)) { 1877 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1878 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1879 (cycle_time_seconds & 0x40); 1880 ohci->bus_time_running = true; 1881 } 1882 1883 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1884 ohci->bus_time += 0x40; 1885 1886 return ohci->bus_time | cycle_time_seconds; 1887 } 1888 1889 static int get_status_for_port(struct fw_ohci *ohci, int port_index, 1890 enum phy_packet_self_id_port_status *status) 1891 { 1892 int reg; 1893 1894 scoped_guard(mutex, &ohci->phy_reg_mutex) { 1895 reg = write_phy_reg(ohci, 7, port_index); 1896 if (reg < 0) 1897 return reg; 1898 1899 reg = read_phy_reg(ohci, 8); 1900 if (reg < 0) 1901 return reg; 1902 } 1903 1904 switch (reg & 0x0f) { 1905 case 0x06: 1906 // is child node (connected to parent node) 1907 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT; 1908 break; 1909 case 0x0e: 1910 // is parent node (connected to child node) 1911 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD; 1912 break; 1913 default: 1914 // not connected 1915 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN; 1916 break; 1917 } 1918 1919 return 0; 1920 } 1921 1922 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1923 int self_id_count) 1924 { 1925 unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id); 1926 int i; 1927 1928 for (i = 0; i < self_id_count; i++) { 1929 u32 entry = ohci->self_id_buffer[i]; 1930 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry); 1931 1932 if (left_phy_id == right_phy_id) 1933 return -1; 1934 if (left_phy_id < right_phy_id) 1935 return i; 1936 } 1937 return i; 1938 } 1939 1940 static int detect_initiated_reset(struct fw_ohci *ohci, bool *is_initiated_reset) 1941 { 1942 int reg; 1943 1944 guard(mutex)(&ohci->phy_reg_mutex); 1945 1946 // Select page 7 1947 reg = write_phy_reg(ohci, 7, 0xe0); 1948 if (reg < 0) 1949 return reg; 1950 1951 reg = read_phy_reg(ohci, 8); 1952 if (reg < 0) 1953 return reg; 1954 1955 // set PMODE bit 1956 reg |= 0x40; 1957 reg = write_phy_reg(ohci, 8, reg); 1958 if (reg < 0) 1959 return reg; 1960 1961 // read register 12 1962 reg = read_phy_reg(ohci, 12); 1963 if (reg < 0) 1964 return reg; 1965 1966 // bit 3 indicates "initiated reset" 1967 *is_initiated_reset = !!((reg & 0x08) == 0x08); 1968 1969 return 0; 1970 } 1971 1972 /* 1973 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1974 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1975 * Construct the selfID from phy register contents. 1976 */ 1977 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1978 { 1979 int reg, i, pos, err; 1980 bool is_initiated_reset; 1981 u32 self_id = 0; 1982 1983 // link active 1, speed 3, bridge 0, contender 1, more packets 0. 1984 phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID); 1985 phy_packet_self_id_zero_set_link_active(&self_id, true); 1986 phy_packet_self_id_zero_set_scode(&self_id, SCODE_800); 1987 phy_packet_self_id_zero_set_contender(&self_id, true); 1988 1989 reg = reg_read(ohci, OHCI1394_NodeID); 1990 if (!(reg & OHCI1394_NodeID_idValid)) { 1991 ohci_notice(ohci, 1992 "node ID not valid, new bus reset in progress\n"); 1993 return -EBUSY; 1994 } 1995 phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f); 1996 1997 reg = ohci_read_phy_reg(&ohci->card, 4); 1998 if (reg < 0) 1999 return reg; 2000 phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07); 2001 2002 reg = ohci_read_phy_reg(&ohci->card, 1); 2003 if (reg < 0) 2004 return reg; 2005 phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f); 2006 2007 for (i = 0; i < 3; i++) { 2008 enum phy_packet_self_id_port_status status; 2009 2010 err = get_status_for_port(ohci, i, &status); 2011 if (err < 0) 2012 return err; 2013 2014 self_id_sequence_set_port_status(&self_id, 1, i, status); 2015 } 2016 2017 err = detect_initiated_reset(ohci, &is_initiated_reset); 2018 if (err < 0) 2019 return err; 2020 phy_packet_self_id_zero_set_initiated_reset(&self_id, is_initiated_reset); 2021 2022 pos = get_self_id_pos(ohci, self_id, self_id_count); 2023 if (pos >= 0) { 2024 memmove(&(ohci->self_id_buffer[pos+1]), 2025 &(ohci->self_id_buffer[pos]), 2026 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 2027 ohci->self_id_buffer[pos] = self_id; 2028 self_id_count++; 2029 } 2030 return self_id_count; 2031 } 2032 2033 static void bus_reset_work(struct work_struct *work) 2034 { 2035 struct fw_ohci *ohci = from_work(ohci, work, bus_reset_work); 2036 int self_id_count, generation, new_generation, i, j; 2037 u32 reg, quadlet; 2038 void *free_rom = NULL; 2039 dma_addr_t free_rom_bus = 0; 2040 bool is_new_root; 2041 2042 reg = reg_read(ohci, OHCI1394_NodeID); 2043 if (!(reg & OHCI1394_NodeID_idValid)) { 2044 ohci_notice(ohci, 2045 "node ID not valid, new bus reset in progress\n"); 2046 return; 2047 } 2048 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 2049 ohci_notice(ohci, "malconfigured bus\n"); 2050 return; 2051 } 2052 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 2053 OHCI1394_NodeID_nodeNumber); 2054 2055 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 2056 if (!(ohci->is_root && is_new_root)) 2057 reg_write(ohci, OHCI1394_LinkControlSet, 2058 OHCI1394_LinkControl_cycleMaster); 2059 ohci->is_root = is_new_root; 2060 2061 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2062 if (ohci1394_self_id_count_is_error(reg)) { 2063 ohci_notice(ohci, "self ID receive error\n"); 2064 return; 2065 } 2066 /* 2067 * The count in the SelfIDCount register is the number of 2068 * bytes in the self ID receive buffer. Since we also receive 2069 * the inverted quadlets and a header quadlet, we shift one 2070 * bit extra to get the actual number of self IDs. 2071 */ 2072 self_id_count = ohci1394_self_id_count_get_size(reg) >> 1; 2073 2074 if (self_id_count > 252) { 2075 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 2076 return; 2077 } 2078 2079 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); 2080 generation = ohci1394_self_id_receive_q0_get_generation(quadlet); 2081 rmb(); 2082 2083 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 2084 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); 2085 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); 2086 2087 if (id != ~id2) { 2088 /* 2089 * If the invalid data looks like a cycle start packet, 2090 * it's likely to be the result of the cycle master 2091 * having a wrong gap count. In this case, the self IDs 2092 * so far are valid and should be processed so that the 2093 * bus manager can then correct the gap count. 2094 */ 2095 if (id == 0xffff008f) { 2096 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2097 self_id_count = j; 2098 break; 2099 } 2100 2101 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2102 j, self_id_count, id, id2); 2103 return; 2104 } 2105 ohci->self_id_buffer[j] = id; 2106 } 2107 2108 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2109 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2110 if (self_id_count < 0) { 2111 ohci_notice(ohci, 2112 "could not construct local self ID\n"); 2113 return; 2114 } 2115 } 2116 2117 if (self_id_count == 0) { 2118 ohci_notice(ohci, "no self IDs\n"); 2119 return; 2120 } 2121 rmb(); 2122 2123 /* 2124 * Check the consistency of the self IDs we just read. The 2125 * problem we face is that a new bus reset can start while we 2126 * read out the self IDs from the DMA buffer. If this happens, 2127 * the DMA buffer will be overwritten with new self IDs and we 2128 * will read out inconsistent data. The OHCI specification 2129 * (section 11.2) recommends a technique similar to 2130 * linux/seqlock.h, where we remember the generation of the 2131 * self IDs in the buffer before reading them out and compare 2132 * it to the current generation after reading them out. If 2133 * the two generations match we know we have a consistent set 2134 * of self IDs. 2135 */ 2136 2137 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2138 new_generation = ohci1394_self_id_count_get_generation(reg); 2139 if (new_generation != generation) { 2140 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2141 return; 2142 } 2143 2144 // FIXME: Document how the locking works. 2145 scoped_guard(spinlock_irq, &ohci->lock) { 2146 ohci->generation = -1; // prevent AT packet queueing 2147 context_stop(&ohci->at_request_ctx.context); 2148 context_stop(&ohci->at_response_ctx.context); 2149 } 2150 2151 /* 2152 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2153 * packets in the AT queues and software needs to drain them. 2154 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2155 */ 2156 at_context_flush(&ohci->at_request_ctx); 2157 at_context_flush(&ohci->at_response_ctx); 2158 2159 scoped_guard(spinlock_irq, &ohci->lock) { 2160 ohci->generation = generation; 2161 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2162 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2163 2164 if (ohci->quirks & QUIRK_RESET_PACKET) 2165 ohci->request_generation = generation; 2166 2167 // This next bit is unrelated to the AT context stuff but we have to do it under the 2168 // spinlock also. If a new config rom was set up before this reset, the old one is 2169 // now no longer in use and we can free it. Update the config rom pointers to point 2170 // to the current config rom and clear the next_config_rom pointer so a new update 2171 // can take place. 2172 if (ohci->next_config_rom != NULL) { 2173 if (ohci->next_config_rom != ohci->config_rom) { 2174 free_rom = ohci->config_rom; 2175 free_rom_bus = ohci->config_rom_bus; 2176 } 2177 ohci->config_rom = ohci->next_config_rom; 2178 ohci->config_rom_bus = ohci->next_config_rom_bus; 2179 ohci->next_config_rom = NULL; 2180 2181 // Restore config_rom image and manually update config_rom registers. 2182 // Writing the header quadlet will indicate that the config rom is ready, 2183 // so we do that last. 2184 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2])); 2185 ohci->config_rom[0] = ohci->next_header; 2186 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(ohci->next_header)); 2187 } 2188 2189 if (param_remote_dma) { 2190 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2191 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2192 } 2193 } 2194 2195 if (free_rom) 2196 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2197 2198 log_selfids(ohci, generation, self_id_count); 2199 2200 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2201 self_id_count, ohci->self_id_buffer, 2202 ohci->csr_state_setclear_abdicate); 2203 ohci->csr_state_setclear_abdicate = false; 2204 } 2205 2206 static irqreturn_t irq_handler(int irq, void *data) 2207 { 2208 struct fw_ohci *ohci = data; 2209 u32 event, iso_event; 2210 int i; 2211 2212 event = reg_read(ohci, OHCI1394_IntEventClear); 2213 2214 if (!event || !~event) 2215 return IRQ_NONE; 2216 2217 if (unlikely(param_debug > 0)) { 2218 dev_notice_ratelimited(ohci->card.device, 2219 "The debug parameter is superseded by tracepoints events, and deprecated."); 2220 } 2221 2222 /* 2223 * busReset and postedWriteErr events must not be cleared yet 2224 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2225 */ 2226 reg_write(ohci, OHCI1394_IntEventClear, 2227 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2228 trace_irqs(ohci->card.index, event); 2229 log_irqs(ohci, event); 2230 // The flag is masked again at bus_reset_work() scheduled by selfID event. 2231 if (event & OHCI1394_busReset) 2232 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2233 2234 if (event & OHCI1394_selfIDComplete) { 2235 if (trace_self_id_complete_enabled()) { 2236 u32 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2237 2238 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, 2239 has_be_header_quirk(ohci)); 2240 } 2241 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2242 } 2243 2244 if (event & OHCI1394_RQPkt) 2245 queue_work(ohci->card.async_wq, &ohci->ar_request_ctx.work); 2246 2247 if (event & OHCI1394_RSPkt) 2248 queue_work(ohci->card.async_wq, &ohci->ar_response_ctx.work); 2249 2250 if (event & OHCI1394_reqTxComplete) 2251 queue_work(ohci->card.async_wq, &ohci->at_request_ctx.work); 2252 2253 if (event & OHCI1394_respTxComplete) 2254 queue_work(ohci->card.async_wq, &ohci->at_response_ctx.work); 2255 2256 if (event & OHCI1394_isochRx) { 2257 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2258 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2259 2260 while (iso_event) { 2261 i = ffs(iso_event) - 1; 2262 fw_iso_context_schedule_flush_completions(&ohci->ir_context_list[i].base); 2263 iso_event &= ~(1 << i); 2264 } 2265 } 2266 2267 if (event & OHCI1394_isochTx) { 2268 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2269 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2270 2271 while (iso_event) { 2272 i = ffs(iso_event) - 1; 2273 fw_iso_context_schedule_flush_completions(&ohci->it_context_list[i].base); 2274 iso_event &= ~(1 << i); 2275 } 2276 } 2277 2278 if (unlikely(event & OHCI1394_regAccessFail)) 2279 ohci_err(ohci, "register access failure\n"); 2280 2281 if (unlikely(event & OHCI1394_postedWriteErr)) { 2282 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2283 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2284 reg_write(ohci, OHCI1394_IntEventClear, 2285 OHCI1394_postedWriteErr); 2286 dev_err_ratelimited(ohci->card.device, "PCI posted write error\n"); 2287 } 2288 2289 if (unlikely(event & OHCI1394_cycleTooLong)) { 2290 dev_notice_ratelimited(ohci->card.device, "isochronous cycle too long\n"); 2291 reg_write(ohci, OHCI1394_LinkControlSet, 2292 OHCI1394_LinkControl_cycleMaster); 2293 } 2294 2295 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2296 /* 2297 * We need to clear this event bit in order to make 2298 * cycleMatch isochronous I/O work. In theory we should 2299 * stop active cycleMatch iso contexts now and restart 2300 * them at least two cycles later. (FIXME?) 2301 */ 2302 dev_notice_ratelimited(ohci->card.device, "isochronous cycle inconsistent\n"); 2303 } 2304 2305 if (unlikely(event & OHCI1394_unrecoverableError)) 2306 handle_dead_contexts(ohci); 2307 2308 if (event & OHCI1394_cycle64Seconds) { 2309 guard(spinlock)(&ohci->lock); 2310 update_bus_time(ohci); 2311 } else 2312 flush_writes(ohci); 2313 2314 return IRQ_HANDLED; 2315 } 2316 2317 static int software_reset(struct fw_ohci *ohci) 2318 { 2319 u32 val; 2320 int i; 2321 2322 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2323 for (i = 0; i < 500; i++) { 2324 val = reg_read(ohci, OHCI1394_HCControlSet); 2325 if (!~val) 2326 return -ENODEV; /* Card was ejected. */ 2327 2328 if (!(val & OHCI1394_HCControl_softReset)) 2329 return 0; 2330 2331 msleep(1); 2332 } 2333 2334 return -EBUSY; 2335 } 2336 2337 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2338 { 2339 size_t size = length * 4; 2340 2341 memcpy(dest, src, size); 2342 if (size < CONFIG_ROM_SIZE) 2343 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2344 } 2345 2346 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2347 { 2348 bool enable_1394a; 2349 int ret, clear, set, offset; 2350 2351 /* Check if the driver should configure link and PHY. */ 2352 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2353 OHCI1394_HCControl_programPhyEnable)) 2354 return 0; 2355 2356 /* Paranoia: check whether the PHY supports 1394a, too. */ 2357 enable_1394a = false; 2358 ret = read_phy_reg(ohci, 2); 2359 if (ret < 0) 2360 return ret; 2361 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2362 ret = read_paged_phy_reg(ohci, 1, 8); 2363 if (ret < 0) 2364 return ret; 2365 if (ret >= 1) 2366 enable_1394a = true; 2367 } 2368 2369 if (ohci->quirks & QUIRK_NO_1394A) 2370 enable_1394a = false; 2371 2372 /* Configure PHY and link consistently. */ 2373 if (enable_1394a) { 2374 clear = 0; 2375 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2376 } else { 2377 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2378 set = 0; 2379 } 2380 ret = update_phy_reg(ohci, 5, clear, set); 2381 if (ret < 0) 2382 return ret; 2383 2384 if (enable_1394a) 2385 offset = OHCI1394_HCControlSet; 2386 else 2387 offset = OHCI1394_HCControlClear; 2388 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2389 2390 /* Clean up: configuration has been taken care of. */ 2391 reg_write(ohci, OHCI1394_HCControlClear, 2392 OHCI1394_HCControl_programPhyEnable); 2393 2394 return 0; 2395 } 2396 2397 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2398 { 2399 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2400 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2401 int reg, i; 2402 2403 reg = read_phy_reg(ohci, 2); 2404 if (reg < 0) 2405 return reg; 2406 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2407 return 0; 2408 2409 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2410 reg = read_paged_phy_reg(ohci, 1, i + 10); 2411 if (reg < 0) 2412 return reg; 2413 if (reg != id[i]) 2414 return 0; 2415 } 2416 return 1; 2417 } 2418 2419 static int ohci_enable(struct fw_card *card, 2420 const __be32 *config_rom, size_t length) 2421 { 2422 struct fw_ohci *ohci = fw_ohci(card); 2423 u32 lps, version, irqs; 2424 int i, ret; 2425 2426 ret = software_reset(ohci); 2427 if (ret < 0) { 2428 ohci_err(ohci, "failed to reset ohci card\n"); 2429 return ret; 2430 } 2431 2432 /* 2433 * Now enable LPS, which we need in order to start accessing 2434 * most of the registers. In fact, on some cards (ALI M5251), 2435 * accessing registers in the SClk domain without LPS enabled 2436 * will lock up the machine. Wait 50msec to make sure we have 2437 * full link enabled. However, with some cards (well, at least 2438 * a JMicron PCIe card), we have to try again sometimes. 2439 * 2440 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2441 * cannot actually use the phy at that time. These need tens of 2442 * millisecods pause between LPS write and first phy access too. 2443 */ 2444 2445 reg_write(ohci, OHCI1394_HCControlSet, 2446 OHCI1394_HCControl_LPS | 2447 OHCI1394_HCControl_postedWriteEnable); 2448 flush_writes(ohci); 2449 2450 for (lps = 0, i = 0; !lps && i < 3; i++) { 2451 msleep(50); 2452 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2453 OHCI1394_HCControl_LPS; 2454 } 2455 2456 if (!lps) { 2457 ohci_err(ohci, "failed to set Link Power Status\n"); 2458 return -EIO; 2459 } 2460 2461 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2462 ret = probe_tsb41ba3d(ohci); 2463 if (ret < 0) 2464 return ret; 2465 if (ret) 2466 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2467 else 2468 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2469 } 2470 2471 reg_write(ohci, OHCI1394_HCControlClear, 2472 OHCI1394_HCControl_noByteSwapData); 2473 2474 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2475 reg_write(ohci, OHCI1394_LinkControlSet, 2476 OHCI1394_LinkControl_cycleTimerEnable | 2477 OHCI1394_LinkControl_cycleMaster); 2478 2479 reg_write(ohci, OHCI1394_ATRetries, 2480 OHCI1394_MAX_AT_REQ_RETRIES | 2481 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2482 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2483 (200 << 16)); 2484 2485 ohci->bus_time_running = false; 2486 2487 for (i = 0; i < 32; i++) 2488 if (ohci->ir_context_support & (1 << i)) 2489 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2490 IR_CONTEXT_MULTI_CHANNEL_MODE); 2491 2492 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2493 if (version >= OHCI_VERSION_1_1) { 2494 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2495 0xfffffffe); 2496 card->broadcast_channel_auto_allocated = true; 2497 } 2498 2499 /* Get implemented bits of the priority arbitration request counter. */ 2500 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2501 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2502 reg_write(ohci, OHCI1394_FairnessControl, 0); 2503 card->priority_budget_implemented = ohci->pri_req_max != 0; 2504 2505 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2506 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2507 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2508 2509 ret = configure_1394a_enhancements(ohci); 2510 if (ret < 0) 2511 return ret; 2512 2513 /* Activate link_on bit and contender bit in our self ID packets.*/ 2514 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2515 if (ret < 0) 2516 return ret; 2517 2518 /* 2519 * When the link is not yet enabled, the atomic config rom 2520 * update mechanism described below in ohci_set_config_rom() 2521 * is not active. We have to update ConfigRomHeader and 2522 * BusOptions manually, and the write to ConfigROMmap takes 2523 * effect immediately. We tie this to the enabling of the 2524 * link, so we have a valid config rom before enabling - the 2525 * OHCI requires that ConfigROMhdr and BusOptions have valid 2526 * values before enabling. 2527 * 2528 * However, when the ConfigROMmap is written, some controllers 2529 * always read back quadlets 0 and 2 from the config rom to 2530 * the ConfigRomHeader and BusOptions registers on bus reset. 2531 * They shouldn't do that in this initial case where the link 2532 * isn't enabled. This means we have to use the same 2533 * workaround here, setting the bus header to 0 and then write 2534 * the right values in the bus reset work item. 2535 */ 2536 2537 if (config_rom) { 2538 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2539 &ohci->next_config_rom_bus, GFP_KERNEL); 2540 if (ohci->next_config_rom == NULL) 2541 return -ENOMEM; 2542 2543 copy_config_rom(ohci->next_config_rom, config_rom, length); 2544 } else { 2545 /* 2546 * In the suspend case, config_rom is NULL, which 2547 * means that we just reuse the old config rom. 2548 */ 2549 ohci->next_config_rom = ohci->config_rom; 2550 ohci->next_config_rom_bus = ohci->config_rom_bus; 2551 } 2552 2553 ohci->next_header = ohci->next_config_rom[0]; 2554 ohci->next_config_rom[0] = 0; 2555 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2556 reg_write(ohci, OHCI1394_BusOptions, 2557 be32_to_cpu(ohci->next_config_rom[2])); 2558 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2559 2560 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2561 2562 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2563 OHCI1394_RQPkt | OHCI1394_RSPkt | 2564 OHCI1394_isochTx | OHCI1394_isochRx | 2565 OHCI1394_postedWriteErr | 2566 OHCI1394_selfIDComplete | 2567 OHCI1394_regAccessFail | 2568 OHCI1394_cycleInconsistent | 2569 OHCI1394_unrecoverableError | 2570 OHCI1394_cycleTooLong | 2571 OHCI1394_masterIntEnable | 2572 OHCI1394_busReset; 2573 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2574 2575 reg_write(ohci, OHCI1394_HCControlSet, 2576 OHCI1394_HCControl_linkEnable | 2577 OHCI1394_HCControl_BIBimageValid); 2578 2579 reg_write(ohci, OHCI1394_LinkControlSet, 2580 OHCI1394_LinkControl_rcvSelfID | 2581 OHCI1394_LinkControl_rcvPhyPkt); 2582 2583 ar_context_run(&ohci->ar_request_ctx); 2584 ar_context_run(&ohci->ar_response_ctx); 2585 2586 flush_writes(ohci); 2587 2588 /* We are ready to go, reset bus to finish initialization. */ 2589 fw_schedule_bus_reset(&ohci->card, false, true); 2590 2591 return 0; 2592 } 2593 2594 static int ohci_set_config_rom(struct fw_card *card, 2595 const __be32 *config_rom, size_t length) 2596 { 2597 struct fw_ohci *ohci; 2598 __be32 *next_config_rom; 2599 dma_addr_t next_config_rom_bus; 2600 2601 ohci = fw_ohci(card); 2602 2603 /* 2604 * When the OHCI controller is enabled, the config rom update 2605 * mechanism is a bit tricky, but easy enough to use. See 2606 * section 5.5.6 in the OHCI specification. 2607 * 2608 * The OHCI controller caches the new config rom address in a 2609 * shadow register (ConfigROMmapNext) and needs a bus reset 2610 * for the changes to take place. When the bus reset is 2611 * detected, the controller loads the new values for the 2612 * ConfigRomHeader and BusOptions registers from the specified 2613 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2614 * shadow register. All automatically and atomically. 2615 * 2616 * Now, there's a twist to this story. The automatic load of 2617 * ConfigRomHeader and BusOptions doesn't honor the 2618 * noByteSwapData bit, so with a be32 config rom, the 2619 * controller will load be32 values in to these registers 2620 * during the atomic update, even on little endian 2621 * architectures. The workaround we use is to put a 0 in the 2622 * header quadlet; 0 is endian agnostic and means that the 2623 * config rom isn't ready yet. In the bus reset work item we 2624 * then set up the real values for the two registers. 2625 * 2626 * We use ohci->lock to avoid racing with the code that sets 2627 * ohci->next_config_rom to NULL (see bus_reset_work). 2628 */ 2629 2630 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2631 &next_config_rom_bus, GFP_KERNEL); 2632 if (next_config_rom == NULL) 2633 return -ENOMEM; 2634 2635 scoped_guard(spinlock_irq, &ohci->lock) { 2636 // If there is not an already pending config_rom update, push our new allocation 2637 // into the ohci->next_config_rom and then mark the local variable as null so that 2638 // we won't deallocate the new buffer. 2639 // 2640 // OTOH, if there is a pending config_rom update, just use that buffer with the new 2641 // config_rom data, and let this routine free the unused DMA allocation. 2642 if (ohci->next_config_rom == NULL) { 2643 ohci->next_config_rom = next_config_rom; 2644 ohci->next_config_rom_bus = next_config_rom_bus; 2645 next_config_rom = NULL; 2646 } 2647 2648 copy_config_rom(ohci->next_config_rom, config_rom, length); 2649 2650 ohci->next_header = config_rom[0]; 2651 ohci->next_config_rom[0] = 0; 2652 2653 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2654 } 2655 2656 /* If we didn't use the DMA allocation, delete it. */ 2657 if (next_config_rom != NULL) { 2658 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2659 next_config_rom_bus); 2660 } 2661 2662 /* 2663 * Now initiate a bus reset to have the changes take 2664 * effect. We clean up the old config rom memory and DMA 2665 * mappings in the bus reset work item, since the OHCI 2666 * controller could need to access it before the bus reset 2667 * takes effect. 2668 */ 2669 2670 fw_schedule_bus_reset(&ohci->card, true, true); 2671 2672 return 0; 2673 } 2674 2675 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2676 { 2677 struct fw_ohci *ohci = fw_ohci(card); 2678 2679 at_context_transmit(&ohci->at_request_ctx, packet); 2680 } 2681 2682 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2683 { 2684 struct fw_ohci *ohci = fw_ohci(card); 2685 2686 at_context_transmit(&ohci->at_response_ctx, packet); 2687 } 2688 2689 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2690 { 2691 struct fw_ohci *ohci = fw_ohci(card); 2692 struct at_context *ctx = &ohci->at_request_ctx; 2693 struct driver_data *driver_data = packet->driver_data; 2694 int ret = -ENOENT; 2695 2696 // Avoid dead lock due to programming mistake. 2697 if (WARN_ON_ONCE(current_work() == &ctx->work)) 2698 return 0; 2699 disable_work_sync(&ctx->work); 2700 2701 if (packet->ack != 0) 2702 goto out; 2703 2704 if (packet->payload_mapped) 2705 dma_unmap_single(ohci->card.device, packet->payload_bus, 2706 packet->payload_length, DMA_TO_DEVICE); 2707 2708 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2709 driver_data->packet = NULL; 2710 packet->ack = RCODE_CANCELLED; 2711 2712 // Timestamping on behalf of the hardware. 2713 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2714 2715 packet->callback(packet, &ohci->card, packet->ack); 2716 ret = 0; 2717 out: 2718 enable_work(&ctx->work); 2719 2720 return ret; 2721 } 2722 2723 static int ohci_enable_phys_dma(struct fw_card *card, 2724 int node_id, int generation) 2725 { 2726 struct fw_ohci *ohci = fw_ohci(card); 2727 int n, ret = 0; 2728 2729 if (param_remote_dma) 2730 return 0; 2731 2732 /* 2733 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2734 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2735 */ 2736 2737 guard(spinlock_irqsave)(&ohci->lock); 2738 2739 if (ohci->generation != generation) 2740 return -ESTALE; 2741 2742 /* 2743 * Note, if the node ID contains a non-local bus ID, physical DMA is 2744 * enabled for _all_ nodes on remote buses. 2745 */ 2746 2747 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2748 if (n < 32) 2749 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2750 else 2751 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2752 2753 flush_writes(ohci); 2754 2755 return ret; 2756 } 2757 2758 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2759 { 2760 struct fw_ohci *ohci = fw_ohci(card); 2761 u32 value; 2762 2763 switch (csr_offset) { 2764 case CSR_STATE_CLEAR: 2765 case CSR_STATE_SET: 2766 if (ohci->is_root && 2767 (reg_read(ohci, OHCI1394_LinkControlSet) & 2768 OHCI1394_LinkControl_cycleMaster)) 2769 value = CSR_STATE_BIT_CMSTR; 2770 else 2771 value = 0; 2772 if (ohci->csr_state_setclear_abdicate) 2773 value |= CSR_STATE_BIT_ABDICATE; 2774 2775 return value; 2776 2777 case CSR_NODE_IDS: 2778 return reg_read(ohci, OHCI1394_NodeID) << 16; 2779 2780 case CSR_CYCLE_TIME: 2781 return get_cycle_time(ohci); 2782 2783 case CSR_BUS_TIME: 2784 { 2785 // We might be called just after the cycle timer has wrapped around but just before 2786 // the cycle64Seconds handler, so we better check here, too, if the bus time needs 2787 // to be updated. 2788 2789 guard(spinlock_irqsave)(&ohci->lock); 2790 return update_bus_time(ohci); 2791 } 2792 case CSR_BUSY_TIMEOUT: 2793 value = reg_read(ohci, OHCI1394_ATRetries); 2794 return (value >> 4) & 0x0ffff00f; 2795 2796 case CSR_PRIORITY_BUDGET: 2797 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2798 (ohci->pri_req_max << 8); 2799 2800 default: 2801 WARN_ON(1); 2802 return 0; 2803 } 2804 } 2805 2806 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2807 { 2808 struct fw_ohci *ohci = fw_ohci(card); 2809 2810 switch (csr_offset) { 2811 case CSR_STATE_CLEAR: 2812 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2813 reg_write(ohci, OHCI1394_LinkControlClear, 2814 OHCI1394_LinkControl_cycleMaster); 2815 flush_writes(ohci); 2816 } 2817 if (value & CSR_STATE_BIT_ABDICATE) 2818 ohci->csr_state_setclear_abdicate = false; 2819 break; 2820 2821 case CSR_STATE_SET: 2822 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2823 reg_write(ohci, OHCI1394_LinkControlSet, 2824 OHCI1394_LinkControl_cycleMaster); 2825 flush_writes(ohci); 2826 } 2827 if (value & CSR_STATE_BIT_ABDICATE) 2828 ohci->csr_state_setclear_abdicate = true; 2829 break; 2830 2831 case CSR_NODE_IDS: 2832 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2833 flush_writes(ohci); 2834 break; 2835 2836 case CSR_CYCLE_TIME: 2837 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2838 reg_write(ohci, OHCI1394_IntEventSet, 2839 OHCI1394_cycleInconsistent); 2840 flush_writes(ohci); 2841 break; 2842 2843 case CSR_BUS_TIME: 2844 { 2845 guard(spinlock_irqsave)(&ohci->lock); 2846 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f); 2847 break; 2848 } 2849 case CSR_BUSY_TIMEOUT: 2850 value = (value & 0xf) | ((value & 0xf) << 4) | 2851 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2852 reg_write(ohci, OHCI1394_ATRetries, value); 2853 flush_writes(ohci); 2854 break; 2855 2856 case CSR_PRIORITY_BUDGET: 2857 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2858 flush_writes(ohci); 2859 break; 2860 2861 default: 2862 WARN_ON(1); 2863 break; 2864 } 2865 } 2866 2867 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause) 2868 { 2869 trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2870 ctx->header_length); 2871 trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2872 ctx->header_length); 2873 2874 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2875 ctx->header_length, ctx->header, 2876 ctx->base.callback_data); 2877 ctx->header_length = 0; 2878 } 2879 2880 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2881 { 2882 u32 *ctx_hdr; 2883 2884 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2885 if (ctx->base.drop_overflow_headers) 2886 return; 2887 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 2888 } 2889 2890 ctx_hdr = ctx->header + ctx->header_length; 2891 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2892 2893 /* 2894 * The two iso header quadlets are byteswapped to little 2895 * endian by the controller, but we want to present them 2896 * as big endian for consistency with the bus endianness. 2897 */ 2898 if (ctx->base.header_size > 0) 2899 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2900 if (ctx->base.header_size > 4) 2901 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2902 if (ctx->base.header_size > 8) 2903 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2904 ctx->header_length += ctx->base.header_size; 2905 } 2906 2907 static int handle_ir_packet_per_buffer(struct context *context, 2908 struct descriptor *d, 2909 struct descriptor *last) 2910 { 2911 struct iso_context *ctx = 2912 container_of(context, struct iso_context, context); 2913 struct descriptor *pd; 2914 u32 buffer_dma; 2915 2916 for (pd = d; pd <= last; pd++) 2917 if (pd->transfer_status) 2918 break; 2919 if (pd > last) 2920 /* Descriptor(s) not done yet, stop iteration */ 2921 return 0; 2922 2923 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2924 d++; 2925 buffer_dma = le32_to_cpu(d->data_address); 2926 dma_sync_single_range_for_cpu(context->ohci->card.device, 2927 buffer_dma & PAGE_MASK, 2928 buffer_dma & ~PAGE_MASK, 2929 le16_to_cpu(d->req_count), 2930 DMA_FROM_DEVICE); 2931 } 2932 2933 copy_iso_headers(ctx, (u32 *) (last + 1)); 2934 2935 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2936 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_INTERRUPT); 2937 2938 return 1; 2939 } 2940 2941 /* d == last because each descriptor block is only a single descriptor. */ 2942 static int handle_ir_buffer_fill(struct context *context, 2943 struct descriptor *d, 2944 struct descriptor *last) 2945 { 2946 struct iso_context *ctx = 2947 container_of(context, struct iso_context, context); 2948 unsigned int req_count, res_count, completed; 2949 u32 buffer_dma; 2950 2951 req_count = le16_to_cpu(last->req_count); 2952 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2953 completed = req_count - res_count; 2954 buffer_dma = le32_to_cpu(last->data_address); 2955 2956 if (completed > 0) { 2957 ctx->mc_buffer_bus = buffer_dma; 2958 ctx->mc_completed = completed; 2959 } 2960 2961 if (res_count != 0) 2962 /* Descriptor(s) not done yet, stop iteration */ 2963 return 0; 2964 2965 dma_sync_single_range_for_cpu(context->ohci->card.device, 2966 buffer_dma & PAGE_MASK, 2967 buffer_dma & ~PAGE_MASK, 2968 completed, DMA_FROM_DEVICE); 2969 2970 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2971 trace_isoc_inbound_multiple_completions(&ctx->base, completed, 2972 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_INTERRUPT); 2973 2974 ctx->base.callback.mc(&ctx->base, 2975 buffer_dma + completed, 2976 ctx->base.callback_data); 2977 ctx->mc_completed = 0; 2978 } 2979 2980 return 1; 2981 } 2982 2983 static void flush_ir_buffer_fill(struct iso_context *ctx) 2984 { 2985 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2986 ctx->mc_buffer_bus & PAGE_MASK, 2987 ctx->mc_buffer_bus & ~PAGE_MASK, 2988 ctx->mc_completed, DMA_FROM_DEVICE); 2989 2990 trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed, 2991 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 2992 2993 ctx->base.callback.mc(&ctx->base, 2994 ctx->mc_buffer_bus + ctx->mc_completed, 2995 ctx->base.callback_data); 2996 ctx->mc_completed = 0; 2997 } 2998 2999 static inline void sync_it_packet_for_cpu(struct context *context, 3000 struct descriptor *pd) 3001 { 3002 __le16 control; 3003 u32 buffer_dma; 3004 3005 /* only packets beginning with OUTPUT_MORE* have data buffers */ 3006 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3007 return; 3008 3009 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 3010 pd += 2; 3011 3012 /* 3013 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 3014 * data buffer is in the context program's coherent page and must not 3015 * be synced. 3016 */ 3017 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 3018 (context->current_bus & PAGE_MASK)) { 3019 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3020 return; 3021 pd++; 3022 } 3023 3024 do { 3025 buffer_dma = le32_to_cpu(pd->data_address); 3026 dma_sync_single_range_for_cpu(context->ohci->card.device, 3027 buffer_dma & PAGE_MASK, 3028 buffer_dma & ~PAGE_MASK, 3029 le16_to_cpu(pd->req_count), 3030 DMA_TO_DEVICE); 3031 control = pd->control; 3032 pd++; 3033 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 3034 } 3035 3036 static int handle_it_packet(struct context *context, 3037 struct descriptor *d, 3038 struct descriptor *last) 3039 { 3040 struct iso_context *ctx = 3041 container_of(context, struct iso_context, context); 3042 struct descriptor *pd; 3043 __be32 *ctx_hdr; 3044 3045 for (pd = d; pd <= last; pd++) 3046 if (pd->transfer_status) 3047 break; 3048 if (pd > last) 3049 /* Descriptor(s) not done yet, stop iteration */ 3050 return 0; 3051 3052 sync_it_packet_for_cpu(context, d); 3053 3054 if (ctx->header_length + 4 > PAGE_SIZE) { 3055 if (ctx->base.drop_overflow_headers) 3056 return 1; 3057 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 3058 } 3059 3060 ctx_hdr = ctx->header + ctx->header_length; 3061 ctx->last_timestamp = le16_to_cpu(last->res_count); 3062 /* Present this value as big-endian to match the receive code */ 3063 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 3064 le16_to_cpu(pd->res_count)); 3065 ctx->header_length += 4; 3066 3067 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 3068 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_INTERRUPT); 3069 3070 return 1; 3071 } 3072 3073 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 3074 { 3075 u32 hi = channels >> 32, lo = channels; 3076 3077 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 3078 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 3079 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 3080 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 3081 ohci->mc_channels = channels; 3082 } 3083 3084 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 3085 int type, int channel, size_t header_size) 3086 { 3087 struct fw_ohci *ohci = fw_ohci(card); 3088 struct iso_context *ctx; 3089 descriptor_callback_t callback; 3090 u64 *channels; 3091 u32 *mask, regs; 3092 int index, ret = -EBUSY; 3093 3094 scoped_guard(spinlock_irq, &ohci->lock) { 3095 switch (type) { 3096 case FW_ISO_CONTEXT_TRANSMIT: 3097 mask = &ohci->it_context_mask; 3098 callback = handle_it_packet; 3099 index = ffs(*mask) - 1; 3100 if (index >= 0) { 3101 *mask &= ~(1 << index); 3102 regs = OHCI1394_IsoXmitContextBase(index); 3103 ctx = &ohci->it_context_list[index]; 3104 } 3105 break; 3106 3107 case FW_ISO_CONTEXT_RECEIVE: 3108 channels = &ohci->ir_context_channels; 3109 mask = &ohci->ir_context_mask; 3110 callback = handle_ir_packet_per_buffer; 3111 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3112 if (index >= 0) { 3113 *channels &= ~(1ULL << channel); 3114 *mask &= ~(1 << index); 3115 regs = OHCI1394_IsoRcvContextBase(index); 3116 ctx = &ohci->ir_context_list[index]; 3117 } 3118 break; 3119 3120 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3121 mask = &ohci->ir_context_mask; 3122 callback = handle_ir_buffer_fill; 3123 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3124 if (index >= 0) { 3125 ohci->mc_allocated = true; 3126 *mask &= ~(1 << index); 3127 regs = OHCI1394_IsoRcvContextBase(index); 3128 ctx = &ohci->ir_context_list[index]; 3129 } 3130 break; 3131 3132 default: 3133 index = -1; 3134 ret = -ENOSYS; 3135 } 3136 3137 if (index < 0) 3138 return ERR_PTR(ret); 3139 } 3140 3141 memset(ctx, 0, sizeof(*ctx)); 3142 ctx->header_length = 0; 3143 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3144 if (ctx->header == NULL) { 3145 ret = -ENOMEM; 3146 goto out; 3147 } 3148 ret = context_init(&ctx->context, ohci, regs, callback); 3149 if (ret < 0) 3150 goto out_with_header; 3151 fw_iso_context_init_work(&ctx->base, ohci_isoc_context_work); 3152 3153 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3154 set_multichannel_mask(ohci, 0); 3155 ctx->mc_completed = 0; 3156 } 3157 3158 return &ctx->base; 3159 3160 out_with_header: 3161 free_page((unsigned long)ctx->header); 3162 out: 3163 scoped_guard(spinlock_irq, &ohci->lock) { 3164 switch (type) { 3165 case FW_ISO_CONTEXT_RECEIVE: 3166 *channels |= 1ULL << channel; 3167 break; 3168 3169 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3170 ohci->mc_allocated = false; 3171 break; 3172 } 3173 *mask |= 1 << index; 3174 } 3175 3176 return ERR_PTR(ret); 3177 } 3178 3179 static int ohci_start_iso(struct fw_iso_context *base, 3180 s32 cycle, u32 sync, u32 tags) 3181 { 3182 struct iso_context *ctx = container_of(base, struct iso_context, base); 3183 struct fw_ohci *ohci = ctx->context.ohci; 3184 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3185 int index; 3186 3187 /* the controller cannot start without any queued packets */ 3188 if (ctx->context.last->branch_address == 0) 3189 return -ENODATA; 3190 3191 switch (ctx->base.type) { 3192 case FW_ISO_CONTEXT_TRANSMIT: 3193 index = ctx - ohci->it_context_list; 3194 match = 0; 3195 if (cycle >= 0) 3196 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3197 (cycle & 0x7fff) << 16; 3198 3199 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3200 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3201 context_run(&ctx->context, match); 3202 break; 3203 3204 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3205 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3206 fallthrough; 3207 case FW_ISO_CONTEXT_RECEIVE: 3208 index = ctx - ohci->ir_context_list; 3209 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3210 if (cycle >= 0) { 3211 match |= (cycle & 0x07fff) << 12; 3212 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3213 } 3214 3215 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3216 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3217 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3218 context_run(&ctx->context, control); 3219 3220 ctx->sync = sync; 3221 ctx->tags = tags; 3222 3223 break; 3224 } 3225 3226 return 0; 3227 } 3228 3229 static int ohci_stop_iso(struct fw_iso_context *base) 3230 { 3231 struct fw_ohci *ohci = fw_ohci(base->card); 3232 struct iso_context *ctx = container_of(base, struct iso_context, base); 3233 int index; 3234 3235 switch (ctx->base.type) { 3236 case FW_ISO_CONTEXT_TRANSMIT: 3237 index = ctx - ohci->it_context_list; 3238 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3239 break; 3240 3241 case FW_ISO_CONTEXT_RECEIVE: 3242 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3243 index = ctx - ohci->ir_context_list; 3244 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3245 break; 3246 } 3247 flush_writes(ohci); 3248 context_stop(&ctx->context); 3249 3250 return 0; 3251 } 3252 3253 static void ohci_free_iso_context(struct fw_iso_context *base) 3254 { 3255 struct fw_ohci *ohci = fw_ohci(base->card); 3256 struct iso_context *ctx = container_of(base, struct iso_context, base); 3257 int index; 3258 3259 ohci_stop_iso(base); 3260 context_release(&ctx->context); 3261 free_page((unsigned long)ctx->header); 3262 3263 guard(spinlock_irqsave)(&ohci->lock); 3264 3265 switch (base->type) { 3266 case FW_ISO_CONTEXT_TRANSMIT: 3267 index = ctx - ohci->it_context_list; 3268 ohci->it_context_mask |= 1 << index; 3269 break; 3270 3271 case FW_ISO_CONTEXT_RECEIVE: 3272 index = ctx - ohci->ir_context_list; 3273 ohci->ir_context_mask |= 1 << index; 3274 ohci->ir_context_channels |= 1ULL << base->channel; 3275 break; 3276 3277 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3278 index = ctx - ohci->ir_context_list; 3279 ohci->ir_context_mask |= 1 << index; 3280 ohci->ir_context_channels |= ohci->mc_channels; 3281 ohci->mc_channels = 0; 3282 ohci->mc_allocated = false; 3283 break; 3284 } 3285 } 3286 3287 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3288 { 3289 struct fw_ohci *ohci = fw_ohci(base->card); 3290 3291 switch (base->type) { 3292 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3293 { 3294 guard(spinlock_irqsave)(&ohci->lock); 3295 3296 // Don't allow multichannel to grab other contexts' channels. 3297 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3298 *channels = ohci->ir_context_channels; 3299 return -EBUSY; 3300 } else { 3301 set_multichannel_mask(ohci, *channels); 3302 return 0; 3303 } 3304 } 3305 default: 3306 return -EINVAL; 3307 } 3308 } 3309 3310 static void __maybe_unused ohci_resume_iso_dma(struct fw_ohci *ohci) 3311 { 3312 int i; 3313 struct iso_context *ctx; 3314 3315 for (i = 0 ; i < ohci->n_ir ; i++) { 3316 ctx = &ohci->ir_context_list[i]; 3317 if (ctx->context.running) 3318 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3319 } 3320 3321 for (i = 0 ; i < ohci->n_it ; i++) { 3322 ctx = &ohci->it_context_list[i]; 3323 if (ctx->context.running) 3324 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3325 } 3326 } 3327 3328 static int queue_iso_transmit(struct iso_context *ctx, 3329 struct fw_iso_packet *packet, 3330 struct fw_iso_buffer *buffer, 3331 unsigned long payload) 3332 { 3333 struct descriptor *d, *last, *pd; 3334 struct fw_iso_packet *p; 3335 __le32 *header; 3336 dma_addr_t d_bus, page_bus; 3337 u32 z, header_z, payload_z, irq; 3338 u32 payload_index, payload_end_index, next_page_index; 3339 int page, end_page, i, length, offset; 3340 3341 p = packet; 3342 payload_index = payload; 3343 3344 if (p->skip) 3345 z = 1; 3346 else 3347 z = 2; 3348 if (p->header_length > 0) 3349 z++; 3350 3351 /* Determine the first page the payload isn't contained in. */ 3352 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3353 if (p->payload_length > 0) 3354 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3355 else 3356 payload_z = 0; 3357 3358 z += payload_z; 3359 3360 /* Get header size in number of descriptors. */ 3361 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3362 3363 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3364 if (d == NULL) 3365 return -ENOMEM; 3366 3367 if (!p->skip) { 3368 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3369 d[0].req_count = cpu_to_le16(8); 3370 /* 3371 * Link the skip address to this descriptor itself. This causes 3372 * a context to skip a cycle whenever lost cycles or FIFO 3373 * overruns occur, without dropping the data. The application 3374 * should then decide whether this is an error condition or not. 3375 * FIXME: Make the context's cycle-lost behaviour configurable? 3376 */ 3377 d[0].branch_address = cpu_to_le32(d_bus | z); 3378 3379 header = (__le32 *) &d[1]; 3380 3381 ohci1394_it_data_set_speed(header, ctx->base.speed); 3382 ohci1394_it_data_set_tag(header, p->tag); 3383 ohci1394_it_data_set_channel(header, ctx->base.channel); 3384 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 3385 ohci1394_it_data_set_sync(header, p->sy); 3386 3387 ohci1394_it_data_set_data_length(header, p->header_length + p->payload_length); 3388 } 3389 3390 if (p->header_length > 0) { 3391 d[2].req_count = cpu_to_le16(p->header_length); 3392 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3393 memcpy(&d[z], p->header, p->header_length); 3394 } 3395 3396 pd = d + z - payload_z; 3397 payload_end_index = payload_index + p->payload_length; 3398 for (i = 0; i < payload_z; i++) { 3399 page = payload_index >> PAGE_SHIFT; 3400 offset = payload_index & ~PAGE_MASK; 3401 next_page_index = (page + 1) << PAGE_SHIFT; 3402 length = 3403 min(next_page_index, payload_end_index) - payload_index; 3404 pd[i].req_count = cpu_to_le16(length); 3405 3406 page_bus = page_private(buffer->pages[page]); 3407 pd[i].data_address = cpu_to_le32(page_bus + offset); 3408 3409 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3410 page_bus, offset, length, 3411 DMA_TO_DEVICE); 3412 3413 payload_index += length; 3414 } 3415 3416 if (p->interrupt) 3417 irq = DESCRIPTOR_IRQ_ALWAYS; 3418 else 3419 irq = DESCRIPTOR_NO_IRQ; 3420 3421 last = z == 2 ? d : d + z - 1; 3422 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3423 DESCRIPTOR_STATUS | 3424 DESCRIPTOR_BRANCH_ALWAYS | 3425 irq); 3426 3427 context_append(&ctx->context, d, z, header_z); 3428 3429 return 0; 3430 } 3431 3432 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3433 struct fw_iso_packet *packet, 3434 struct fw_iso_buffer *buffer, 3435 unsigned long payload) 3436 { 3437 struct device *device = ctx->context.ohci->card.device; 3438 struct descriptor *d, *pd; 3439 dma_addr_t d_bus, page_bus; 3440 u32 z, header_z, rest; 3441 int i, j, length; 3442 int page, offset, packet_count, header_size, payload_per_buffer; 3443 3444 /* 3445 * The OHCI controller puts the isochronous header and trailer in the 3446 * buffer, so we need at least 8 bytes. 3447 */ 3448 packet_count = packet->header_length / ctx->base.header_size; 3449 header_size = max(ctx->base.header_size, (size_t)8); 3450 3451 /* Get header size in number of descriptors. */ 3452 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3453 page = payload >> PAGE_SHIFT; 3454 offset = payload & ~PAGE_MASK; 3455 payload_per_buffer = packet->payload_length / packet_count; 3456 3457 for (i = 0; i < packet_count; i++) { 3458 /* d points to the header descriptor */ 3459 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3460 d = context_get_descriptors(&ctx->context, 3461 z + header_z, &d_bus); 3462 if (d == NULL) 3463 return -ENOMEM; 3464 3465 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3466 DESCRIPTOR_INPUT_MORE); 3467 if (packet->skip && i == 0) 3468 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3469 d->req_count = cpu_to_le16(header_size); 3470 d->res_count = d->req_count; 3471 d->transfer_status = 0; 3472 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3473 3474 rest = payload_per_buffer; 3475 pd = d; 3476 for (j = 1; j < z; j++) { 3477 pd++; 3478 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3479 DESCRIPTOR_INPUT_MORE); 3480 3481 if (offset + rest < PAGE_SIZE) 3482 length = rest; 3483 else 3484 length = PAGE_SIZE - offset; 3485 pd->req_count = cpu_to_le16(length); 3486 pd->res_count = pd->req_count; 3487 pd->transfer_status = 0; 3488 3489 page_bus = page_private(buffer->pages[page]); 3490 pd->data_address = cpu_to_le32(page_bus + offset); 3491 3492 dma_sync_single_range_for_device(device, page_bus, 3493 offset, length, 3494 DMA_FROM_DEVICE); 3495 3496 offset = (offset + length) & ~PAGE_MASK; 3497 rest -= length; 3498 if (offset == 0) 3499 page++; 3500 } 3501 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3502 DESCRIPTOR_INPUT_LAST | 3503 DESCRIPTOR_BRANCH_ALWAYS); 3504 if (packet->interrupt && i == packet_count - 1) 3505 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3506 3507 context_append(&ctx->context, d, z, header_z); 3508 } 3509 3510 return 0; 3511 } 3512 3513 static int queue_iso_buffer_fill(struct iso_context *ctx, 3514 struct fw_iso_packet *packet, 3515 struct fw_iso_buffer *buffer, 3516 unsigned long payload) 3517 { 3518 struct descriptor *d; 3519 dma_addr_t d_bus, page_bus; 3520 int page, offset, rest, z, i, length; 3521 3522 page = payload >> PAGE_SHIFT; 3523 offset = payload & ~PAGE_MASK; 3524 rest = packet->payload_length; 3525 3526 /* We need one descriptor for each page in the buffer. */ 3527 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3528 3529 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3530 return -EFAULT; 3531 3532 for (i = 0; i < z; i++) { 3533 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3534 if (d == NULL) 3535 return -ENOMEM; 3536 3537 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3538 DESCRIPTOR_BRANCH_ALWAYS); 3539 if (packet->skip && i == 0) 3540 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3541 if (packet->interrupt && i == z - 1) 3542 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3543 3544 if (offset + rest < PAGE_SIZE) 3545 length = rest; 3546 else 3547 length = PAGE_SIZE - offset; 3548 d->req_count = cpu_to_le16(length); 3549 d->res_count = d->req_count; 3550 d->transfer_status = 0; 3551 3552 page_bus = page_private(buffer->pages[page]); 3553 d->data_address = cpu_to_le32(page_bus + offset); 3554 3555 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3556 page_bus, offset, length, 3557 DMA_FROM_DEVICE); 3558 3559 rest -= length; 3560 offset = 0; 3561 page++; 3562 3563 context_append(&ctx->context, d, 1, 0); 3564 } 3565 3566 return 0; 3567 } 3568 3569 static int ohci_queue_iso(struct fw_iso_context *base, 3570 struct fw_iso_packet *packet, 3571 struct fw_iso_buffer *buffer, 3572 unsigned long payload) 3573 { 3574 struct iso_context *ctx = container_of(base, struct iso_context, base); 3575 3576 guard(spinlock_irqsave)(&ctx->context.ohci->lock); 3577 3578 switch (base->type) { 3579 case FW_ISO_CONTEXT_TRANSMIT: 3580 return queue_iso_transmit(ctx, packet, buffer, payload); 3581 case FW_ISO_CONTEXT_RECEIVE: 3582 return queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3583 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3584 return queue_iso_buffer_fill(ctx, packet, buffer, payload); 3585 default: 3586 return -ENOSYS; 3587 } 3588 } 3589 3590 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3591 { 3592 struct context *ctx = 3593 &container_of(base, struct iso_context, base)->context; 3594 3595 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3596 } 3597 3598 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3599 { 3600 struct iso_context *ctx = container_of(base, struct iso_context, base); 3601 int ret = 0; 3602 3603 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3604 ohci_isoc_context_work(&base->work); 3605 3606 switch (base->type) { 3607 case FW_ISO_CONTEXT_TRANSMIT: 3608 case FW_ISO_CONTEXT_RECEIVE: 3609 if (ctx->header_length != 0) 3610 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3611 break; 3612 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3613 if (ctx->mc_completed != 0) 3614 flush_ir_buffer_fill(ctx); 3615 break; 3616 default: 3617 ret = -ENOSYS; 3618 } 3619 3620 clear_bit_unlock(0, &ctx->flushing_completions); 3621 smp_mb__after_atomic(); 3622 } 3623 3624 return ret; 3625 } 3626 3627 static const struct fw_card_driver ohci_driver = { 3628 .enable = ohci_enable, 3629 .read_phy_reg = ohci_read_phy_reg, 3630 .update_phy_reg = ohci_update_phy_reg, 3631 .set_config_rom = ohci_set_config_rom, 3632 .send_request = ohci_send_request, 3633 .send_response = ohci_send_response, 3634 .cancel_packet = ohci_cancel_packet, 3635 .enable_phys_dma = ohci_enable_phys_dma, 3636 .read_csr = ohci_read_csr, 3637 .write_csr = ohci_write_csr, 3638 3639 .allocate_iso_context = ohci_allocate_iso_context, 3640 .free_iso_context = ohci_free_iso_context, 3641 .set_iso_channels = ohci_set_iso_channels, 3642 .queue_iso = ohci_queue_iso, 3643 .flush_queue_iso = ohci_flush_queue_iso, 3644 .flush_iso_completions = ohci_flush_iso_completions, 3645 .start_iso = ohci_start_iso, 3646 .stop_iso = ohci_stop_iso, 3647 }; 3648 3649 #ifdef CONFIG_PPC_PMAC 3650 static void pmac_ohci_on(struct pci_dev *dev) 3651 { 3652 if (machine_is(powermac)) { 3653 struct device_node *ofn = pci_device_to_OF_node(dev); 3654 3655 if (ofn) { 3656 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3657 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3658 } 3659 } 3660 } 3661 3662 static void pmac_ohci_off(struct pci_dev *dev) 3663 { 3664 if (machine_is(powermac)) { 3665 struct device_node *ofn = pci_device_to_OF_node(dev); 3666 3667 if (ofn) { 3668 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3669 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3670 } 3671 } 3672 } 3673 #else 3674 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3675 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3676 #endif /* CONFIG_PPC_PMAC */ 3677 3678 static void release_ohci(struct device *dev, void *data) 3679 { 3680 struct pci_dev *pdev = to_pci_dev(dev); 3681 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3682 3683 pmac_ohci_off(pdev); 3684 3685 ar_context_release(&ohci->ar_response_ctx); 3686 ar_context_release(&ohci->ar_request_ctx); 3687 3688 dev_notice(dev, "removed fw-ohci device\n"); 3689 } 3690 3691 static int pci_probe(struct pci_dev *dev, 3692 const struct pci_device_id *ent) 3693 { 3694 struct fw_ohci *ohci; 3695 u32 bus_options, max_receive, link_speed, version; 3696 u64 guid; 3697 int i, flags, irq, err; 3698 size_t size; 3699 3700 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3701 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3702 return -ENOSYS; 3703 } 3704 3705 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3706 if (ohci == NULL) 3707 return -ENOMEM; 3708 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3709 pci_set_drvdata(dev, ohci); 3710 pmac_ohci_on(dev); 3711 devres_add(&dev->dev, ohci); 3712 3713 err = pcim_enable_device(dev); 3714 if (err) { 3715 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3716 return err; 3717 } 3718 3719 pci_set_master(dev); 3720 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3721 3722 spin_lock_init(&ohci->lock); 3723 mutex_init(&ohci->phy_reg_mutex); 3724 3725 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3726 3727 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3728 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3729 ohci_err(ohci, "invalid MMIO resource\n"); 3730 return -ENXIO; 3731 } 3732 3733 ohci->registers = pcim_iomap_region(dev, 0, ohci_driver_name); 3734 if (IS_ERR(ohci->registers)) { 3735 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3736 return -ENXIO; 3737 } 3738 3739 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3740 if ((ohci_quirks[i].vendor == dev->vendor) && 3741 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3742 ohci_quirks[i].device == dev->device) && 3743 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3744 ohci_quirks[i].revision >= dev->revision)) { 3745 ohci->quirks = ohci_quirks[i].flags; 3746 break; 3747 } 3748 if (param_quirks) 3749 ohci->quirks = param_quirks; 3750 3751 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3752 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3753 3754 /* 3755 * Because dma_alloc_coherent() allocates at least one page, 3756 * we save space by using a common buffer for the AR request/ 3757 * response descriptors and the self IDs buffer. 3758 */ 3759 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3760 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3761 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3762 GFP_KERNEL); 3763 if (!ohci->misc_buffer) 3764 return -ENOMEM; 3765 3766 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3767 OHCI1394_AsReqRcvContextControlSet); 3768 if (err < 0) 3769 return err; 3770 3771 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3772 OHCI1394_AsRspRcvContextControlSet); 3773 if (err < 0) 3774 return err; 3775 3776 err = context_init(&ohci->at_request_ctx.context, ohci, 3777 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3778 if (err < 0) 3779 return err; 3780 INIT_WORK(&ohci->at_request_ctx.work, ohci_at_context_work); 3781 3782 err = context_init(&ohci->at_response_ctx.context, ohci, 3783 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3784 if (err < 0) 3785 return err; 3786 INIT_WORK(&ohci->at_response_ctx.work, ohci_at_context_work); 3787 3788 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3789 ohci->ir_context_channels = ~0ULL; 3790 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3791 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3792 ohci->ir_context_mask = ohci->ir_context_support; 3793 ohci->n_ir = hweight32(ohci->ir_context_mask); 3794 size = sizeof(struct iso_context) * ohci->n_ir; 3795 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3796 if (!ohci->ir_context_list) 3797 return -ENOMEM; 3798 3799 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3800 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3801 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3802 if (!ohci->it_context_support) { 3803 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3804 ohci->it_context_support = 0xf; 3805 } 3806 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3807 ohci->it_context_mask = ohci->it_context_support; 3808 ohci->n_it = hweight32(ohci->it_context_mask); 3809 size = sizeof(struct iso_context) * ohci->n_it; 3810 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3811 if (!ohci->it_context_list) 3812 return -ENOMEM; 3813 3814 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3815 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3816 3817 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3818 max_receive = (bus_options >> 12) & 0xf; 3819 link_speed = bus_options & 0x7; 3820 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3821 reg_read(ohci, OHCI1394_GUIDLo); 3822 3823 flags = PCI_IRQ_INTX; 3824 if (!(ohci->quirks & QUIRK_NO_MSI)) 3825 flags |= PCI_IRQ_MSI; 3826 err = pci_alloc_irq_vectors(dev, 1, 1, flags); 3827 if (err < 0) 3828 return err; 3829 irq = pci_irq_vector(dev, 0); 3830 if (irq < 0) { 3831 err = irq; 3832 goto fail_msi; 3833 } 3834 3835 err = request_threaded_irq(irq, irq_handler, NULL, 3836 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, 3837 ohci); 3838 if (err < 0) { 3839 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); 3840 goto fail_msi; 3841 } 3842 3843 err = fw_card_add(&ohci->card, max_receive, link_speed, guid, ohci->n_it + ohci->n_ir); 3844 if (err) 3845 goto fail_irq; 3846 3847 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3848 ohci_notice(ohci, 3849 "added OHCI v%x.%x device as card %d, " 3850 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3851 version >> 16, version & 0xff, ohci->card.index, 3852 ohci->n_ir, ohci->n_it, ohci->quirks, 3853 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3854 ", physUB" : ""); 3855 3856 return 0; 3857 3858 fail_irq: 3859 free_irq(irq, ohci); 3860 fail_msi: 3861 pci_free_irq_vectors(dev); 3862 3863 return err; 3864 } 3865 3866 static void pci_remove(struct pci_dev *dev) 3867 { 3868 struct fw_ohci *ohci = pci_get_drvdata(dev); 3869 int irq; 3870 3871 /* 3872 * If the removal is happening from the suspend state, LPS won't be 3873 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3874 */ 3875 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3876 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3877 flush_writes(ohci); 3878 } 3879 cancel_work_sync(&ohci->bus_reset_work); 3880 fw_core_remove_card(&ohci->card); 3881 3882 /* 3883 * FIXME: Fail all pending packets here, now that the upper 3884 * layers can't queue any more. 3885 */ 3886 3887 software_reset(ohci); 3888 3889 irq = pci_irq_vector(dev, 0); 3890 if (irq >= 0) 3891 free_irq(irq, ohci); 3892 pci_free_irq_vectors(dev); 3893 3894 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3895 } 3896 3897 static int __maybe_unused pci_suspend(struct device *dev) 3898 { 3899 struct pci_dev *pdev = to_pci_dev(dev); 3900 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3901 3902 software_reset(ohci); 3903 pmac_ohci_off(pdev); 3904 3905 return 0; 3906 } 3907 3908 3909 static int __maybe_unused pci_resume(struct device *dev) 3910 { 3911 struct pci_dev *pdev = to_pci_dev(dev); 3912 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3913 int err; 3914 3915 pmac_ohci_on(pdev); 3916 3917 /* Some systems don't setup GUID register on resume from ram */ 3918 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3919 !reg_read(ohci, OHCI1394_GUIDHi)) { 3920 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3921 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3922 } 3923 3924 err = ohci_enable(&ohci->card, NULL, 0); 3925 if (err) 3926 return err; 3927 3928 ohci_resume_iso_dma(ohci); 3929 3930 return 0; 3931 } 3932 3933 static const struct pci_device_id pci_table[] = { 3934 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3935 { } 3936 }; 3937 3938 MODULE_DEVICE_TABLE(pci, pci_table); 3939 3940 static SIMPLE_DEV_PM_OPS(pci_pm_ops, pci_suspend, pci_resume); 3941 3942 static struct pci_driver fw_ohci_pci_driver = { 3943 .name = ohci_driver_name, 3944 .id_table = pci_table, 3945 .probe = pci_probe, 3946 .remove = pci_remove, 3947 .driver.pm = &pci_pm_ops, 3948 }; 3949 3950 static int __init fw_ohci_init(void) 3951 { 3952 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3953 if (!selfid_workqueue) 3954 return -ENOMEM; 3955 3956 return pci_register_driver(&fw_ohci_pci_driver); 3957 } 3958 3959 static void __exit fw_ohci_cleanup(void) 3960 { 3961 pci_unregister_driver(&fw_ohci_pci_driver); 3962 destroy_workqueue(selfid_workqueue); 3963 } 3964 3965 module_init(fw_ohci_init); 3966 module_exit(fw_ohci_cleanup); 3967 3968 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3969 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3970 MODULE_LICENSE("GPL"); 3971 3972 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3973 MODULE_ALIAS("ohci1394"); 3974