1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 #include "packet-header-definitions.h" 44 #include "phy-packet-definitions.h" 45 46 #include <trace/events/firewire.h> 47 48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/firewire_ohci.h> 52 53 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 54 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 55 56 #define DESCRIPTOR_OUTPUT_MORE 0 57 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 58 #define DESCRIPTOR_INPUT_MORE (2 << 12) 59 #define DESCRIPTOR_INPUT_LAST (3 << 12) 60 #define DESCRIPTOR_STATUS (1 << 11) 61 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 62 #define DESCRIPTOR_PING (1 << 7) 63 #define DESCRIPTOR_YY (1 << 6) 64 #define DESCRIPTOR_NO_IRQ (0 << 4) 65 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 66 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 67 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 68 #define DESCRIPTOR_WAIT (3 << 0) 69 70 #define DESCRIPTOR_CMD (0xf << 12) 71 72 struct descriptor { 73 __le16 req_count; 74 __le16 control; 75 __le32 data_address; 76 __le32 branch_address; 77 __le16 res_count; 78 __le16 transfer_status; 79 } __aligned(16); 80 81 #define CONTROL_SET(regs) (regs) 82 #define CONTROL_CLEAR(regs) ((regs) + 4) 83 #define COMMAND_PTR(regs) ((regs) + 12) 84 #define CONTEXT_MATCH(regs) ((regs) + 16) 85 86 #define AR_BUFFER_SIZE (32*1024) 87 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 88 /* we need at least two pages for proper list management */ 89 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 90 91 #define MAX_ASYNC_PAYLOAD 4096 92 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 93 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 94 95 struct ar_context { 96 struct fw_ohci *ohci; 97 struct page *pages[AR_BUFFERS]; 98 void *buffer; 99 struct descriptor *descriptors; 100 dma_addr_t descriptors_bus; 101 void *pointer; 102 unsigned int last_buffer_index; 103 u32 regs; 104 struct tasklet_struct tasklet; 105 }; 106 107 struct context; 108 109 typedef int (*descriptor_callback_t)(struct context *ctx, 110 struct descriptor *d, 111 struct descriptor *last); 112 113 /* 114 * A buffer that contains a block of DMA-able coherent memory used for 115 * storing a portion of a DMA descriptor program. 116 */ 117 struct descriptor_buffer { 118 struct list_head list; 119 dma_addr_t buffer_bus; 120 size_t buffer_size; 121 size_t used; 122 struct descriptor buffer[]; 123 }; 124 125 struct context { 126 struct fw_ohci *ohci; 127 u32 regs; 128 int total_allocation; 129 u32 current_bus; 130 bool running; 131 bool flushing; 132 133 /* 134 * List of page-sized buffers for storing DMA descriptors. 135 * Head of list contains buffers in use and tail of list contains 136 * free buffers. 137 */ 138 struct list_head buffer_list; 139 140 /* 141 * Pointer to a buffer inside buffer_list that contains the tail 142 * end of the current DMA program. 143 */ 144 struct descriptor_buffer *buffer_tail; 145 146 /* 147 * The descriptor containing the branch address of the first 148 * descriptor that has not yet been filled by the device. 149 */ 150 struct descriptor *last; 151 152 /* 153 * The last descriptor block in the DMA program. It contains the branch 154 * address that must be updated upon appending a new descriptor. 155 */ 156 struct descriptor *prev; 157 int prev_z; 158 159 descriptor_callback_t callback; 160 161 struct tasklet_struct tasklet; 162 }; 163 164 struct iso_context { 165 struct fw_iso_context base; 166 struct context context; 167 void *header; 168 size_t header_length; 169 unsigned long flushing_completions; 170 u32 mc_buffer_bus; 171 u16 mc_completed; 172 u16 last_timestamp; 173 u8 sync; 174 u8 tags; 175 }; 176 177 #define CONFIG_ROM_SIZE (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM) 178 179 struct fw_ohci { 180 struct fw_card card; 181 182 __iomem char *registers; 183 int node_id; 184 int generation; 185 int request_generation; /* for timestamping incoming requests */ 186 unsigned quirks; 187 unsigned int pri_req_max; 188 u32 bus_time; 189 bool bus_time_running; 190 bool is_root; 191 bool csr_state_setclear_abdicate; 192 int n_ir; 193 int n_it; 194 /* 195 * Spinlock for accessing fw_ohci data. Never call out of 196 * this driver with this lock held. 197 */ 198 spinlock_t lock; 199 200 struct mutex phy_reg_mutex; 201 202 void *misc_buffer; 203 dma_addr_t misc_buffer_bus; 204 205 struct ar_context ar_request_ctx; 206 struct ar_context ar_response_ctx; 207 struct context at_request_ctx; 208 struct context at_response_ctx; 209 210 u32 it_context_support; 211 u32 it_context_mask; /* unoccupied IT contexts */ 212 struct iso_context *it_context_list; 213 u64 ir_context_channels; /* unoccupied channels */ 214 u32 ir_context_support; 215 u32 ir_context_mask; /* unoccupied IR contexts */ 216 struct iso_context *ir_context_list; 217 u64 mc_channels; /* channels in use by the multichannel IR context */ 218 bool mc_allocated; 219 220 __be32 *config_rom; 221 dma_addr_t config_rom_bus; 222 __be32 *next_config_rom; 223 dma_addr_t next_config_rom_bus; 224 __be32 next_header; 225 226 __le32 *self_id; 227 dma_addr_t self_id_bus; 228 struct work_struct bus_reset_work; 229 230 u32 self_id_buffer[512]; 231 }; 232 233 static struct workqueue_struct *selfid_workqueue; 234 235 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 236 { 237 return container_of(card, struct fw_ohci, card); 238 } 239 240 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 241 #define IR_CONTEXT_BUFFER_FILL 0x80000000 242 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 243 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 244 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 245 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 246 247 #define CONTEXT_RUN 0x8000 248 #define CONTEXT_WAKE 0x1000 249 #define CONTEXT_DEAD 0x0800 250 #define CONTEXT_ACTIVE 0x0400 251 252 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 253 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 254 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 255 256 #define OHCI1394_REGISTER_SIZE 0x800 257 #define OHCI1394_PCI_HCI_Control 0x40 258 #define SELF_ID_BUF_SIZE 0x800 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 265 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 267 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 268 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 269 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 270 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 271 #define PCI_REV_ID_VIA_VT6306 0x46 272 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 273 274 #define QUIRK_CYCLE_TIMER 0x1 275 #define QUIRK_RESET_PACKET 0x2 276 #define QUIRK_BE_HEADERS 0x4 277 #define QUIRK_NO_1394A 0x8 278 #define QUIRK_NO_MSI 0x10 279 #define QUIRK_TI_SLLZ059 0x20 280 #define QUIRK_IR_WAKE 0x40 281 282 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 283 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 284 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 285 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 286 // while it is probable due to detection of any type of PCIe error. 287 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 288 289 #if IS_ENABLED(CONFIG_X86) 290 291 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 292 { 293 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 294 } 295 296 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 297 298 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 299 { 300 const struct pci_dev *pcie_to_pci_bridge; 301 302 // Detect any type of AMD Ryzen machine. 303 if (!static_cpu_has(X86_FEATURE_ZEN)) 304 return false; 305 306 // Detect VIA VT6306/6307/6308. 307 if (pdev->vendor != PCI_VENDOR_ID_VIA) 308 return false; 309 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 310 return false; 311 312 // Detect Asmedia ASM1083/1085. 313 pcie_to_pci_bridge = pdev->bus->self; 314 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 315 return false; 316 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 317 return false; 318 319 return true; 320 } 321 322 #else 323 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 324 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 325 #endif 326 327 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 328 static const struct { 329 unsigned short vendor, device, revision, flags; 330 } ohci_quirks[] = { 331 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 332 QUIRK_CYCLE_TIMER}, 333 334 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 335 QUIRK_BE_HEADERS}, 336 337 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 338 QUIRK_NO_MSI}, 339 340 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 341 QUIRK_RESET_PACKET}, 342 343 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 344 QUIRK_NO_MSI}, 345 346 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 347 QUIRK_CYCLE_TIMER}, 348 349 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 350 QUIRK_NO_MSI}, 351 352 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 353 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 354 355 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 356 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 357 358 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 359 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 360 361 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 362 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 363 364 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 365 QUIRK_RESET_PACKET}, 366 367 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 368 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 369 370 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 371 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 372 373 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 374 QUIRK_NO_MSI}, 375 376 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 377 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 378 }; 379 380 /* This overrides anything that was found in ohci_quirks[]. */ 381 static int param_quirks; 382 module_param_named(quirks, param_quirks, int, 0644); 383 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 384 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 385 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 386 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 387 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 388 ", disable MSI = " __stringify(QUIRK_NO_MSI) 389 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 390 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 391 ")"); 392 393 #define OHCI_PARAM_DEBUG_AT_AR 1 394 #define OHCI_PARAM_DEBUG_SELFIDS 2 395 #define OHCI_PARAM_DEBUG_IRQS 4 396 397 static int param_debug; 398 module_param_named(debug, param_debug, int, 0644); 399 MODULE_PARM_DESC(debug, "Verbose logging, deprecated in v6.11 kernel or later. (default = 0" 400 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 401 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 402 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 403 ", or a combination, or all = -1)"); 404 405 static bool param_remote_dma; 406 module_param_named(remote_dma, param_remote_dma, bool, 0444); 407 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 408 409 static void log_irqs(struct fw_ohci *ohci, u32 evt) 410 { 411 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) 412 return; 413 414 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 415 evt & OHCI1394_selfIDComplete ? " selfID" : "", 416 evt & OHCI1394_RQPkt ? " AR_req" : "", 417 evt & OHCI1394_RSPkt ? " AR_resp" : "", 418 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 419 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 420 evt & OHCI1394_isochRx ? " IR" : "", 421 evt & OHCI1394_isochTx ? " IT" : "", 422 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 423 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 424 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 425 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 426 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 427 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 428 evt & OHCI1394_busReset ? " busReset" : "", 429 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 430 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 431 OHCI1394_respTxComplete | OHCI1394_isochRx | 432 OHCI1394_isochTx | OHCI1394_postedWriteErr | 433 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 434 OHCI1394_cycleInconsistent | 435 OHCI1394_regAccessFail | OHCI1394_busReset) 436 ? " ?" : ""); 437 } 438 439 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 440 { 441 static const char *const speed[] = { 442 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 443 }; 444 static const char *const power[] = { 445 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 446 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 447 }; 448 static const char port[] = { 449 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.', 450 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-', 451 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p', 452 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c', 453 }; 454 struct self_id_sequence_enumerator enumerator = { 455 .cursor = ohci->self_id_buffer, 456 .quadlet_count = self_id_count, 457 }; 458 459 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 460 return; 461 462 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 463 self_id_count, generation, ohci->node_id); 464 465 while (enumerator.quadlet_count > 0) { 466 unsigned int quadlet_count; 467 unsigned int port_index; 468 const u32 *s; 469 int i; 470 471 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count); 472 if (IS_ERR(s)) 473 break; 474 475 ohci_notice(ohci, 476 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 477 *s, 478 phy_packet_self_id_get_phy_id(*s), 479 port[self_id_sequence_get_port_status(s, quadlet_count, 0)], 480 port[self_id_sequence_get_port_status(s, quadlet_count, 1)], 481 port[self_id_sequence_get_port_status(s, quadlet_count, 2)], 482 speed[*s >> 14 & 3], *s >> 16 & 63, 483 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 484 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 485 486 port_index = 3; 487 for (i = 1; i < quadlet_count; ++i) { 488 ohci_notice(ohci, 489 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 490 s[i], 491 phy_packet_self_id_get_phy_id(s[i]), 492 port[self_id_sequence_get_port_status(s, quadlet_count, port_index)], 493 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)], 494 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)], 495 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)], 496 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)], 497 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)], 498 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)], 499 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)] 500 ); 501 502 port_index += 8; 503 } 504 } 505 } 506 507 static const char *evts[] = { 508 [0x00] = "evt_no_status", [0x01] = "-reserved-", 509 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 510 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 511 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 512 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 513 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 514 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 515 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 516 [0x10] = "-reserved-", [0x11] = "ack_complete", 517 [0x12] = "ack_pending ", [0x13] = "-reserved-", 518 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 519 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 520 [0x18] = "-reserved-", [0x19] = "-reserved-", 521 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 522 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 523 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 524 [0x20] = "pending/cancelled", 525 }; 526 527 static void log_ar_at_event(struct fw_ohci *ohci, 528 char dir, int speed, u32 *header, int evt) 529 { 530 static const char *const tcodes[] = { 531 [TCODE_WRITE_QUADLET_REQUEST] = "QW req", 532 [TCODE_WRITE_BLOCK_REQUEST] = "BW req", 533 [TCODE_WRITE_RESPONSE] = "W resp", 534 [0x3] = "-reserved-", 535 [TCODE_READ_QUADLET_REQUEST] = "QR req", 536 [TCODE_READ_BLOCK_REQUEST] = "BR req", 537 [TCODE_READ_QUADLET_RESPONSE] = "QR resp", 538 [TCODE_READ_BLOCK_RESPONSE] = "BR resp", 539 [TCODE_CYCLE_START] = "cycle start", 540 [TCODE_LOCK_REQUEST] = "Lk req", 541 [TCODE_STREAM_DATA] = "async stream packet", 542 [TCODE_LOCK_RESPONSE] = "Lk resp", 543 [0xc] = "-reserved-", 544 [0xd] = "-reserved-", 545 [TCODE_LINK_INTERNAL] = "link internal", 546 [0xf] = "-reserved-", 547 }; 548 int tcode = async_header_get_tcode(header); 549 char specific[12]; 550 551 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 552 return; 553 554 if (unlikely(evt >= ARRAY_SIZE(evts))) 555 evt = 0x1f; 556 557 if (evt == OHCI1394_evt_bus_reset) { 558 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 559 dir, (header[2] >> 16) & 0xff); 560 return; 561 } 562 563 switch (tcode) { 564 case TCODE_WRITE_QUADLET_REQUEST: 565 case TCODE_READ_QUADLET_RESPONSE: 566 case TCODE_CYCLE_START: 567 snprintf(specific, sizeof(specific), " = %08x", 568 be32_to_cpu((__force __be32)header[3])); 569 break; 570 case TCODE_WRITE_BLOCK_REQUEST: 571 case TCODE_READ_BLOCK_REQUEST: 572 case TCODE_READ_BLOCK_RESPONSE: 573 case TCODE_LOCK_REQUEST: 574 case TCODE_LOCK_RESPONSE: 575 snprintf(specific, sizeof(specific), " %x,%x", 576 async_header_get_data_length(header), 577 async_header_get_extended_tcode(header)); 578 break; 579 default: 580 specific[0] = '\0'; 581 } 582 583 switch (tcode) { 584 case TCODE_STREAM_DATA: 585 ohci_notice(ohci, "A%c %s, %s\n", 586 dir, evts[evt], tcodes[tcode]); 587 break; 588 case TCODE_LINK_INTERNAL: 589 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 590 dir, evts[evt], header[1], header[2]); 591 break; 592 case TCODE_WRITE_QUADLET_REQUEST: 593 case TCODE_WRITE_BLOCK_REQUEST: 594 case TCODE_READ_QUADLET_REQUEST: 595 case TCODE_READ_BLOCK_REQUEST: 596 case TCODE_LOCK_REQUEST: 597 ohci_notice(ohci, 598 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n", 599 dir, speed, async_header_get_tlabel(header), 600 async_header_get_source(header), async_header_get_destination(header), 601 evts[evt], tcodes[tcode], async_header_get_offset(header), specific); 602 break; 603 default: 604 ohci_notice(ohci, 605 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 606 dir, speed, async_header_get_tlabel(header), 607 async_header_get_source(header), async_header_get_destination(header), 608 evts[evt], tcodes[tcode], specific); 609 } 610 } 611 612 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 613 { 614 writel(data, ohci->registers + offset); 615 } 616 617 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 618 { 619 return readl(ohci->registers + offset); 620 } 621 622 static inline void flush_writes(const struct fw_ohci *ohci) 623 { 624 /* Do a dummy read to flush writes. */ 625 reg_read(ohci, OHCI1394_Version); 626 } 627 628 /* 629 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 630 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 631 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 632 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 633 */ 634 static int read_phy_reg(struct fw_ohci *ohci, int addr) 635 { 636 u32 val; 637 int i; 638 639 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 640 for (i = 0; i < 3 + 100; i++) { 641 val = reg_read(ohci, OHCI1394_PhyControl); 642 if (!~val) 643 return -ENODEV; /* Card was ejected. */ 644 645 if (val & OHCI1394_PhyControl_ReadDone) 646 return OHCI1394_PhyControl_ReadData(val); 647 648 /* 649 * Try a few times without waiting. Sleeping is necessary 650 * only when the link/PHY interface is busy. 651 */ 652 if (i >= 3) 653 msleep(1); 654 } 655 ohci_err(ohci, "failed to read phy reg %d\n", addr); 656 dump_stack(); 657 658 return -EBUSY; 659 } 660 661 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 662 { 663 int i; 664 665 reg_write(ohci, OHCI1394_PhyControl, 666 OHCI1394_PhyControl_Write(addr, val)); 667 for (i = 0; i < 3 + 100; i++) { 668 val = reg_read(ohci, OHCI1394_PhyControl); 669 if (!~val) 670 return -ENODEV; /* Card was ejected. */ 671 672 if (!(val & OHCI1394_PhyControl_WritePending)) 673 return 0; 674 675 if (i >= 3) 676 msleep(1); 677 } 678 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 679 dump_stack(); 680 681 return -EBUSY; 682 } 683 684 static int update_phy_reg(struct fw_ohci *ohci, int addr, 685 int clear_bits, int set_bits) 686 { 687 int ret = read_phy_reg(ohci, addr); 688 if (ret < 0) 689 return ret; 690 691 /* 692 * The interrupt status bits are cleared by writing a one bit. 693 * Avoid clearing them unless explicitly requested in set_bits. 694 */ 695 if (addr == 5) 696 clear_bits |= PHY_INT_STATUS_BITS; 697 698 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 699 } 700 701 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 702 { 703 int ret; 704 705 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 706 if (ret < 0) 707 return ret; 708 709 return read_phy_reg(ohci, addr); 710 } 711 712 static int ohci_read_phy_reg(struct fw_card *card, int addr) 713 { 714 struct fw_ohci *ohci = fw_ohci(card); 715 716 guard(mutex)(&ohci->phy_reg_mutex); 717 718 return read_phy_reg(ohci, addr); 719 } 720 721 static int ohci_update_phy_reg(struct fw_card *card, int addr, 722 int clear_bits, int set_bits) 723 { 724 struct fw_ohci *ohci = fw_ohci(card); 725 726 guard(mutex)(&ohci->phy_reg_mutex); 727 728 return update_phy_reg(ohci, addr, clear_bits, set_bits); 729 } 730 731 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 732 { 733 return page_private(ctx->pages[i]); 734 } 735 736 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 737 { 738 struct descriptor *d; 739 740 d = &ctx->descriptors[index]; 741 d->branch_address &= cpu_to_le32(~0xf); 742 d->res_count = cpu_to_le16(PAGE_SIZE); 743 d->transfer_status = 0; 744 745 wmb(); /* finish init of new descriptors before branch_address update */ 746 d = &ctx->descriptors[ctx->last_buffer_index]; 747 d->branch_address |= cpu_to_le32(1); 748 749 ctx->last_buffer_index = index; 750 751 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 752 } 753 754 static void ar_context_release(struct ar_context *ctx) 755 { 756 struct device *dev = ctx->ohci->card.device; 757 unsigned int i; 758 759 if (!ctx->buffer) 760 return; 761 762 vunmap(ctx->buffer); 763 764 for (i = 0; i < AR_BUFFERS; i++) { 765 if (ctx->pages[i]) 766 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 767 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 768 } 769 } 770 771 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 772 { 773 struct fw_ohci *ohci = ctx->ohci; 774 775 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 776 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 777 flush_writes(ohci); 778 779 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 780 } 781 /* FIXME: restart? */ 782 } 783 784 static inline unsigned int ar_next_buffer_index(unsigned int index) 785 { 786 return (index + 1) % AR_BUFFERS; 787 } 788 789 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 790 { 791 return ar_next_buffer_index(ctx->last_buffer_index); 792 } 793 794 /* 795 * We search for the buffer that contains the last AR packet DMA data written 796 * by the controller. 797 */ 798 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 799 unsigned int *buffer_offset) 800 { 801 unsigned int i, next_i, last = ctx->last_buffer_index; 802 __le16 res_count, next_res_count; 803 804 i = ar_first_buffer_index(ctx); 805 res_count = READ_ONCE(ctx->descriptors[i].res_count); 806 807 /* A buffer that is not yet completely filled must be the last one. */ 808 while (i != last && res_count == 0) { 809 810 /* Peek at the next descriptor. */ 811 next_i = ar_next_buffer_index(i); 812 rmb(); /* read descriptors in order */ 813 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 814 /* 815 * If the next descriptor is still empty, we must stop at this 816 * descriptor. 817 */ 818 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 819 /* 820 * The exception is when the DMA data for one packet is 821 * split over three buffers; in this case, the middle 822 * buffer's descriptor might be never updated by the 823 * controller and look still empty, and we have to peek 824 * at the third one. 825 */ 826 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 827 next_i = ar_next_buffer_index(next_i); 828 rmb(); 829 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 830 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 831 goto next_buffer_is_active; 832 } 833 834 break; 835 } 836 837 next_buffer_is_active: 838 i = next_i; 839 res_count = next_res_count; 840 } 841 842 rmb(); /* read res_count before the DMA data */ 843 844 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 845 if (*buffer_offset > PAGE_SIZE) { 846 *buffer_offset = 0; 847 ar_context_abort(ctx, "corrupted descriptor"); 848 } 849 850 return i; 851 } 852 853 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 854 unsigned int end_buffer_index, 855 unsigned int end_buffer_offset) 856 { 857 unsigned int i; 858 859 i = ar_first_buffer_index(ctx); 860 while (i != end_buffer_index) { 861 dma_sync_single_for_cpu(ctx->ohci->card.device, 862 ar_buffer_bus(ctx, i), 863 PAGE_SIZE, DMA_FROM_DEVICE); 864 i = ar_next_buffer_index(i); 865 } 866 if (end_buffer_offset > 0) 867 dma_sync_single_for_cpu(ctx->ohci->card.device, 868 ar_buffer_bus(ctx, i), 869 end_buffer_offset, DMA_FROM_DEVICE); 870 } 871 872 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 873 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk) 874 { 875 return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value); 876 } 877 878 static bool has_be_header_quirk(const struct fw_ohci *ohci) 879 { 880 return !!(ohci->quirks & QUIRK_BE_HEADERS); 881 } 882 #else 883 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused) 884 { 885 return le32_to_cpu(value); 886 } 887 888 static bool has_be_header_quirk(const struct fw_ohci *ohci) 889 { 890 return false; 891 } 892 #endif 893 894 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 895 { 896 struct fw_ohci *ohci = ctx->ohci; 897 struct fw_packet p; 898 u32 status, length, tcode; 899 int evt; 900 901 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); 902 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); 903 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); 904 905 tcode = async_header_get_tcode(p.header); 906 switch (tcode) { 907 case TCODE_WRITE_QUADLET_REQUEST: 908 case TCODE_READ_QUADLET_RESPONSE: 909 p.header[3] = (__force __u32) buffer[3]; 910 p.header_length = 16; 911 p.payload_length = 0; 912 break; 913 914 case TCODE_READ_BLOCK_REQUEST : 915 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 916 p.header_length = 16; 917 p.payload_length = 0; 918 break; 919 920 case TCODE_WRITE_BLOCK_REQUEST: 921 case TCODE_READ_BLOCK_RESPONSE: 922 case TCODE_LOCK_REQUEST: 923 case TCODE_LOCK_RESPONSE: 924 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 925 p.header_length = 16; 926 p.payload_length = async_header_get_data_length(p.header); 927 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 928 ar_context_abort(ctx, "invalid packet length"); 929 return NULL; 930 } 931 break; 932 933 case TCODE_WRITE_RESPONSE: 934 case TCODE_READ_QUADLET_REQUEST: 935 case TCODE_LINK_INTERNAL: 936 p.header_length = 12; 937 p.payload_length = 0; 938 break; 939 940 default: 941 ar_context_abort(ctx, "invalid tcode"); 942 return NULL; 943 } 944 945 p.payload = (void *) buffer + p.header_length; 946 947 /* FIXME: What to do about evt_* errors? */ 948 length = (p.header_length + p.payload_length + 3) / 4; 949 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); 950 evt = (status >> 16) & 0x1f; 951 952 p.ack = evt - 16; 953 p.speed = (status >> 21) & 0x7; 954 p.timestamp = status & 0xffff; 955 p.generation = ohci->request_generation; 956 957 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 958 959 /* 960 * Several controllers, notably from NEC and VIA, forget to 961 * write ack_complete status at PHY packet reception. 962 */ 963 if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL) 964 p.ack = ACK_COMPLETE; 965 966 /* 967 * The OHCI bus reset handler synthesizes a PHY packet with 968 * the new generation number when a bus reset happens (see 969 * section 8.4.2.3). This helps us determine when a request 970 * was received and make sure we send the response in the same 971 * generation. We only need this for requests; for responses 972 * we use the unique tlabel for finding the matching 973 * request. 974 * 975 * Alas some chips sometimes emit bus reset packets with a 976 * wrong generation. We set the correct generation for these 977 * at a slightly incorrect time (in bus_reset_work). 978 */ 979 if (evt == OHCI1394_evt_bus_reset) { 980 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 981 ohci->request_generation = (p.header[2] >> 16) & 0xff; 982 } else if (ctx == &ohci->ar_request_ctx) { 983 fw_core_handle_request(&ohci->card, &p); 984 } else { 985 fw_core_handle_response(&ohci->card, &p); 986 } 987 988 return buffer + length + 1; 989 } 990 991 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 992 { 993 void *next; 994 995 while (p < end) { 996 next = handle_ar_packet(ctx, p); 997 if (!next) 998 return p; 999 p = next; 1000 } 1001 1002 return p; 1003 } 1004 1005 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 1006 { 1007 unsigned int i; 1008 1009 i = ar_first_buffer_index(ctx); 1010 while (i != end_buffer) { 1011 dma_sync_single_for_device(ctx->ohci->card.device, 1012 ar_buffer_bus(ctx, i), 1013 PAGE_SIZE, DMA_FROM_DEVICE); 1014 ar_context_link_page(ctx, i); 1015 i = ar_next_buffer_index(i); 1016 } 1017 } 1018 1019 static void ar_context_tasklet(unsigned long data) 1020 { 1021 struct ar_context *ctx = (struct ar_context *)data; 1022 unsigned int end_buffer_index, end_buffer_offset; 1023 void *p, *end; 1024 1025 p = ctx->pointer; 1026 if (!p) 1027 return; 1028 1029 end_buffer_index = ar_search_last_active_buffer(ctx, 1030 &end_buffer_offset); 1031 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 1032 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 1033 1034 if (end_buffer_index < ar_first_buffer_index(ctx)) { 1035 /* 1036 * The filled part of the overall buffer wraps around; handle 1037 * all packets up to the buffer end here. If the last packet 1038 * wraps around, its tail will be visible after the buffer end 1039 * because the buffer start pages are mapped there again. 1040 */ 1041 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 1042 p = handle_ar_packets(ctx, p, buffer_end); 1043 if (p < buffer_end) 1044 goto error; 1045 /* adjust p to point back into the actual buffer */ 1046 p -= AR_BUFFERS * PAGE_SIZE; 1047 } 1048 1049 p = handle_ar_packets(ctx, p, end); 1050 if (p != end) { 1051 if (p > end) 1052 ar_context_abort(ctx, "inconsistent descriptor"); 1053 goto error; 1054 } 1055 1056 ctx->pointer = p; 1057 ar_recycle_buffers(ctx, end_buffer_index); 1058 1059 return; 1060 1061 error: 1062 ctx->pointer = NULL; 1063 } 1064 1065 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1066 unsigned int descriptors_offset, u32 regs) 1067 { 1068 struct device *dev = ohci->card.device; 1069 unsigned int i; 1070 dma_addr_t dma_addr; 1071 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1072 struct descriptor *d; 1073 1074 ctx->regs = regs; 1075 ctx->ohci = ohci; 1076 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1077 1078 for (i = 0; i < AR_BUFFERS; i++) { 1079 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1080 DMA_FROM_DEVICE, GFP_KERNEL); 1081 if (!ctx->pages[i]) 1082 goto out_of_memory; 1083 set_page_private(ctx->pages[i], dma_addr); 1084 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1085 DMA_FROM_DEVICE); 1086 } 1087 1088 for (i = 0; i < AR_BUFFERS; i++) 1089 pages[i] = ctx->pages[i]; 1090 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1091 pages[AR_BUFFERS + i] = ctx->pages[i]; 1092 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1093 if (!ctx->buffer) 1094 goto out_of_memory; 1095 1096 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1097 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1098 1099 for (i = 0; i < AR_BUFFERS; i++) { 1100 d = &ctx->descriptors[i]; 1101 d->req_count = cpu_to_le16(PAGE_SIZE); 1102 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1103 DESCRIPTOR_STATUS | 1104 DESCRIPTOR_BRANCH_ALWAYS); 1105 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1106 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1107 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1108 } 1109 1110 return 0; 1111 1112 out_of_memory: 1113 ar_context_release(ctx); 1114 1115 return -ENOMEM; 1116 } 1117 1118 static void ar_context_run(struct ar_context *ctx) 1119 { 1120 unsigned int i; 1121 1122 for (i = 0; i < AR_BUFFERS; i++) 1123 ar_context_link_page(ctx, i); 1124 1125 ctx->pointer = ctx->buffer; 1126 1127 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1128 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1129 } 1130 1131 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1132 { 1133 __le16 branch; 1134 1135 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1136 1137 /* figure out which descriptor the branch address goes in */ 1138 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1139 return d; 1140 else 1141 return d + z - 1; 1142 } 1143 1144 static void context_tasklet(unsigned long data) 1145 { 1146 struct context *ctx = (struct context *) data; 1147 struct descriptor *d, *last; 1148 u32 address; 1149 int z; 1150 struct descriptor_buffer *desc; 1151 1152 desc = list_entry(ctx->buffer_list.next, 1153 struct descriptor_buffer, list); 1154 last = ctx->last; 1155 while (last->branch_address != 0) { 1156 struct descriptor_buffer *old_desc = desc; 1157 address = le32_to_cpu(last->branch_address); 1158 z = address & 0xf; 1159 address &= ~0xf; 1160 ctx->current_bus = address; 1161 1162 /* If the branch address points to a buffer outside of the 1163 * current buffer, advance to the next buffer. */ 1164 if (address < desc->buffer_bus || 1165 address >= desc->buffer_bus + desc->used) 1166 desc = list_entry(desc->list.next, 1167 struct descriptor_buffer, list); 1168 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1169 last = find_branch_descriptor(d, z); 1170 1171 if (!ctx->callback(ctx, d, last)) 1172 break; 1173 1174 if (old_desc != desc) { 1175 // If we've advanced to the next buffer, move the previous buffer to the 1176 // free list. 1177 old_desc->used = 0; 1178 guard(spinlock_irqsave)(&ctx->ohci->lock); 1179 list_move_tail(&old_desc->list, &ctx->buffer_list); 1180 } 1181 ctx->last = last; 1182 } 1183 } 1184 1185 static void ohci_isoc_context_work(struct work_struct *work) 1186 { 1187 struct fw_iso_context *base = container_of(work, struct fw_iso_context, work); 1188 struct iso_context *isoc_ctx = container_of(base, struct iso_context, base); 1189 struct context *ctx = &isoc_ctx->context; 1190 struct descriptor *d, *last; 1191 u32 address; 1192 int z; 1193 struct descriptor_buffer *desc; 1194 1195 desc = list_entry(ctx->buffer_list.next, struct descriptor_buffer, list); 1196 last = ctx->last; 1197 while (last->branch_address != 0) { 1198 struct descriptor_buffer *old_desc = desc; 1199 1200 address = le32_to_cpu(last->branch_address); 1201 z = address & 0xf; 1202 address &= ~0xf; 1203 ctx->current_bus = address; 1204 1205 // If the branch address points to a buffer outside of the current buffer, advance 1206 // to the next buffer. 1207 if (address < desc->buffer_bus || address >= desc->buffer_bus + desc->used) 1208 desc = list_entry(desc->list.next, struct descriptor_buffer, list); 1209 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1210 last = find_branch_descriptor(d, z); 1211 1212 if (!ctx->callback(ctx, d, last)) 1213 break; 1214 1215 if (old_desc != desc) { 1216 // If we've advanced to the next buffer, move the previous buffer to the 1217 // free list. 1218 old_desc->used = 0; 1219 guard(spinlock_irqsave)(&ctx->ohci->lock); 1220 list_move_tail(&old_desc->list, &ctx->buffer_list); 1221 } 1222 ctx->last = last; 1223 } 1224 } 1225 1226 /* 1227 * Allocate a new buffer and add it to the list of free buffers for this 1228 * context. Must be called with ohci->lock held. 1229 */ 1230 static int context_add_buffer(struct context *ctx) 1231 { 1232 struct descriptor_buffer *desc; 1233 dma_addr_t bus_addr; 1234 int offset; 1235 1236 /* 1237 * 16MB of descriptors should be far more than enough for any DMA 1238 * program. This will catch run-away userspace or DoS attacks. 1239 */ 1240 if (ctx->total_allocation >= 16*1024*1024) 1241 return -ENOMEM; 1242 1243 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1244 if (!desc) 1245 return -ENOMEM; 1246 1247 offset = (void *)&desc->buffer - (void *)desc; 1248 /* 1249 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1250 * for descriptors, even 0x10-byte ones. This can cause page faults when 1251 * an IOMMU is in use and the oversized read crosses a page boundary. 1252 * Work around this by always leaving at least 0x10 bytes of padding. 1253 */ 1254 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1255 desc->buffer_bus = bus_addr + offset; 1256 desc->used = 0; 1257 1258 list_add_tail(&desc->list, &ctx->buffer_list); 1259 ctx->total_allocation += PAGE_SIZE; 1260 1261 return 0; 1262 } 1263 1264 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1265 u32 regs, descriptor_callback_t callback) 1266 { 1267 ctx->ohci = ohci; 1268 ctx->regs = regs; 1269 ctx->total_allocation = 0; 1270 1271 INIT_LIST_HEAD(&ctx->buffer_list); 1272 if (context_add_buffer(ctx) < 0) 1273 return -ENOMEM; 1274 1275 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1276 struct descriptor_buffer, list); 1277 1278 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1279 ctx->callback = callback; 1280 1281 /* 1282 * We put a dummy descriptor in the buffer that has a NULL 1283 * branch address and looks like it's been sent. That way we 1284 * have a descriptor to append DMA programs to. 1285 */ 1286 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1287 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1288 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1289 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1290 ctx->last = ctx->buffer_tail->buffer; 1291 ctx->prev = ctx->buffer_tail->buffer; 1292 ctx->prev_z = 1; 1293 1294 return 0; 1295 } 1296 1297 static void context_release(struct context *ctx) 1298 { 1299 struct fw_card *card = &ctx->ohci->card; 1300 struct descriptor_buffer *desc, *tmp; 1301 1302 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1303 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1304 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1305 } 1306 } 1307 1308 /* Must be called with ohci->lock held */ 1309 static struct descriptor *context_get_descriptors(struct context *ctx, 1310 int z, dma_addr_t *d_bus) 1311 { 1312 struct descriptor *d = NULL; 1313 struct descriptor_buffer *desc = ctx->buffer_tail; 1314 1315 if (z * sizeof(*d) > desc->buffer_size) 1316 return NULL; 1317 1318 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1319 /* No room for the descriptor in this buffer, so advance to the 1320 * next one. */ 1321 1322 if (desc->list.next == &ctx->buffer_list) { 1323 /* If there is no free buffer next in the list, 1324 * allocate one. */ 1325 if (context_add_buffer(ctx) < 0) 1326 return NULL; 1327 } 1328 desc = list_entry(desc->list.next, 1329 struct descriptor_buffer, list); 1330 ctx->buffer_tail = desc; 1331 } 1332 1333 d = desc->buffer + desc->used / sizeof(*d); 1334 memset(d, 0, z * sizeof(*d)); 1335 *d_bus = desc->buffer_bus + desc->used; 1336 1337 return d; 1338 } 1339 1340 static void context_run(struct context *ctx, u32 extra) 1341 { 1342 struct fw_ohci *ohci = ctx->ohci; 1343 1344 reg_write(ohci, COMMAND_PTR(ctx->regs), 1345 le32_to_cpu(ctx->last->branch_address)); 1346 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1347 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1348 ctx->running = true; 1349 flush_writes(ohci); 1350 } 1351 1352 static void context_append(struct context *ctx, 1353 struct descriptor *d, int z, int extra) 1354 { 1355 dma_addr_t d_bus; 1356 struct descriptor_buffer *desc = ctx->buffer_tail; 1357 struct descriptor *d_branch; 1358 1359 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1360 1361 desc->used += (z + extra) * sizeof(*d); 1362 1363 wmb(); /* finish init of new descriptors before branch_address update */ 1364 1365 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1366 d_branch->branch_address = cpu_to_le32(d_bus | z); 1367 1368 /* 1369 * VT6306 incorrectly checks only the single descriptor at the 1370 * CommandPtr when the wake bit is written, so if it's a 1371 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1372 * the branch address in the first descriptor. 1373 * 1374 * Not doing this for transmit contexts since not sure how it interacts 1375 * with skip addresses. 1376 */ 1377 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1378 d_branch != ctx->prev && 1379 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1380 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1381 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1382 } 1383 1384 ctx->prev = d; 1385 ctx->prev_z = z; 1386 } 1387 1388 static void context_stop(struct context *ctx) 1389 { 1390 struct fw_ohci *ohci = ctx->ohci; 1391 u32 reg; 1392 int i; 1393 1394 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1395 ctx->running = false; 1396 1397 for (i = 0; i < 1000; i++) { 1398 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1399 if ((reg & CONTEXT_ACTIVE) == 0) 1400 return; 1401 1402 if (i) 1403 udelay(10); 1404 } 1405 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1406 } 1407 1408 struct driver_data { 1409 u8 inline_data[8]; 1410 struct fw_packet *packet; 1411 }; 1412 1413 /* 1414 * This function apppends a packet to the DMA queue for transmission. 1415 * Must always be called with the ochi->lock held to ensure proper 1416 * generation handling and locking around packet queue manipulation. 1417 */ 1418 static int at_context_queue_packet(struct context *ctx, 1419 struct fw_packet *packet) 1420 { 1421 struct fw_ohci *ohci = ctx->ohci; 1422 dma_addr_t d_bus, payload_bus; 1423 struct driver_data *driver_data; 1424 struct descriptor *d, *last; 1425 __le32 *header; 1426 int z, tcode; 1427 1428 d = context_get_descriptors(ctx, 4, &d_bus); 1429 if (d == NULL) { 1430 packet->ack = RCODE_SEND_ERROR; 1431 return -1; 1432 } 1433 1434 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1435 d[0].res_count = cpu_to_le16(packet->timestamp); 1436 1437 tcode = async_header_get_tcode(packet->header); 1438 header = (__le32 *) &d[1]; 1439 switch (tcode) { 1440 case TCODE_WRITE_QUADLET_REQUEST: 1441 case TCODE_WRITE_BLOCK_REQUEST: 1442 case TCODE_WRITE_RESPONSE: 1443 case TCODE_READ_QUADLET_REQUEST: 1444 case TCODE_READ_BLOCK_REQUEST: 1445 case TCODE_READ_QUADLET_RESPONSE: 1446 case TCODE_READ_BLOCK_RESPONSE: 1447 case TCODE_LOCK_REQUEST: 1448 case TCODE_LOCK_RESPONSE: 1449 ohci1394_at_data_set_src_bus_id(header, false); 1450 ohci1394_at_data_set_speed(header, packet->speed); 1451 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header)); 1452 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header)); 1453 ohci1394_at_data_set_tcode(header, tcode); 1454 1455 ohci1394_at_data_set_destination_id(header, 1456 async_header_get_destination(packet->header)); 1457 1458 if (ctx == &ctx->ohci->at_response_ctx) { 1459 ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header)); 1460 } else { 1461 ohci1394_at_data_set_destination_offset(header, 1462 async_header_get_offset(packet->header)); 1463 } 1464 1465 if (tcode_is_block_packet(tcode)) 1466 header[3] = cpu_to_le32(packet->header[3]); 1467 else 1468 header[3] = (__force __le32) packet->header[3]; 1469 1470 d[0].req_count = cpu_to_le16(packet->header_length); 1471 break; 1472 case TCODE_LINK_INTERNAL: 1473 ohci1394_at_data_set_speed(header, packet->speed); 1474 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL); 1475 1476 header[1] = cpu_to_le32(packet->header[1]); 1477 header[2] = cpu_to_le32(packet->header[2]); 1478 d[0].req_count = cpu_to_le16(12); 1479 1480 if (is_ping_packet(&packet->header[1])) 1481 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1482 break; 1483 1484 case TCODE_STREAM_DATA: 1485 ohci1394_it_data_set_speed(header, packet->speed); 1486 ohci1394_it_data_set_tag(header, isoc_header_get_tag(packet->header[0])); 1487 ohci1394_it_data_set_channel(header, isoc_header_get_channel(packet->header[0])); 1488 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 1489 ohci1394_it_data_set_sync(header, isoc_header_get_sy(packet->header[0])); 1490 1491 ohci1394_it_data_set_data_length(header, isoc_header_get_data_length(packet->header[0])); 1492 1493 d[0].req_count = cpu_to_le16(8); 1494 break; 1495 1496 default: 1497 /* BUG(); */ 1498 packet->ack = RCODE_SEND_ERROR; 1499 return -1; 1500 } 1501 1502 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1503 driver_data = (struct driver_data *) &d[3]; 1504 driver_data->packet = packet; 1505 packet->driver_data = driver_data; 1506 1507 if (packet->payload_length > 0) { 1508 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1509 payload_bus = dma_map_single(ohci->card.device, 1510 packet->payload, 1511 packet->payload_length, 1512 DMA_TO_DEVICE); 1513 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1514 packet->ack = RCODE_SEND_ERROR; 1515 return -1; 1516 } 1517 packet->payload_bus = payload_bus; 1518 packet->payload_mapped = true; 1519 } else { 1520 memcpy(driver_data->inline_data, packet->payload, 1521 packet->payload_length); 1522 payload_bus = d_bus + 3 * sizeof(*d); 1523 } 1524 1525 d[2].req_count = cpu_to_le16(packet->payload_length); 1526 d[2].data_address = cpu_to_le32(payload_bus); 1527 last = &d[2]; 1528 z = 3; 1529 } else { 1530 last = &d[0]; 1531 z = 2; 1532 } 1533 1534 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1535 DESCRIPTOR_IRQ_ALWAYS | 1536 DESCRIPTOR_BRANCH_ALWAYS); 1537 1538 /* FIXME: Document how the locking works. */ 1539 if (ohci->generation != packet->generation) { 1540 if (packet->payload_mapped) 1541 dma_unmap_single(ohci->card.device, payload_bus, 1542 packet->payload_length, DMA_TO_DEVICE); 1543 packet->ack = RCODE_GENERATION; 1544 return -1; 1545 } 1546 1547 context_append(ctx, d, z, 4 - z); 1548 1549 if (ctx->running) 1550 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1551 else 1552 context_run(ctx, 0); 1553 1554 return 0; 1555 } 1556 1557 static void at_context_flush(struct context *ctx) 1558 { 1559 tasklet_disable(&ctx->tasklet); 1560 1561 ctx->flushing = true; 1562 context_tasklet((unsigned long)ctx); 1563 ctx->flushing = false; 1564 1565 tasklet_enable(&ctx->tasklet); 1566 } 1567 1568 static int handle_at_packet(struct context *context, 1569 struct descriptor *d, 1570 struct descriptor *last) 1571 { 1572 struct driver_data *driver_data; 1573 struct fw_packet *packet; 1574 struct fw_ohci *ohci = context->ohci; 1575 int evt; 1576 1577 if (last->transfer_status == 0 && !context->flushing) 1578 /* This descriptor isn't done yet, stop iteration. */ 1579 return 0; 1580 1581 driver_data = (struct driver_data *) &d[3]; 1582 packet = driver_data->packet; 1583 if (packet == NULL) 1584 /* This packet was cancelled, just continue. */ 1585 return 1; 1586 1587 if (packet->payload_mapped) 1588 dma_unmap_single(ohci->card.device, packet->payload_bus, 1589 packet->payload_length, DMA_TO_DEVICE); 1590 1591 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1592 packet->timestamp = le16_to_cpu(last->res_count); 1593 1594 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1595 1596 switch (evt) { 1597 case OHCI1394_evt_timeout: 1598 /* Async response transmit timed out. */ 1599 packet->ack = RCODE_CANCELLED; 1600 break; 1601 1602 case OHCI1394_evt_flushed: 1603 /* 1604 * The packet was flushed should give same error as 1605 * when we try to use a stale generation count. 1606 */ 1607 packet->ack = RCODE_GENERATION; 1608 break; 1609 1610 case OHCI1394_evt_missing_ack: 1611 if (context->flushing) 1612 packet->ack = RCODE_GENERATION; 1613 else { 1614 /* 1615 * Using a valid (current) generation count, but the 1616 * node is not on the bus or not sending acks. 1617 */ 1618 packet->ack = RCODE_NO_ACK; 1619 } 1620 break; 1621 1622 case ACK_COMPLETE + 0x10: 1623 case ACK_PENDING + 0x10: 1624 case ACK_BUSY_X + 0x10: 1625 case ACK_BUSY_A + 0x10: 1626 case ACK_BUSY_B + 0x10: 1627 case ACK_DATA_ERROR + 0x10: 1628 case ACK_TYPE_ERROR + 0x10: 1629 packet->ack = evt - 0x10; 1630 break; 1631 1632 case OHCI1394_evt_no_status: 1633 if (context->flushing) { 1634 packet->ack = RCODE_GENERATION; 1635 break; 1636 } 1637 fallthrough; 1638 1639 default: 1640 packet->ack = RCODE_SEND_ERROR; 1641 break; 1642 } 1643 1644 packet->callback(packet, &ohci->card, packet->ack); 1645 1646 return 1; 1647 } 1648 1649 static u32 get_cycle_time(struct fw_ohci *ohci); 1650 1651 static void handle_local_rom(struct fw_ohci *ohci, 1652 struct fw_packet *packet, u32 csr) 1653 { 1654 struct fw_packet response; 1655 int tcode, length, i; 1656 1657 tcode = async_header_get_tcode(packet->header); 1658 if (tcode_is_block_packet(tcode)) 1659 length = async_header_get_data_length(packet->header); 1660 else 1661 length = 4; 1662 1663 i = csr - CSR_CONFIG_ROM; 1664 if (i + length > CONFIG_ROM_SIZE) { 1665 fw_fill_response(&response, packet->header, 1666 RCODE_ADDRESS_ERROR, NULL, 0); 1667 } else if (!tcode_is_read_request(tcode)) { 1668 fw_fill_response(&response, packet->header, 1669 RCODE_TYPE_ERROR, NULL, 0); 1670 } else { 1671 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1672 (void *) ohci->config_rom + i, length); 1673 } 1674 1675 // Timestamping on behalf of the hardware. 1676 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1677 fw_core_handle_response(&ohci->card, &response); 1678 } 1679 1680 static void handle_local_lock(struct fw_ohci *ohci, 1681 struct fw_packet *packet, u32 csr) 1682 { 1683 struct fw_packet response; 1684 int tcode, length, ext_tcode, sel, try; 1685 __be32 *payload, lock_old; 1686 u32 lock_arg, lock_data; 1687 1688 tcode = async_header_get_tcode(packet->header); 1689 length = async_header_get_data_length(packet->header); 1690 payload = packet->payload; 1691 ext_tcode = async_header_get_extended_tcode(packet->header); 1692 1693 if (tcode == TCODE_LOCK_REQUEST && 1694 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1695 lock_arg = be32_to_cpu(payload[0]); 1696 lock_data = be32_to_cpu(payload[1]); 1697 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1698 lock_arg = 0; 1699 lock_data = 0; 1700 } else { 1701 fw_fill_response(&response, packet->header, 1702 RCODE_TYPE_ERROR, NULL, 0); 1703 goto out; 1704 } 1705 1706 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1707 reg_write(ohci, OHCI1394_CSRData, lock_data); 1708 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1709 reg_write(ohci, OHCI1394_CSRControl, sel); 1710 1711 for (try = 0; try < 20; try++) 1712 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1713 lock_old = cpu_to_be32(reg_read(ohci, 1714 OHCI1394_CSRData)); 1715 fw_fill_response(&response, packet->header, 1716 RCODE_COMPLETE, 1717 &lock_old, sizeof(lock_old)); 1718 goto out; 1719 } 1720 1721 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1722 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1723 1724 out: 1725 // Timestamping on behalf of the hardware. 1726 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1727 fw_core_handle_response(&ohci->card, &response); 1728 } 1729 1730 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1731 { 1732 u64 offset, csr; 1733 1734 if (ctx == &ctx->ohci->at_request_ctx) { 1735 packet->ack = ACK_PENDING; 1736 packet->callback(packet, &ctx->ohci->card, packet->ack); 1737 } 1738 1739 offset = async_header_get_offset(packet->header); 1740 csr = offset - CSR_REGISTER_BASE; 1741 1742 /* Handle config rom reads. */ 1743 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1744 handle_local_rom(ctx->ohci, packet, csr); 1745 else switch (csr) { 1746 case CSR_BUS_MANAGER_ID: 1747 case CSR_BANDWIDTH_AVAILABLE: 1748 case CSR_CHANNELS_AVAILABLE_HI: 1749 case CSR_CHANNELS_AVAILABLE_LO: 1750 handle_local_lock(ctx->ohci, packet, csr); 1751 break; 1752 default: 1753 if (ctx == &ctx->ohci->at_request_ctx) 1754 fw_core_handle_request(&ctx->ohci->card, packet); 1755 else 1756 fw_core_handle_response(&ctx->ohci->card, packet); 1757 break; 1758 } 1759 1760 if (ctx == &ctx->ohci->at_response_ctx) { 1761 packet->ack = ACK_COMPLETE; 1762 packet->callback(packet, &ctx->ohci->card, packet->ack); 1763 } 1764 } 1765 1766 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1767 { 1768 unsigned long flags; 1769 int ret; 1770 1771 spin_lock_irqsave(&ctx->ohci->lock, flags); 1772 1773 if (async_header_get_destination(packet->header) == ctx->ohci->node_id && 1774 ctx->ohci->generation == packet->generation) { 1775 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1776 1777 // Timestamping on behalf of the hardware. 1778 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1779 1780 handle_local_request(ctx, packet); 1781 return; 1782 } 1783 1784 ret = at_context_queue_packet(ctx, packet); 1785 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1786 1787 if (ret < 0) { 1788 // Timestamping on behalf of the hardware. 1789 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1790 1791 packet->callback(packet, &ctx->ohci->card, packet->ack); 1792 } 1793 } 1794 1795 static void detect_dead_context(struct fw_ohci *ohci, 1796 const char *name, unsigned int regs) 1797 { 1798 u32 ctl; 1799 1800 ctl = reg_read(ohci, CONTROL_SET(regs)); 1801 if (ctl & CONTEXT_DEAD) 1802 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1803 name, evts[ctl & 0x1f]); 1804 } 1805 1806 static void handle_dead_contexts(struct fw_ohci *ohci) 1807 { 1808 unsigned int i; 1809 char name[8]; 1810 1811 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1812 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1813 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1814 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1815 for (i = 0; i < 32; ++i) { 1816 if (!(ohci->it_context_support & (1 << i))) 1817 continue; 1818 sprintf(name, "IT%u", i); 1819 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1820 } 1821 for (i = 0; i < 32; ++i) { 1822 if (!(ohci->ir_context_support & (1 << i))) 1823 continue; 1824 sprintf(name, "IR%u", i); 1825 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1826 } 1827 /* TODO: maybe try to flush and restart the dead contexts */ 1828 } 1829 1830 static u32 cycle_timer_ticks(u32 cycle_timer) 1831 { 1832 u32 ticks; 1833 1834 ticks = cycle_timer & 0xfff; 1835 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1836 ticks += (3072 * 8000) * (cycle_timer >> 25); 1837 1838 return ticks; 1839 } 1840 1841 /* 1842 * Some controllers exhibit one or more of the following bugs when updating the 1843 * iso cycle timer register: 1844 * - When the lowest six bits are wrapping around to zero, a read that happens 1845 * at the same time will return garbage in the lowest ten bits. 1846 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1847 * not incremented for about 60 ns. 1848 * - Occasionally, the entire register reads zero. 1849 * 1850 * To catch these, we read the register three times and ensure that the 1851 * difference between each two consecutive reads is approximately the same, i.e. 1852 * less than twice the other. Furthermore, any negative difference indicates an 1853 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1854 * execute, so we have enough precision to compute the ratio of the differences.) 1855 */ 1856 static u32 get_cycle_time(struct fw_ohci *ohci) 1857 { 1858 u32 c0, c1, c2; 1859 u32 t0, t1, t2; 1860 s32 diff01, diff12; 1861 int i; 1862 1863 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1864 return 0; 1865 1866 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1867 1868 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1869 i = 0; 1870 c1 = c2; 1871 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1872 do { 1873 c0 = c1; 1874 c1 = c2; 1875 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1876 t0 = cycle_timer_ticks(c0); 1877 t1 = cycle_timer_ticks(c1); 1878 t2 = cycle_timer_ticks(c2); 1879 diff01 = t1 - t0; 1880 diff12 = t2 - t1; 1881 } while ((diff01 <= 0 || diff12 <= 0 || 1882 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1883 && i++ < 20); 1884 } 1885 1886 return c2; 1887 } 1888 1889 /* 1890 * This function has to be called at least every 64 seconds. The bus_time 1891 * field stores not only the upper 25 bits of the BUS_TIME register but also 1892 * the most significant bit of the cycle timer in bit 6 so that we can detect 1893 * changes in this bit. 1894 */ 1895 static u32 update_bus_time(struct fw_ohci *ohci) 1896 { 1897 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1898 1899 if (unlikely(!ohci->bus_time_running)) { 1900 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1901 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1902 (cycle_time_seconds & 0x40); 1903 ohci->bus_time_running = true; 1904 } 1905 1906 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1907 ohci->bus_time += 0x40; 1908 1909 return ohci->bus_time | cycle_time_seconds; 1910 } 1911 1912 static int get_status_for_port(struct fw_ohci *ohci, int port_index, 1913 enum phy_packet_self_id_port_status *status) 1914 { 1915 int reg; 1916 1917 scoped_guard(mutex, &ohci->phy_reg_mutex) { 1918 reg = write_phy_reg(ohci, 7, port_index); 1919 if (reg < 0) 1920 return reg; 1921 1922 reg = read_phy_reg(ohci, 8); 1923 if (reg < 0) 1924 return reg; 1925 } 1926 1927 switch (reg & 0x0f) { 1928 case 0x06: 1929 // is child node (connected to parent node) 1930 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT; 1931 break; 1932 case 0x0e: 1933 // is parent node (connected to child node) 1934 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD; 1935 break; 1936 default: 1937 // not connected 1938 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN; 1939 break; 1940 } 1941 1942 return 0; 1943 } 1944 1945 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1946 int self_id_count) 1947 { 1948 unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id); 1949 int i; 1950 1951 for (i = 0; i < self_id_count; i++) { 1952 u32 entry = ohci->self_id_buffer[i]; 1953 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry); 1954 1955 if (left_phy_id == right_phy_id) 1956 return -1; 1957 if (left_phy_id < right_phy_id) 1958 return i; 1959 } 1960 return i; 1961 } 1962 1963 static int detect_initiated_reset(struct fw_ohci *ohci, bool *is_initiated_reset) 1964 { 1965 int reg; 1966 1967 guard(mutex)(&ohci->phy_reg_mutex); 1968 1969 // Select page 7 1970 reg = write_phy_reg(ohci, 7, 0xe0); 1971 if (reg < 0) 1972 return reg; 1973 1974 reg = read_phy_reg(ohci, 8); 1975 if (reg < 0) 1976 return reg; 1977 1978 // set PMODE bit 1979 reg |= 0x40; 1980 reg = write_phy_reg(ohci, 8, reg); 1981 if (reg < 0) 1982 return reg; 1983 1984 // read register 12 1985 reg = read_phy_reg(ohci, 12); 1986 if (reg < 0) 1987 return reg; 1988 1989 // bit 3 indicates "initiated reset" 1990 *is_initiated_reset = !!((reg & 0x08) == 0x08); 1991 1992 return 0; 1993 } 1994 1995 /* 1996 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1997 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1998 * Construct the selfID from phy register contents. 1999 */ 2000 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 2001 { 2002 int reg, i, pos, err; 2003 bool is_initiated_reset; 2004 u32 self_id = 0; 2005 2006 // link active 1, speed 3, bridge 0, contender 1, more packets 0. 2007 phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID); 2008 phy_packet_self_id_zero_set_link_active(&self_id, true); 2009 phy_packet_self_id_zero_set_scode(&self_id, SCODE_800); 2010 phy_packet_self_id_zero_set_contender(&self_id, true); 2011 2012 reg = reg_read(ohci, OHCI1394_NodeID); 2013 if (!(reg & OHCI1394_NodeID_idValid)) { 2014 ohci_notice(ohci, 2015 "node ID not valid, new bus reset in progress\n"); 2016 return -EBUSY; 2017 } 2018 phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f); 2019 2020 reg = ohci_read_phy_reg(&ohci->card, 4); 2021 if (reg < 0) 2022 return reg; 2023 phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07); 2024 2025 reg = ohci_read_phy_reg(&ohci->card, 1); 2026 if (reg < 0) 2027 return reg; 2028 phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f); 2029 2030 for (i = 0; i < 3; i++) { 2031 enum phy_packet_self_id_port_status status; 2032 2033 err = get_status_for_port(ohci, i, &status); 2034 if (err < 0) 2035 return err; 2036 2037 self_id_sequence_set_port_status(&self_id, 1, i, status); 2038 } 2039 2040 err = detect_initiated_reset(ohci, &is_initiated_reset); 2041 if (err < 0) 2042 return err; 2043 phy_packet_self_id_zero_set_initiated_reset(&self_id, is_initiated_reset); 2044 2045 pos = get_self_id_pos(ohci, self_id, self_id_count); 2046 if (pos >= 0) { 2047 memmove(&(ohci->self_id_buffer[pos+1]), 2048 &(ohci->self_id_buffer[pos]), 2049 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 2050 ohci->self_id_buffer[pos] = self_id; 2051 self_id_count++; 2052 } 2053 return self_id_count; 2054 } 2055 2056 static void bus_reset_work(struct work_struct *work) 2057 { 2058 struct fw_ohci *ohci = 2059 container_of(work, struct fw_ohci, bus_reset_work); 2060 int self_id_count, generation, new_generation, i, j; 2061 u32 reg, quadlet; 2062 void *free_rom = NULL; 2063 dma_addr_t free_rom_bus = 0; 2064 bool is_new_root; 2065 2066 reg = reg_read(ohci, OHCI1394_NodeID); 2067 if (!(reg & OHCI1394_NodeID_idValid)) { 2068 ohci_notice(ohci, 2069 "node ID not valid, new bus reset in progress\n"); 2070 return; 2071 } 2072 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 2073 ohci_notice(ohci, "malconfigured bus\n"); 2074 return; 2075 } 2076 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 2077 OHCI1394_NodeID_nodeNumber); 2078 2079 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 2080 if (!(ohci->is_root && is_new_root)) 2081 reg_write(ohci, OHCI1394_LinkControlSet, 2082 OHCI1394_LinkControl_cycleMaster); 2083 ohci->is_root = is_new_root; 2084 2085 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2086 if (ohci1394_self_id_count_is_error(reg)) { 2087 ohci_notice(ohci, "self ID receive error\n"); 2088 return; 2089 } 2090 /* 2091 * The count in the SelfIDCount register is the number of 2092 * bytes in the self ID receive buffer. Since we also receive 2093 * the inverted quadlets and a header quadlet, we shift one 2094 * bit extra to get the actual number of self IDs. 2095 */ 2096 self_id_count = ohci1394_self_id_count_get_size(reg) >> 1; 2097 2098 if (self_id_count > 252) { 2099 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 2100 return; 2101 } 2102 2103 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); 2104 generation = ohci1394_self_id_receive_q0_get_generation(quadlet); 2105 rmb(); 2106 2107 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 2108 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); 2109 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); 2110 2111 if (id != ~id2) { 2112 /* 2113 * If the invalid data looks like a cycle start packet, 2114 * it's likely to be the result of the cycle master 2115 * having a wrong gap count. In this case, the self IDs 2116 * so far are valid and should be processed so that the 2117 * bus manager can then correct the gap count. 2118 */ 2119 if (id == 0xffff008f) { 2120 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2121 self_id_count = j; 2122 break; 2123 } 2124 2125 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2126 j, self_id_count, id, id2); 2127 return; 2128 } 2129 ohci->self_id_buffer[j] = id; 2130 } 2131 2132 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2133 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2134 if (self_id_count < 0) { 2135 ohci_notice(ohci, 2136 "could not construct local self ID\n"); 2137 return; 2138 } 2139 } 2140 2141 if (self_id_count == 0) { 2142 ohci_notice(ohci, "no self IDs\n"); 2143 return; 2144 } 2145 rmb(); 2146 2147 /* 2148 * Check the consistency of the self IDs we just read. The 2149 * problem we face is that a new bus reset can start while we 2150 * read out the self IDs from the DMA buffer. If this happens, 2151 * the DMA buffer will be overwritten with new self IDs and we 2152 * will read out inconsistent data. The OHCI specification 2153 * (section 11.2) recommends a technique similar to 2154 * linux/seqlock.h, where we remember the generation of the 2155 * self IDs in the buffer before reading them out and compare 2156 * it to the current generation after reading them out. If 2157 * the two generations match we know we have a consistent set 2158 * of self IDs. 2159 */ 2160 2161 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2162 new_generation = ohci1394_self_id_count_get_generation(reg); 2163 if (new_generation != generation) { 2164 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2165 return; 2166 } 2167 2168 // FIXME: Document how the locking works. 2169 scoped_guard(spinlock_irq, &ohci->lock) { 2170 ohci->generation = -1; // prevent AT packet queueing 2171 context_stop(&ohci->at_request_ctx); 2172 context_stop(&ohci->at_response_ctx); 2173 } 2174 2175 /* 2176 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2177 * packets in the AT queues and software needs to drain them. 2178 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2179 */ 2180 at_context_flush(&ohci->at_request_ctx); 2181 at_context_flush(&ohci->at_response_ctx); 2182 2183 scoped_guard(spinlock_irq, &ohci->lock) { 2184 ohci->generation = generation; 2185 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2186 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2187 2188 if (ohci->quirks & QUIRK_RESET_PACKET) 2189 ohci->request_generation = generation; 2190 2191 // This next bit is unrelated to the AT context stuff but we have to do it under the 2192 // spinlock also. If a new config rom was set up before this reset, the old one is 2193 // now no longer in use and we can free it. Update the config rom pointers to point 2194 // to the current config rom and clear the next_config_rom pointer so a new update 2195 // can take place. 2196 if (ohci->next_config_rom != NULL) { 2197 if (ohci->next_config_rom != ohci->config_rom) { 2198 free_rom = ohci->config_rom; 2199 free_rom_bus = ohci->config_rom_bus; 2200 } 2201 ohci->config_rom = ohci->next_config_rom; 2202 ohci->config_rom_bus = ohci->next_config_rom_bus; 2203 ohci->next_config_rom = NULL; 2204 2205 // Restore config_rom image and manually update config_rom registers. 2206 // Writing the header quadlet will indicate that the config rom is ready, 2207 // so we do that last. 2208 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2])); 2209 ohci->config_rom[0] = ohci->next_header; 2210 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(ohci->next_header)); 2211 } 2212 2213 if (param_remote_dma) { 2214 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2215 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2216 } 2217 } 2218 2219 if (free_rom) 2220 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2221 2222 log_selfids(ohci, generation, self_id_count); 2223 2224 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2225 self_id_count, ohci->self_id_buffer, 2226 ohci->csr_state_setclear_abdicate); 2227 ohci->csr_state_setclear_abdicate = false; 2228 } 2229 2230 static irqreturn_t irq_handler(int irq, void *data) 2231 { 2232 struct fw_ohci *ohci = data; 2233 u32 event, iso_event; 2234 int i; 2235 2236 event = reg_read(ohci, OHCI1394_IntEventClear); 2237 2238 if (!event || !~event) 2239 return IRQ_NONE; 2240 2241 if (unlikely(param_debug > 0)) { 2242 dev_notice_ratelimited(ohci->card.device, 2243 "The debug parameter is superceded by tracepoints events, and deprecated."); 2244 } 2245 2246 /* 2247 * busReset and postedWriteErr events must not be cleared yet 2248 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2249 */ 2250 reg_write(ohci, OHCI1394_IntEventClear, 2251 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2252 trace_irqs(ohci->card.index, event); 2253 log_irqs(ohci, event); 2254 // The flag is masked again at bus_reset_work() scheduled by selfID event. 2255 if (event & OHCI1394_busReset) 2256 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2257 2258 if (event & OHCI1394_selfIDComplete) { 2259 if (trace_self_id_complete_enabled()) { 2260 u32 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2261 2262 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, 2263 has_be_header_quirk(ohci)); 2264 } 2265 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2266 } 2267 2268 if (event & OHCI1394_RQPkt) 2269 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2270 2271 if (event & OHCI1394_RSPkt) 2272 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2273 2274 if (event & OHCI1394_reqTxComplete) 2275 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2276 2277 if (event & OHCI1394_respTxComplete) 2278 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2279 2280 if (event & OHCI1394_isochRx) { 2281 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2282 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2283 2284 while (iso_event) { 2285 i = ffs(iso_event) - 1; 2286 fw_iso_context_queue_work(&ohci->ir_context_list[i].base); 2287 iso_event &= ~(1 << i); 2288 } 2289 } 2290 2291 if (event & OHCI1394_isochTx) { 2292 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2293 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2294 2295 while (iso_event) { 2296 i = ffs(iso_event) - 1; 2297 fw_iso_context_queue_work(&ohci->it_context_list[i].base); 2298 iso_event &= ~(1 << i); 2299 } 2300 } 2301 2302 if (unlikely(event & OHCI1394_regAccessFail)) 2303 ohci_err(ohci, "register access failure\n"); 2304 2305 if (unlikely(event & OHCI1394_postedWriteErr)) { 2306 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2307 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2308 reg_write(ohci, OHCI1394_IntEventClear, 2309 OHCI1394_postedWriteErr); 2310 dev_err_ratelimited(ohci->card.device, "PCI posted write error\n"); 2311 } 2312 2313 if (unlikely(event & OHCI1394_cycleTooLong)) { 2314 dev_notice_ratelimited(ohci->card.device, "isochronous cycle too long\n"); 2315 reg_write(ohci, OHCI1394_LinkControlSet, 2316 OHCI1394_LinkControl_cycleMaster); 2317 } 2318 2319 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2320 /* 2321 * We need to clear this event bit in order to make 2322 * cycleMatch isochronous I/O work. In theory we should 2323 * stop active cycleMatch iso contexts now and restart 2324 * them at least two cycles later. (FIXME?) 2325 */ 2326 dev_notice_ratelimited(ohci->card.device, "isochronous cycle inconsistent\n"); 2327 } 2328 2329 if (unlikely(event & OHCI1394_unrecoverableError)) 2330 handle_dead_contexts(ohci); 2331 2332 if (event & OHCI1394_cycle64Seconds) { 2333 guard(spinlock)(&ohci->lock); 2334 update_bus_time(ohci); 2335 } else 2336 flush_writes(ohci); 2337 2338 return IRQ_HANDLED; 2339 } 2340 2341 static int software_reset(struct fw_ohci *ohci) 2342 { 2343 u32 val; 2344 int i; 2345 2346 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2347 for (i = 0; i < 500; i++) { 2348 val = reg_read(ohci, OHCI1394_HCControlSet); 2349 if (!~val) 2350 return -ENODEV; /* Card was ejected. */ 2351 2352 if (!(val & OHCI1394_HCControl_softReset)) 2353 return 0; 2354 2355 msleep(1); 2356 } 2357 2358 return -EBUSY; 2359 } 2360 2361 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2362 { 2363 size_t size = length * 4; 2364 2365 memcpy(dest, src, size); 2366 if (size < CONFIG_ROM_SIZE) 2367 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2368 } 2369 2370 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2371 { 2372 bool enable_1394a; 2373 int ret, clear, set, offset; 2374 2375 /* Check if the driver should configure link and PHY. */ 2376 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2377 OHCI1394_HCControl_programPhyEnable)) 2378 return 0; 2379 2380 /* Paranoia: check whether the PHY supports 1394a, too. */ 2381 enable_1394a = false; 2382 ret = read_phy_reg(ohci, 2); 2383 if (ret < 0) 2384 return ret; 2385 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2386 ret = read_paged_phy_reg(ohci, 1, 8); 2387 if (ret < 0) 2388 return ret; 2389 if (ret >= 1) 2390 enable_1394a = true; 2391 } 2392 2393 if (ohci->quirks & QUIRK_NO_1394A) 2394 enable_1394a = false; 2395 2396 /* Configure PHY and link consistently. */ 2397 if (enable_1394a) { 2398 clear = 0; 2399 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2400 } else { 2401 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2402 set = 0; 2403 } 2404 ret = update_phy_reg(ohci, 5, clear, set); 2405 if (ret < 0) 2406 return ret; 2407 2408 if (enable_1394a) 2409 offset = OHCI1394_HCControlSet; 2410 else 2411 offset = OHCI1394_HCControlClear; 2412 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2413 2414 /* Clean up: configuration has been taken care of. */ 2415 reg_write(ohci, OHCI1394_HCControlClear, 2416 OHCI1394_HCControl_programPhyEnable); 2417 2418 return 0; 2419 } 2420 2421 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2422 { 2423 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2424 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2425 int reg, i; 2426 2427 reg = read_phy_reg(ohci, 2); 2428 if (reg < 0) 2429 return reg; 2430 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2431 return 0; 2432 2433 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2434 reg = read_paged_phy_reg(ohci, 1, i + 10); 2435 if (reg < 0) 2436 return reg; 2437 if (reg != id[i]) 2438 return 0; 2439 } 2440 return 1; 2441 } 2442 2443 static int ohci_enable(struct fw_card *card, 2444 const __be32 *config_rom, size_t length) 2445 { 2446 struct fw_ohci *ohci = fw_ohci(card); 2447 u32 lps, version, irqs; 2448 int i, ret; 2449 2450 ret = software_reset(ohci); 2451 if (ret < 0) { 2452 ohci_err(ohci, "failed to reset ohci card\n"); 2453 return ret; 2454 } 2455 2456 /* 2457 * Now enable LPS, which we need in order to start accessing 2458 * most of the registers. In fact, on some cards (ALI M5251), 2459 * accessing registers in the SClk domain without LPS enabled 2460 * will lock up the machine. Wait 50msec to make sure we have 2461 * full link enabled. However, with some cards (well, at least 2462 * a JMicron PCIe card), we have to try again sometimes. 2463 * 2464 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2465 * cannot actually use the phy at that time. These need tens of 2466 * millisecods pause between LPS write and first phy access too. 2467 */ 2468 2469 reg_write(ohci, OHCI1394_HCControlSet, 2470 OHCI1394_HCControl_LPS | 2471 OHCI1394_HCControl_postedWriteEnable); 2472 flush_writes(ohci); 2473 2474 for (lps = 0, i = 0; !lps && i < 3; i++) { 2475 msleep(50); 2476 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2477 OHCI1394_HCControl_LPS; 2478 } 2479 2480 if (!lps) { 2481 ohci_err(ohci, "failed to set Link Power Status\n"); 2482 return -EIO; 2483 } 2484 2485 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2486 ret = probe_tsb41ba3d(ohci); 2487 if (ret < 0) 2488 return ret; 2489 if (ret) 2490 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2491 else 2492 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2493 } 2494 2495 reg_write(ohci, OHCI1394_HCControlClear, 2496 OHCI1394_HCControl_noByteSwapData); 2497 2498 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2499 reg_write(ohci, OHCI1394_LinkControlSet, 2500 OHCI1394_LinkControl_cycleTimerEnable | 2501 OHCI1394_LinkControl_cycleMaster); 2502 2503 reg_write(ohci, OHCI1394_ATRetries, 2504 OHCI1394_MAX_AT_REQ_RETRIES | 2505 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2506 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2507 (200 << 16)); 2508 2509 ohci->bus_time_running = false; 2510 2511 for (i = 0; i < 32; i++) 2512 if (ohci->ir_context_support & (1 << i)) 2513 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2514 IR_CONTEXT_MULTI_CHANNEL_MODE); 2515 2516 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2517 if (version >= OHCI_VERSION_1_1) { 2518 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2519 0xfffffffe); 2520 card->broadcast_channel_auto_allocated = true; 2521 } 2522 2523 /* Get implemented bits of the priority arbitration request counter. */ 2524 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2525 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2526 reg_write(ohci, OHCI1394_FairnessControl, 0); 2527 card->priority_budget_implemented = ohci->pri_req_max != 0; 2528 2529 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2530 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2531 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2532 2533 ret = configure_1394a_enhancements(ohci); 2534 if (ret < 0) 2535 return ret; 2536 2537 /* Activate link_on bit and contender bit in our self ID packets.*/ 2538 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2539 if (ret < 0) 2540 return ret; 2541 2542 /* 2543 * When the link is not yet enabled, the atomic config rom 2544 * update mechanism described below in ohci_set_config_rom() 2545 * is not active. We have to update ConfigRomHeader and 2546 * BusOptions manually, and the write to ConfigROMmap takes 2547 * effect immediately. We tie this to the enabling of the 2548 * link, so we have a valid config rom before enabling - the 2549 * OHCI requires that ConfigROMhdr and BusOptions have valid 2550 * values before enabling. 2551 * 2552 * However, when the ConfigROMmap is written, some controllers 2553 * always read back quadlets 0 and 2 from the config rom to 2554 * the ConfigRomHeader and BusOptions registers on bus reset. 2555 * They shouldn't do that in this initial case where the link 2556 * isn't enabled. This means we have to use the same 2557 * workaround here, setting the bus header to 0 and then write 2558 * the right values in the bus reset tasklet. 2559 */ 2560 2561 if (config_rom) { 2562 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2563 &ohci->next_config_rom_bus, GFP_KERNEL); 2564 if (ohci->next_config_rom == NULL) 2565 return -ENOMEM; 2566 2567 copy_config_rom(ohci->next_config_rom, config_rom, length); 2568 } else { 2569 /* 2570 * In the suspend case, config_rom is NULL, which 2571 * means that we just reuse the old config rom. 2572 */ 2573 ohci->next_config_rom = ohci->config_rom; 2574 ohci->next_config_rom_bus = ohci->config_rom_bus; 2575 } 2576 2577 ohci->next_header = ohci->next_config_rom[0]; 2578 ohci->next_config_rom[0] = 0; 2579 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2580 reg_write(ohci, OHCI1394_BusOptions, 2581 be32_to_cpu(ohci->next_config_rom[2])); 2582 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2583 2584 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2585 2586 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2587 OHCI1394_RQPkt | OHCI1394_RSPkt | 2588 OHCI1394_isochTx | OHCI1394_isochRx | 2589 OHCI1394_postedWriteErr | 2590 OHCI1394_selfIDComplete | 2591 OHCI1394_regAccessFail | 2592 OHCI1394_cycleInconsistent | 2593 OHCI1394_unrecoverableError | 2594 OHCI1394_cycleTooLong | 2595 OHCI1394_masterIntEnable | 2596 OHCI1394_busReset; 2597 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2598 2599 reg_write(ohci, OHCI1394_HCControlSet, 2600 OHCI1394_HCControl_linkEnable | 2601 OHCI1394_HCControl_BIBimageValid); 2602 2603 reg_write(ohci, OHCI1394_LinkControlSet, 2604 OHCI1394_LinkControl_rcvSelfID | 2605 OHCI1394_LinkControl_rcvPhyPkt); 2606 2607 ar_context_run(&ohci->ar_request_ctx); 2608 ar_context_run(&ohci->ar_response_ctx); 2609 2610 flush_writes(ohci); 2611 2612 /* We are ready to go, reset bus to finish initialization. */ 2613 fw_schedule_bus_reset(&ohci->card, false, true); 2614 2615 return 0; 2616 } 2617 2618 static int ohci_set_config_rom(struct fw_card *card, 2619 const __be32 *config_rom, size_t length) 2620 { 2621 struct fw_ohci *ohci; 2622 __be32 *next_config_rom; 2623 dma_addr_t next_config_rom_bus; 2624 2625 ohci = fw_ohci(card); 2626 2627 /* 2628 * When the OHCI controller is enabled, the config rom update 2629 * mechanism is a bit tricky, but easy enough to use. See 2630 * section 5.5.6 in the OHCI specification. 2631 * 2632 * The OHCI controller caches the new config rom address in a 2633 * shadow register (ConfigROMmapNext) and needs a bus reset 2634 * for the changes to take place. When the bus reset is 2635 * detected, the controller loads the new values for the 2636 * ConfigRomHeader and BusOptions registers from the specified 2637 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2638 * shadow register. All automatically and atomically. 2639 * 2640 * Now, there's a twist to this story. The automatic load of 2641 * ConfigRomHeader and BusOptions doesn't honor the 2642 * noByteSwapData bit, so with a be32 config rom, the 2643 * controller will load be32 values in to these registers 2644 * during the atomic update, even on litte endian 2645 * architectures. The workaround we use is to put a 0 in the 2646 * header quadlet; 0 is endian agnostic and means that the 2647 * config rom isn't ready yet. In the bus reset tasklet we 2648 * then set up the real values for the two registers. 2649 * 2650 * We use ohci->lock to avoid racing with the code that sets 2651 * ohci->next_config_rom to NULL (see bus_reset_work). 2652 */ 2653 2654 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2655 &next_config_rom_bus, GFP_KERNEL); 2656 if (next_config_rom == NULL) 2657 return -ENOMEM; 2658 2659 scoped_guard(spinlock_irq, &ohci->lock) { 2660 // If there is not an already pending config_rom update, push our new allocation 2661 // into the ohci->next_config_rom and then mark the local variable as null so that 2662 // we won't deallocate the new buffer. 2663 // 2664 // OTOH, if there is a pending config_rom update, just use that buffer with the new 2665 // config_rom data, and let this routine free the unused DMA allocation. 2666 if (ohci->next_config_rom == NULL) { 2667 ohci->next_config_rom = next_config_rom; 2668 ohci->next_config_rom_bus = next_config_rom_bus; 2669 next_config_rom = NULL; 2670 } 2671 2672 copy_config_rom(ohci->next_config_rom, config_rom, length); 2673 2674 ohci->next_header = config_rom[0]; 2675 ohci->next_config_rom[0] = 0; 2676 2677 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2678 } 2679 2680 /* If we didn't use the DMA allocation, delete it. */ 2681 if (next_config_rom != NULL) { 2682 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2683 next_config_rom_bus); 2684 } 2685 2686 /* 2687 * Now initiate a bus reset to have the changes take 2688 * effect. We clean up the old config rom memory and DMA 2689 * mappings in the bus reset tasklet, since the OHCI 2690 * controller could need to access it before the bus reset 2691 * takes effect. 2692 */ 2693 2694 fw_schedule_bus_reset(&ohci->card, true, true); 2695 2696 return 0; 2697 } 2698 2699 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2700 { 2701 struct fw_ohci *ohci = fw_ohci(card); 2702 2703 at_context_transmit(&ohci->at_request_ctx, packet); 2704 } 2705 2706 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2707 { 2708 struct fw_ohci *ohci = fw_ohci(card); 2709 2710 at_context_transmit(&ohci->at_response_ctx, packet); 2711 } 2712 2713 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2714 { 2715 struct fw_ohci *ohci = fw_ohci(card); 2716 struct context *ctx = &ohci->at_request_ctx; 2717 struct driver_data *driver_data = packet->driver_data; 2718 int ret = -ENOENT; 2719 2720 tasklet_disable_in_atomic(&ctx->tasklet); 2721 2722 if (packet->ack != 0) 2723 goto out; 2724 2725 if (packet->payload_mapped) 2726 dma_unmap_single(ohci->card.device, packet->payload_bus, 2727 packet->payload_length, DMA_TO_DEVICE); 2728 2729 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2730 driver_data->packet = NULL; 2731 packet->ack = RCODE_CANCELLED; 2732 2733 // Timestamping on behalf of the hardware. 2734 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2735 2736 packet->callback(packet, &ohci->card, packet->ack); 2737 ret = 0; 2738 out: 2739 tasklet_enable(&ctx->tasklet); 2740 2741 return ret; 2742 } 2743 2744 static int ohci_enable_phys_dma(struct fw_card *card, 2745 int node_id, int generation) 2746 { 2747 struct fw_ohci *ohci = fw_ohci(card); 2748 int n, ret = 0; 2749 2750 if (param_remote_dma) 2751 return 0; 2752 2753 /* 2754 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2755 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2756 */ 2757 2758 guard(spinlock_irqsave)(&ohci->lock); 2759 2760 if (ohci->generation != generation) 2761 return -ESTALE; 2762 2763 /* 2764 * Note, if the node ID contains a non-local bus ID, physical DMA is 2765 * enabled for _all_ nodes on remote buses. 2766 */ 2767 2768 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2769 if (n < 32) 2770 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2771 else 2772 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2773 2774 flush_writes(ohci); 2775 2776 return ret; 2777 } 2778 2779 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2780 { 2781 struct fw_ohci *ohci = fw_ohci(card); 2782 u32 value; 2783 2784 switch (csr_offset) { 2785 case CSR_STATE_CLEAR: 2786 case CSR_STATE_SET: 2787 if (ohci->is_root && 2788 (reg_read(ohci, OHCI1394_LinkControlSet) & 2789 OHCI1394_LinkControl_cycleMaster)) 2790 value = CSR_STATE_BIT_CMSTR; 2791 else 2792 value = 0; 2793 if (ohci->csr_state_setclear_abdicate) 2794 value |= CSR_STATE_BIT_ABDICATE; 2795 2796 return value; 2797 2798 case CSR_NODE_IDS: 2799 return reg_read(ohci, OHCI1394_NodeID) << 16; 2800 2801 case CSR_CYCLE_TIME: 2802 return get_cycle_time(ohci); 2803 2804 case CSR_BUS_TIME: 2805 { 2806 // We might be called just after the cycle timer has wrapped around but just before 2807 // the cycle64Seconds handler, so we better check here, too, if the bus time needs 2808 // to be updated. 2809 2810 guard(spinlock_irqsave)(&ohci->lock); 2811 return update_bus_time(ohci); 2812 } 2813 case CSR_BUSY_TIMEOUT: 2814 value = reg_read(ohci, OHCI1394_ATRetries); 2815 return (value >> 4) & 0x0ffff00f; 2816 2817 case CSR_PRIORITY_BUDGET: 2818 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2819 (ohci->pri_req_max << 8); 2820 2821 default: 2822 WARN_ON(1); 2823 return 0; 2824 } 2825 } 2826 2827 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2828 { 2829 struct fw_ohci *ohci = fw_ohci(card); 2830 2831 switch (csr_offset) { 2832 case CSR_STATE_CLEAR: 2833 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2834 reg_write(ohci, OHCI1394_LinkControlClear, 2835 OHCI1394_LinkControl_cycleMaster); 2836 flush_writes(ohci); 2837 } 2838 if (value & CSR_STATE_BIT_ABDICATE) 2839 ohci->csr_state_setclear_abdicate = false; 2840 break; 2841 2842 case CSR_STATE_SET: 2843 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2844 reg_write(ohci, OHCI1394_LinkControlSet, 2845 OHCI1394_LinkControl_cycleMaster); 2846 flush_writes(ohci); 2847 } 2848 if (value & CSR_STATE_BIT_ABDICATE) 2849 ohci->csr_state_setclear_abdicate = true; 2850 break; 2851 2852 case CSR_NODE_IDS: 2853 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2854 flush_writes(ohci); 2855 break; 2856 2857 case CSR_CYCLE_TIME: 2858 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2859 reg_write(ohci, OHCI1394_IntEventSet, 2860 OHCI1394_cycleInconsistent); 2861 flush_writes(ohci); 2862 break; 2863 2864 case CSR_BUS_TIME: 2865 { 2866 guard(spinlock_irqsave)(&ohci->lock); 2867 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f); 2868 break; 2869 } 2870 case CSR_BUSY_TIMEOUT: 2871 value = (value & 0xf) | ((value & 0xf) << 4) | 2872 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2873 reg_write(ohci, OHCI1394_ATRetries, value); 2874 flush_writes(ohci); 2875 break; 2876 2877 case CSR_PRIORITY_BUDGET: 2878 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2879 flush_writes(ohci); 2880 break; 2881 2882 default: 2883 WARN_ON(1); 2884 break; 2885 } 2886 } 2887 2888 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause) 2889 { 2890 trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2891 ctx->header_length); 2892 trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2893 ctx->header_length); 2894 2895 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2896 ctx->header_length, ctx->header, 2897 ctx->base.callback_data); 2898 ctx->header_length = 0; 2899 } 2900 2901 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2902 { 2903 u32 *ctx_hdr; 2904 2905 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2906 if (ctx->base.drop_overflow_headers) 2907 return; 2908 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 2909 } 2910 2911 ctx_hdr = ctx->header + ctx->header_length; 2912 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2913 2914 /* 2915 * The two iso header quadlets are byteswapped to little 2916 * endian by the controller, but we want to present them 2917 * as big endian for consistency with the bus endianness. 2918 */ 2919 if (ctx->base.header_size > 0) 2920 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2921 if (ctx->base.header_size > 4) 2922 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2923 if (ctx->base.header_size > 8) 2924 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2925 ctx->header_length += ctx->base.header_size; 2926 } 2927 2928 static int handle_ir_packet_per_buffer(struct context *context, 2929 struct descriptor *d, 2930 struct descriptor *last) 2931 { 2932 struct iso_context *ctx = 2933 container_of(context, struct iso_context, context); 2934 struct descriptor *pd; 2935 u32 buffer_dma; 2936 2937 for (pd = d; pd <= last; pd++) 2938 if (pd->transfer_status) 2939 break; 2940 if (pd > last) 2941 /* Descriptor(s) not done yet, stop iteration */ 2942 return 0; 2943 2944 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2945 d++; 2946 buffer_dma = le32_to_cpu(d->data_address); 2947 dma_sync_single_range_for_cpu(context->ohci->card.device, 2948 buffer_dma & PAGE_MASK, 2949 buffer_dma & ~PAGE_MASK, 2950 le16_to_cpu(d->req_count), 2951 DMA_FROM_DEVICE); 2952 } 2953 2954 copy_iso_headers(ctx, (u32 *) (last + 1)); 2955 2956 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2957 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2958 2959 return 1; 2960 } 2961 2962 /* d == last because each descriptor block is only a single descriptor. */ 2963 static int handle_ir_buffer_fill(struct context *context, 2964 struct descriptor *d, 2965 struct descriptor *last) 2966 { 2967 struct iso_context *ctx = 2968 container_of(context, struct iso_context, context); 2969 unsigned int req_count, res_count, completed; 2970 u32 buffer_dma; 2971 2972 req_count = le16_to_cpu(last->req_count); 2973 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2974 completed = req_count - res_count; 2975 buffer_dma = le32_to_cpu(last->data_address); 2976 2977 if (completed > 0) { 2978 ctx->mc_buffer_bus = buffer_dma; 2979 ctx->mc_completed = completed; 2980 } 2981 2982 if (res_count != 0) 2983 /* Descriptor(s) not done yet, stop iteration */ 2984 return 0; 2985 2986 dma_sync_single_range_for_cpu(context->ohci->card.device, 2987 buffer_dma & PAGE_MASK, 2988 buffer_dma & ~PAGE_MASK, 2989 completed, DMA_FROM_DEVICE); 2990 2991 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2992 trace_isoc_inbound_multiple_completions(&ctx->base, completed, 2993 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2994 2995 ctx->base.callback.mc(&ctx->base, 2996 buffer_dma + completed, 2997 ctx->base.callback_data); 2998 ctx->mc_completed = 0; 2999 } 3000 3001 return 1; 3002 } 3003 3004 static void flush_ir_buffer_fill(struct iso_context *ctx) 3005 { 3006 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 3007 ctx->mc_buffer_bus & PAGE_MASK, 3008 ctx->mc_buffer_bus & ~PAGE_MASK, 3009 ctx->mc_completed, DMA_FROM_DEVICE); 3010 3011 trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed, 3012 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3013 3014 ctx->base.callback.mc(&ctx->base, 3015 ctx->mc_buffer_bus + ctx->mc_completed, 3016 ctx->base.callback_data); 3017 ctx->mc_completed = 0; 3018 } 3019 3020 static inline void sync_it_packet_for_cpu(struct context *context, 3021 struct descriptor *pd) 3022 { 3023 __le16 control; 3024 u32 buffer_dma; 3025 3026 /* only packets beginning with OUTPUT_MORE* have data buffers */ 3027 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3028 return; 3029 3030 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 3031 pd += 2; 3032 3033 /* 3034 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 3035 * data buffer is in the context program's coherent page and must not 3036 * be synced. 3037 */ 3038 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 3039 (context->current_bus & PAGE_MASK)) { 3040 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3041 return; 3042 pd++; 3043 } 3044 3045 do { 3046 buffer_dma = le32_to_cpu(pd->data_address); 3047 dma_sync_single_range_for_cpu(context->ohci->card.device, 3048 buffer_dma & PAGE_MASK, 3049 buffer_dma & ~PAGE_MASK, 3050 le16_to_cpu(pd->req_count), 3051 DMA_TO_DEVICE); 3052 control = pd->control; 3053 pd++; 3054 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 3055 } 3056 3057 static int handle_it_packet(struct context *context, 3058 struct descriptor *d, 3059 struct descriptor *last) 3060 { 3061 struct iso_context *ctx = 3062 container_of(context, struct iso_context, context); 3063 struct descriptor *pd; 3064 __be32 *ctx_hdr; 3065 3066 for (pd = d; pd <= last; pd++) 3067 if (pd->transfer_status) 3068 break; 3069 if (pd > last) 3070 /* Descriptor(s) not done yet, stop iteration */ 3071 return 0; 3072 3073 sync_it_packet_for_cpu(context, d); 3074 3075 if (ctx->header_length + 4 > PAGE_SIZE) { 3076 if (ctx->base.drop_overflow_headers) 3077 return 1; 3078 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 3079 } 3080 3081 ctx_hdr = ctx->header + ctx->header_length; 3082 ctx->last_timestamp = le16_to_cpu(last->res_count); 3083 /* Present this value as big-endian to match the receive code */ 3084 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 3085 le16_to_cpu(pd->res_count)); 3086 ctx->header_length += 4; 3087 3088 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 3089 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 3090 3091 return 1; 3092 } 3093 3094 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 3095 { 3096 u32 hi = channels >> 32, lo = channels; 3097 3098 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 3099 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 3100 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 3101 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 3102 ohci->mc_channels = channels; 3103 } 3104 3105 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 3106 int type, int channel, size_t header_size) 3107 { 3108 struct fw_ohci *ohci = fw_ohci(card); 3109 struct iso_context *ctx; 3110 descriptor_callback_t callback; 3111 u64 *channels; 3112 u32 *mask, regs; 3113 int index, ret = -EBUSY; 3114 3115 scoped_guard(spinlock_irq, &ohci->lock) { 3116 switch (type) { 3117 case FW_ISO_CONTEXT_TRANSMIT: 3118 mask = &ohci->it_context_mask; 3119 callback = handle_it_packet; 3120 index = ffs(*mask) - 1; 3121 if (index >= 0) { 3122 *mask &= ~(1 << index); 3123 regs = OHCI1394_IsoXmitContextBase(index); 3124 ctx = &ohci->it_context_list[index]; 3125 } 3126 break; 3127 3128 case FW_ISO_CONTEXT_RECEIVE: 3129 channels = &ohci->ir_context_channels; 3130 mask = &ohci->ir_context_mask; 3131 callback = handle_ir_packet_per_buffer; 3132 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3133 if (index >= 0) { 3134 *channels &= ~(1ULL << channel); 3135 *mask &= ~(1 << index); 3136 regs = OHCI1394_IsoRcvContextBase(index); 3137 ctx = &ohci->ir_context_list[index]; 3138 } 3139 break; 3140 3141 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3142 mask = &ohci->ir_context_mask; 3143 callback = handle_ir_buffer_fill; 3144 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3145 if (index >= 0) { 3146 ohci->mc_allocated = true; 3147 *mask &= ~(1 << index); 3148 regs = OHCI1394_IsoRcvContextBase(index); 3149 ctx = &ohci->ir_context_list[index]; 3150 } 3151 break; 3152 3153 default: 3154 index = -1; 3155 ret = -ENOSYS; 3156 } 3157 3158 if (index < 0) 3159 return ERR_PTR(ret); 3160 } 3161 3162 memset(ctx, 0, sizeof(*ctx)); 3163 ctx->header_length = 0; 3164 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3165 if (ctx->header == NULL) { 3166 ret = -ENOMEM; 3167 goto out; 3168 } 3169 ret = context_init(&ctx->context, ohci, regs, callback); 3170 if (ret < 0) 3171 goto out_with_header; 3172 fw_iso_context_init_work(&ctx->base, ohci_isoc_context_work); 3173 3174 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3175 set_multichannel_mask(ohci, 0); 3176 ctx->mc_completed = 0; 3177 } 3178 3179 return &ctx->base; 3180 3181 out_with_header: 3182 free_page((unsigned long)ctx->header); 3183 out: 3184 scoped_guard(spinlock_irq, &ohci->lock) { 3185 switch (type) { 3186 case FW_ISO_CONTEXT_RECEIVE: 3187 *channels |= 1ULL << channel; 3188 break; 3189 3190 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3191 ohci->mc_allocated = false; 3192 break; 3193 } 3194 *mask |= 1 << index; 3195 } 3196 3197 return ERR_PTR(ret); 3198 } 3199 3200 static int ohci_start_iso(struct fw_iso_context *base, 3201 s32 cycle, u32 sync, u32 tags) 3202 { 3203 struct iso_context *ctx = container_of(base, struct iso_context, base); 3204 struct fw_ohci *ohci = ctx->context.ohci; 3205 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3206 int index; 3207 3208 /* the controller cannot start without any queued packets */ 3209 if (ctx->context.last->branch_address == 0) 3210 return -ENODATA; 3211 3212 switch (ctx->base.type) { 3213 case FW_ISO_CONTEXT_TRANSMIT: 3214 index = ctx - ohci->it_context_list; 3215 match = 0; 3216 if (cycle >= 0) 3217 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3218 (cycle & 0x7fff) << 16; 3219 3220 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3221 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3222 context_run(&ctx->context, match); 3223 break; 3224 3225 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3226 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3227 fallthrough; 3228 case FW_ISO_CONTEXT_RECEIVE: 3229 index = ctx - ohci->ir_context_list; 3230 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3231 if (cycle >= 0) { 3232 match |= (cycle & 0x07fff) << 12; 3233 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3234 } 3235 3236 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3237 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3238 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3239 context_run(&ctx->context, control); 3240 3241 ctx->sync = sync; 3242 ctx->tags = tags; 3243 3244 break; 3245 } 3246 3247 return 0; 3248 } 3249 3250 static int ohci_stop_iso(struct fw_iso_context *base) 3251 { 3252 struct fw_ohci *ohci = fw_ohci(base->card); 3253 struct iso_context *ctx = container_of(base, struct iso_context, base); 3254 int index; 3255 3256 switch (ctx->base.type) { 3257 case FW_ISO_CONTEXT_TRANSMIT: 3258 index = ctx - ohci->it_context_list; 3259 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3260 break; 3261 3262 case FW_ISO_CONTEXT_RECEIVE: 3263 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3264 index = ctx - ohci->ir_context_list; 3265 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3266 break; 3267 } 3268 flush_writes(ohci); 3269 context_stop(&ctx->context); 3270 3271 return 0; 3272 } 3273 3274 static void ohci_free_iso_context(struct fw_iso_context *base) 3275 { 3276 struct fw_ohci *ohci = fw_ohci(base->card); 3277 struct iso_context *ctx = container_of(base, struct iso_context, base); 3278 int index; 3279 3280 ohci_stop_iso(base); 3281 context_release(&ctx->context); 3282 free_page((unsigned long)ctx->header); 3283 3284 guard(spinlock_irqsave)(&ohci->lock); 3285 3286 switch (base->type) { 3287 case FW_ISO_CONTEXT_TRANSMIT: 3288 index = ctx - ohci->it_context_list; 3289 ohci->it_context_mask |= 1 << index; 3290 break; 3291 3292 case FW_ISO_CONTEXT_RECEIVE: 3293 index = ctx - ohci->ir_context_list; 3294 ohci->ir_context_mask |= 1 << index; 3295 ohci->ir_context_channels |= 1ULL << base->channel; 3296 break; 3297 3298 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3299 index = ctx - ohci->ir_context_list; 3300 ohci->ir_context_mask |= 1 << index; 3301 ohci->ir_context_channels |= ohci->mc_channels; 3302 ohci->mc_channels = 0; 3303 ohci->mc_allocated = false; 3304 break; 3305 } 3306 } 3307 3308 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3309 { 3310 struct fw_ohci *ohci = fw_ohci(base->card); 3311 3312 switch (base->type) { 3313 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3314 { 3315 guard(spinlock_irqsave)(&ohci->lock); 3316 3317 // Don't allow multichannel to grab other contexts' channels. 3318 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3319 *channels = ohci->ir_context_channels; 3320 return -EBUSY; 3321 } else { 3322 set_multichannel_mask(ohci, *channels); 3323 return 0; 3324 } 3325 } 3326 default: 3327 return -EINVAL; 3328 } 3329 } 3330 3331 #ifdef CONFIG_PM 3332 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3333 { 3334 int i; 3335 struct iso_context *ctx; 3336 3337 for (i = 0 ; i < ohci->n_ir ; i++) { 3338 ctx = &ohci->ir_context_list[i]; 3339 if (ctx->context.running) 3340 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3341 } 3342 3343 for (i = 0 ; i < ohci->n_it ; i++) { 3344 ctx = &ohci->it_context_list[i]; 3345 if (ctx->context.running) 3346 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3347 } 3348 } 3349 #endif 3350 3351 static int queue_iso_transmit(struct iso_context *ctx, 3352 struct fw_iso_packet *packet, 3353 struct fw_iso_buffer *buffer, 3354 unsigned long payload) 3355 { 3356 struct descriptor *d, *last, *pd; 3357 struct fw_iso_packet *p; 3358 __le32 *header; 3359 dma_addr_t d_bus, page_bus; 3360 u32 z, header_z, payload_z, irq; 3361 u32 payload_index, payload_end_index, next_page_index; 3362 int page, end_page, i, length, offset; 3363 3364 p = packet; 3365 payload_index = payload; 3366 3367 if (p->skip) 3368 z = 1; 3369 else 3370 z = 2; 3371 if (p->header_length > 0) 3372 z++; 3373 3374 /* Determine the first page the payload isn't contained in. */ 3375 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3376 if (p->payload_length > 0) 3377 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3378 else 3379 payload_z = 0; 3380 3381 z += payload_z; 3382 3383 /* Get header size in number of descriptors. */ 3384 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3385 3386 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3387 if (d == NULL) 3388 return -ENOMEM; 3389 3390 if (!p->skip) { 3391 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3392 d[0].req_count = cpu_to_le16(8); 3393 /* 3394 * Link the skip address to this descriptor itself. This causes 3395 * a context to skip a cycle whenever lost cycles or FIFO 3396 * overruns occur, without dropping the data. The application 3397 * should then decide whether this is an error condition or not. 3398 * FIXME: Make the context's cycle-lost behaviour configurable? 3399 */ 3400 d[0].branch_address = cpu_to_le32(d_bus | z); 3401 3402 header = (__le32 *) &d[1]; 3403 3404 ohci1394_it_data_set_speed(header, ctx->base.speed); 3405 ohci1394_it_data_set_tag(header, p->tag); 3406 ohci1394_it_data_set_channel(header, ctx->base.channel); 3407 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 3408 ohci1394_it_data_set_sync(header, p->sy); 3409 3410 ohci1394_it_data_set_data_length(header, p->header_length + p->payload_length); 3411 } 3412 3413 if (p->header_length > 0) { 3414 d[2].req_count = cpu_to_le16(p->header_length); 3415 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3416 memcpy(&d[z], p->header, p->header_length); 3417 } 3418 3419 pd = d + z - payload_z; 3420 payload_end_index = payload_index + p->payload_length; 3421 for (i = 0; i < payload_z; i++) { 3422 page = payload_index >> PAGE_SHIFT; 3423 offset = payload_index & ~PAGE_MASK; 3424 next_page_index = (page + 1) << PAGE_SHIFT; 3425 length = 3426 min(next_page_index, payload_end_index) - payload_index; 3427 pd[i].req_count = cpu_to_le16(length); 3428 3429 page_bus = page_private(buffer->pages[page]); 3430 pd[i].data_address = cpu_to_le32(page_bus + offset); 3431 3432 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3433 page_bus, offset, length, 3434 DMA_TO_DEVICE); 3435 3436 payload_index += length; 3437 } 3438 3439 if (p->interrupt) 3440 irq = DESCRIPTOR_IRQ_ALWAYS; 3441 else 3442 irq = DESCRIPTOR_NO_IRQ; 3443 3444 last = z == 2 ? d : d + z - 1; 3445 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3446 DESCRIPTOR_STATUS | 3447 DESCRIPTOR_BRANCH_ALWAYS | 3448 irq); 3449 3450 context_append(&ctx->context, d, z, header_z); 3451 3452 return 0; 3453 } 3454 3455 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3456 struct fw_iso_packet *packet, 3457 struct fw_iso_buffer *buffer, 3458 unsigned long payload) 3459 { 3460 struct device *device = ctx->context.ohci->card.device; 3461 struct descriptor *d, *pd; 3462 dma_addr_t d_bus, page_bus; 3463 u32 z, header_z, rest; 3464 int i, j, length; 3465 int page, offset, packet_count, header_size, payload_per_buffer; 3466 3467 /* 3468 * The OHCI controller puts the isochronous header and trailer in the 3469 * buffer, so we need at least 8 bytes. 3470 */ 3471 packet_count = packet->header_length / ctx->base.header_size; 3472 header_size = max(ctx->base.header_size, (size_t)8); 3473 3474 /* Get header size in number of descriptors. */ 3475 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3476 page = payload >> PAGE_SHIFT; 3477 offset = payload & ~PAGE_MASK; 3478 payload_per_buffer = packet->payload_length / packet_count; 3479 3480 for (i = 0; i < packet_count; i++) { 3481 /* d points to the header descriptor */ 3482 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3483 d = context_get_descriptors(&ctx->context, 3484 z + header_z, &d_bus); 3485 if (d == NULL) 3486 return -ENOMEM; 3487 3488 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3489 DESCRIPTOR_INPUT_MORE); 3490 if (packet->skip && i == 0) 3491 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3492 d->req_count = cpu_to_le16(header_size); 3493 d->res_count = d->req_count; 3494 d->transfer_status = 0; 3495 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3496 3497 rest = payload_per_buffer; 3498 pd = d; 3499 for (j = 1; j < z; j++) { 3500 pd++; 3501 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3502 DESCRIPTOR_INPUT_MORE); 3503 3504 if (offset + rest < PAGE_SIZE) 3505 length = rest; 3506 else 3507 length = PAGE_SIZE - offset; 3508 pd->req_count = cpu_to_le16(length); 3509 pd->res_count = pd->req_count; 3510 pd->transfer_status = 0; 3511 3512 page_bus = page_private(buffer->pages[page]); 3513 pd->data_address = cpu_to_le32(page_bus + offset); 3514 3515 dma_sync_single_range_for_device(device, page_bus, 3516 offset, length, 3517 DMA_FROM_DEVICE); 3518 3519 offset = (offset + length) & ~PAGE_MASK; 3520 rest -= length; 3521 if (offset == 0) 3522 page++; 3523 } 3524 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3525 DESCRIPTOR_INPUT_LAST | 3526 DESCRIPTOR_BRANCH_ALWAYS); 3527 if (packet->interrupt && i == packet_count - 1) 3528 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3529 3530 context_append(&ctx->context, d, z, header_z); 3531 } 3532 3533 return 0; 3534 } 3535 3536 static int queue_iso_buffer_fill(struct iso_context *ctx, 3537 struct fw_iso_packet *packet, 3538 struct fw_iso_buffer *buffer, 3539 unsigned long payload) 3540 { 3541 struct descriptor *d; 3542 dma_addr_t d_bus, page_bus; 3543 int page, offset, rest, z, i, length; 3544 3545 page = payload >> PAGE_SHIFT; 3546 offset = payload & ~PAGE_MASK; 3547 rest = packet->payload_length; 3548 3549 /* We need one descriptor for each page in the buffer. */ 3550 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3551 3552 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3553 return -EFAULT; 3554 3555 for (i = 0; i < z; i++) { 3556 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3557 if (d == NULL) 3558 return -ENOMEM; 3559 3560 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3561 DESCRIPTOR_BRANCH_ALWAYS); 3562 if (packet->skip && i == 0) 3563 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3564 if (packet->interrupt && i == z - 1) 3565 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3566 3567 if (offset + rest < PAGE_SIZE) 3568 length = rest; 3569 else 3570 length = PAGE_SIZE - offset; 3571 d->req_count = cpu_to_le16(length); 3572 d->res_count = d->req_count; 3573 d->transfer_status = 0; 3574 3575 page_bus = page_private(buffer->pages[page]); 3576 d->data_address = cpu_to_le32(page_bus + offset); 3577 3578 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3579 page_bus, offset, length, 3580 DMA_FROM_DEVICE); 3581 3582 rest -= length; 3583 offset = 0; 3584 page++; 3585 3586 context_append(&ctx->context, d, 1, 0); 3587 } 3588 3589 return 0; 3590 } 3591 3592 static int ohci_queue_iso(struct fw_iso_context *base, 3593 struct fw_iso_packet *packet, 3594 struct fw_iso_buffer *buffer, 3595 unsigned long payload) 3596 { 3597 struct iso_context *ctx = container_of(base, struct iso_context, base); 3598 3599 guard(spinlock_irqsave)(&ctx->context.ohci->lock); 3600 3601 switch (base->type) { 3602 case FW_ISO_CONTEXT_TRANSMIT: 3603 return queue_iso_transmit(ctx, packet, buffer, payload); 3604 case FW_ISO_CONTEXT_RECEIVE: 3605 return queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3606 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3607 return queue_iso_buffer_fill(ctx, packet, buffer, payload); 3608 default: 3609 return -ENOSYS; 3610 } 3611 } 3612 3613 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3614 { 3615 struct context *ctx = 3616 &container_of(base, struct iso_context, base)->context; 3617 3618 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3619 } 3620 3621 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3622 { 3623 struct iso_context *ctx = container_of(base, struct iso_context, base); 3624 int ret = 0; 3625 3626 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3627 ohci_isoc_context_work(&base->work); 3628 3629 switch (base->type) { 3630 case FW_ISO_CONTEXT_TRANSMIT: 3631 case FW_ISO_CONTEXT_RECEIVE: 3632 if (ctx->header_length != 0) 3633 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3634 break; 3635 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3636 if (ctx->mc_completed != 0) 3637 flush_ir_buffer_fill(ctx); 3638 break; 3639 default: 3640 ret = -ENOSYS; 3641 } 3642 3643 clear_bit_unlock(0, &ctx->flushing_completions); 3644 smp_mb__after_atomic(); 3645 } 3646 3647 return ret; 3648 } 3649 3650 static const struct fw_card_driver ohci_driver = { 3651 .enable = ohci_enable, 3652 .read_phy_reg = ohci_read_phy_reg, 3653 .update_phy_reg = ohci_update_phy_reg, 3654 .set_config_rom = ohci_set_config_rom, 3655 .send_request = ohci_send_request, 3656 .send_response = ohci_send_response, 3657 .cancel_packet = ohci_cancel_packet, 3658 .enable_phys_dma = ohci_enable_phys_dma, 3659 .read_csr = ohci_read_csr, 3660 .write_csr = ohci_write_csr, 3661 3662 .allocate_iso_context = ohci_allocate_iso_context, 3663 .free_iso_context = ohci_free_iso_context, 3664 .set_iso_channels = ohci_set_iso_channels, 3665 .queue_iso = ohci_queue_iso, 3666 .flush_queue_iso = ohci_flush_queue_iso, 3667 .flush_iso_completions = ohci_flush_iso_completions, 3668 .start_iso = ohci_start_iso, 3669 .stop_iso = ohci_stop_iso, 3670 }; 3671 3672 #ifdef CONFIG_PPC_PMAC 3673 static void pmac_ohci_on(struct pci_dev *dev) 3674 { 3675 if (machine_is(powermac)) { 3676 struct device_node *ofn = pci_device_to_OF_node(dev); 3677 3678 if (ofn) { 3679 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3680 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3681 } 3682 } 3683 } 3684 3685 static void pmac_ohci_off(struct pci_dev *dev) 3686 { 3687 if (machine_is(powermac)) { 3688 struct device_node *ofn = pci_device_to_OF_node(dev); 3689 3690 if (ofn) { 3691 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3692 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3693 } 3694 } 3695 } 3696 #else 3697 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3698 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3699 #endif /* CONFIG_PPC_PMAC */ 3700 3701 static void release_ohci(struct device *dev, void *data) 3702 { 3703 struct pci_dev *pdev = to_pci_dev(dev); 3704 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3705 3706 pmac_ohci_off(pdev); 3707 3708 ar_context_release(&ohci->ar_response_ctx); 3709 ar_context_release(&ohci->ar_request_ctx); 3710 3711 dev_notice(dev, "removed fw-ohci device\n"); 3712 } 3713 3714 static int pci_probe(struct pci_dev *dev, 3715 const struct pci_device_id *ent) 3716 { 3717 struct fw_ohci *ohci; 3718 u32 bus_options, max_receive, link_speed, version; 3719 u64 guid; 3720 int i, flags, irq, err; 3721 size_t size; 3722 3723 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3724 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3725 return -ENOSYS; 3726 } 3727 3728 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3729 if (ohci == NULL) 3730 return -ENOMEM; 3731 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3732 pci_set_drvdata(dev, ohci); 3733 pmac_ohci_on(dev); 3734 devres_add(&dev->dev, ohci); 3735 3736 err = pcim_enable_device(dev); 3737 if (err) { 3738 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3739 return err; 3740 } 3741 3742 pci_set_master(dev); 3743 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3744 3745 spin_lock_init(&ohci->lock); 3746 mutex_init(&ohci->phy_reg_mutex); 3747 3748 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3749 3750 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3751 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3752 ohci_err(ohci, "invalid MMIO resource\n"); 3753 return -ENXIO; 3754 } 3755 3756 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3757 if (err) { 3758 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3759 return -ENXIO; 3760 } 3761 ohci->registers = pcim_iomap_table(dev)[0]; 3762 3763 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3764 if ((ohci_quirks[i].vendor == dev->vendor) && 3765 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3766 ohci_quirks[i].device == dev->device) && 3767 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3768 ohci_quirks[i].revision >= dev->revision)) { 3769 ohci->quirks = ohci_quirks[i].flags; 3770 break; 3771 } 3772 if (param_quirks) 3773 ohci->quirks = param_quirks; 3774 3775 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3776 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3777 3778 /* 3779 * Because dma_alloc_coherent() allocates at least one page, 3780 * we save space by using a common buffer for the AR request/ 3781 * response descriptors and the self IDs buffer. 3782 */ 3783 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3784 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3785 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3786 GFP_KERNEL); 3787 if (!ohci->misc_buffer) 3788 return -ENOMEM; 3789 3790 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3791 OHCI1394_AsReqRcvContextControlSet); 3792 if (err < 0) 3793 return err; 3794 3795 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3796 OHCI1394_AsRspRcvContextControlSet); 3797 if (err < 0) 3798 return err; 3799 3800 err = context_init(&ohci->at_request_ctx, ohci, 3801 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3802 if (err < 0) 3803 return err; 3804 3805 err = context_init(&ohci->at_response_ctx, ohci, 3806 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3807 if (err < 0) 3808 return err; 3809 3810 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3811 ohci->ir_context_channels = ~0ULL; 3812 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3813 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3814 ohci->ir_context_mask = ohci->ir_context_support; 3815 ohci->n_ir = hweight32(ohci->ir_context_mask); 3816 size = sizeof(struct iso_context) * ohci->n_ir; 3817 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3818 if (!ohci->ir_context_list) 3819 return -ENOMEM; 3820 3821 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3822 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3823 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3824 if (!ohci->it_context_support) { 3825 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3826 ohci->it_context_support = 0xf; 3827 } 3828 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3829 ohci->it_context_mask = ohci->it_context_support; 3830 ohci->n_it = hweight32(ohci->it_context_mask); 3831 size = sizeof(struct iso_context) * ohci->n_it; 3832 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3833 if (!ohci->it_context_list) 3834 return -ENOMEM; 3835 3836 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3837 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3838 3839 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3840 max_receive = (bus_options >> 12) & 0xf; 3841 link_speed = bus_options & 0x7; 3842 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3843 reg_read(ohci, OHCI1394_GUIDLo); 3844 3845 flags = PCI_IRQ_INTX; 3846 if (!(ohci->quirks & QUIRK_NO_MSI)) 3847 flags |= PCI_IRQ_MSI; 3848 err = pci_alloc_irq_vectors(dev, 1, 1, flags); 3849 if (err < 0) 3850 return err; 3851 irq = pci_irq_vector(dev, 0); 3852 if (irq < 0) { 3853 err = irq; 3854 goto fail_msi; 3855 } 3856 3857 err = request_threaded_irq(irq, irq_handler, NULL, 3858 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, 3859 ohci); 3860 if (err < 0) { 3861 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); 3862 goto fail_msi; 3863 } 3864 3865 err = fw_card_add(&ohci->card, max_receive, link_speed, guid, ohci->n_it + ohci->n_ir); 3866 if (err) 3867 goto fail_irq; 3868 3869 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3870 ohci_notice(ohci, 3871 "added OHCI v%x.%x device as card %d, " 3872 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3873 version >> 16, version & 0xff, ohci->card.index, 3874 ohci->n_ir, ohci->n_it, ohci->quirks, 3875 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3876 ", physUB" : ""); 3877 3878 return 0; 3879 3880 fail_irq: 3881 free_irq(irq, ohci); 3882 fail_msi: 3883 pci_free_irq_vectors(dev); 3884 3885 return err; 3886 } 3887 3888 static void pci_remove(struct pci_dev *dev) 3889 { 3890 struct fw_ohci *ohci = pci_get_drvdata(dev); 3891 int irq; 3892 3893 /* 3894 * If the removal is happening from the suspend state, LPS won't be 3895 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3896 */ 3897 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3898 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3899 flush_writes(ohci); 3900 } 3901 cancel_work_sync(&ohci->bus_reset_work); 3902 fw_core_remove_card(&ohci->card); 3903 3904 /* 3905 * FIXME: Fail all pending packets here, now that the upper 3906 * layers can't queue any more. 3907 */ 3908 3909 software_reset(ohci); 3910 3911 irq = pci_irq_vector(dev, 0); 3912 if (irq >= 0) 3913 free_irq(irq, ohci); 3914 pci_free_irq_vectors(dev); 3915 3916 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3917 } 3918 3919 #ifdef CONFIG_PM 3920 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3921 { 3922 struct fw_ohci *ohci = pci_get_drvdata(dev); 3923 int err; 3924 3925 software_reset(ohci); 3926 err = pci_save_state(dev); 3927 if (err) { 3928 ohci_err(ohci, "pci_save_state failed\n"); 3929 return err; 3930 } 3931 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3932 if (err) 3933 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3934 pmac_ohci_off(dev); 3935 3936 return 0; 3937 } 3938 3939 static int pci_resume(struct pci_dev *dev) 3940 { 3941 struct fw_ohci *ohci = pci_get_drvdata(dev); 3942 int err; 3943 3944 pmac_ohci_on(dev); 3945 pci_set_power_state(dev, PCI_D0); 3946 pci_restore_state(dev); 3947 err = pci_enable_device(dev); 3948 if (err) { 3949 ohci_err(ohci, "pci_enable_device failed\n"); 3950 return err; 3951 } 3952 3953 /* Some systems don't setup GUID register on resume from ram */ 3954 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3955 !reg_read(ohci, OHCI1394_GUIDHi)) { 3956 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3957 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3958 } 3959 3960 err = ohci_enable(&ohci->card, NULL, 0); 3961 if (err) 3962 return err; 3963 3964 ohci_resume_iso_dma(ohci); 3965 3966 return 0; 3967 } 3968 #endif 3969 3970 static const struct pci_device_id pci_table[] = { 3971 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3972 { } 3973 }; 3974 3975 MODULE_DEVICE_TABLE(pci, pci_table); 3976 3977 static struct pci_driver fw_ohci_pci_driver = { 3978 .name = ohci_driver_name, 3979 .id_table = pci_table, 3980 .probe = pci_probe, 3981 .remove = pci_remove, 3982 #ifdef CONFIG_PM 3983 .resume = pci_resume, 3984 .suspend = pci_suspend, 3985 #endif 3986 }; 3987 3988 static int __init fw_ohci_init(void) 3989 { 3990 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3991 if (!selfid_workqueue) 3992 return -ENOMEM; 3993 3994 return pci_register_driver(&fw_ohci_pci_driver); 3995 } 3996 3997 static void __exit fw_ohci_cleanup(void) 3998 { 3999 pci_unregister_driver(&fw_ohci_pci_driver); 4000 destroy_workqueue(selfid_workqueue); 4001 } 4002 4003 module_init(fw_ohci_init); 4004 module_exit(fw_ohci_cleanup); 4005 4006 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 4007 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 4008 MODULE_LICENSE("GPL"); 4009 4010 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 4011 MODULE_ALIAS("ohci1394"); 4012