1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/bug.h> 23 #include <linux/compiler.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firewire.h> 28 #include <linux/firewire-constants.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/list.h> 34 #include <linux/mm.h> 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/string.h> 43 #include <linux/time.h> 44 #include <linux/vmalloc.h> 45 #include <linux/workqueue.h> 46 47 #include <asm/byteorder.h> 48 #include <asm/page.h> 49 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/pmac_feature.h> 52 #endif 53 54 #include "core.h" 55 #include "ohci.h" 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 struct descriptor { 72 __le16 req_count; 73 __le16 control; 74 __le32 data_address; 75 __le32 branch_address; 76 __le16 res_count; 77 __le16 transfer_status; 78 } __attribute__((aligned(16))); 79 80 #define CONTROL_SET(regs) (regs) 81 #define CONTROL_CLEAR(regs) ((regs) + 4) 82 #define COMMAND_PTR(regs) ((regs) + 12) 83 #define CONTEXT_MATCH(regs) ((regs) + 16) 84 85 #define AR_BUFFER_SIZE (32*1024) 86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 87 /* we need at least two pages for proper list management */ 88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 89 90 #define MAX_ASYNC_PAYLOAD 4096 91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 93 94 struct ar_context { 95 struct fw_ohci *ohci; 96 struct page *pages[AR_BUFFERS]; 97 void *buffer; 98 struct descriptor *descriptors; 99 dma_addr_t descriptors_bus; 100 void *pointer; 101 unsigned int last_buffer_index; 102 u32 regs; 103 struct tasklet_struct tasklet; 104 }; 105 106 struct context; 107 108 typedef int (*descriptor_callback_t)(struct context *ctx, 109 struct descriptor *d, 110 struct descriptor *last); 111 112 /* 113 * A buffer that contains a block of DMA-able coherent memory used for 114 * storing a portion of a DMA descriptor program. 115 */ 116 struct descriptor_buffer { 117 struct list_head list; 118 dma_addr_t buffer_bus; 119 size_t buffer_size; 120 size_t used; 121 struct descriptor buffer[0]; 122 }; 123 124 struct context { 125 struct fw_ohci *ohci; 126 u32 regs; 127 int total_allocation; 128 u32 current_bus; 129 bool running; 130 bool flushing; 131 132 /* 133 * List of page-sized buffers for storing DMA descriptors. 134 * Head of list contains buffers in use and tail of list contains 135 * free buffers. 136 */ 137 struct list_head buffer_list; 138 139 /* 140 * Pointer to a buffer inside buffer_list that contains the tail 141 * end of the current DMA program. 142 */ 143 struct descriptor_buffer *buffer_tail; 144 145 /* 146 * The descriptor containing the branch address of the first 147 * descriptor that has not yet been filled by the device. 148 */ 149 struct descriptor *last; 150 151 /* 152 * The last descriptor in the DMA program. It contains the branch 153 * address that must be updated upon appending a new descriptor. 154 */ 155 struct descriptor *prev; 156 157 descriptor_callback_t callback; 158 159 struct tasklet_struct tasklet; 160 }; 161 162 #define IT_HEADER_SY(v) ((v) << 0) 163 #define IT_HEADER_TCODE(v) ((v) << 4) 164 #define IT_HEADER_CHANNEL(v) ((v) << 8) 165 #define IT_HEADER_TAG(v) ((v) << 14) 166 #define IT_HEADER_SPEED(v) ((v) << 16) 167 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 168 169 struct iso_context { 170 struct fw_iso_context base; 171 struct context context; 172 void *header; 173 size_t header_length; 174 unsigned long flushing_completions; 175 u32 mc_buffer_bus; 176 u16 mc_completed; 177 u16 last_timestamp; 178 u8 sync; 179 u8 tags; 180 }; 181 182 #define CONFIG_ROM_SIZE 1024 183 184 struct fw_ohci { 185 struct fw_card card; 186 187 __iomem char *registers; 188 int node_id; 189 int generation; 190 int request_generation; /* for timestamping incoming requests */ 191 unsigned quirks; 192 unsigned int pri_req_max; 193 u32 bus_time; 194 bool is_root; 195 bool csr_state_setclear_abdicate; 196 int n_ir; 197 int n_it; 198 /* 199 * Spinlock for accessing fw_ohci data. Never call out of 200 * this driver with this lock held. 201 */ 202 spinlock_t lock; 203 204 struct mutex phy_reg_mutex; 205 206 void *misc_buffer; 207 dma_addr_t misc_buffer_bus; 208 209 struct ar_context ar_request_ctx; 210 struct ar_context ar_response_ctx; 211 struct context at_request_ctx; 212 struct context at_response_ctx; 213 214 u32 it_context_support; 215 u32 it_context_mask; /* unoccupied IT contexts */ 216 struct iso_context *it_context_list; 217 u64 ir_context_channels; /* unoccupied channels */ 218 u32 ir_context_support; 219 u32 ir_context_mask; /* unoccupied IR contexts */ 220 struct iso_context *ir_context_list; 221 u64 mc_channels; /* channels in use by the multichannel IR context */ 222 bool mc_allocated; 223 224 __be32 *config_rom; 225 dma_addr_t config_rom_bus; 226 __be32 *next_config_rom; 227 dma_addr_t next_config_rom_bus; 228 __be32 next_header; 229 230 __le32 *self_id_cpu; 231 dma_addr_t self_id_bus; 232 struct work_struct bus_reset_work; 233 234 u32 self_id_buffer[512]; 235 }; 236 237 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 238 { 239 return container_of(card, struct fw_ohci, card); 240 } 241 242 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 243 #define IR_CONTEXT_BUFFER_FILL 0x80000000 244 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 245 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 246 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 247 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 248 249 #define CONTEXT_RUN 0x8000 250 #define CONTEXT_WAKE 0x1000 251 #define CONTEXT_DEAD 0x0800 252 #define CONTEXT_ACTIVE 0x0400 253 254 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 255 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 256 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 257 258 #define OHCI1394_REGISTER_SIZE 0x800 259 #define OHCI1394_PCI_HCI_Control 0x40 260 #define SELF_ID_BUF_SIZE 0x800 261 #define OHCI_TCODE_PHY_PACKET 0x0e 262 #define OHCI_VERSION_1_1 0x010010 263 264 static char ohci_driver_name[] = KBUILD_MODNAME; 265 266 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 267 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 268 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 269 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 270 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 271 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 272 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 273 274 #define QUIRK_CYCLE_TIMER 1 275 #define QUIRK_RESET_PACKET 2 276 #define QUIRK_BE_HEADERS 4 277 #define QUIRK_NO_1394A 8 278 #define QUIRK_NO_MSI 16 279 #define QUIRK_TI_SLLZ059 32 280 281 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 282 static const struct { 283 unsigned short vendor, device, revision, flags; 284 } ohci_quirks[] = { 285 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 286 QUIRK_CYCLE_TIMER}, 287 288 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 289 QUIRK_BE_HEADERS}, 290 291 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 292 QUIRK_NO_MSI}, 293 294 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 295 QUIRK_RESET_PACKET}, 296 297 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 298 QUIRK_NO_MSI}, 299 300 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 301 QUIRK_CYCLE_TIMER}, 302 303 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 304 QUIRK_NO_MSI}, 305 306 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 307 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 308 309 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 310 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 311 312 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 313 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 314 315 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 316 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 317 318 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 319 QUIRK_RESET_PACKET}, 320 321 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 322 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 323 }; 324 325 /* This overrides anything that was found in ohci_quirks[]. */ 326 static int param_quirks; 327 module_param_named(quirks, param_quirks, int, 0644); 328 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 329 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 330 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 331 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) 332 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 333 ", disable MSI = " __stringify(QUIRK_NO_MSI) 334 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 335 ")"); 336 337 #define OHCI_PARAM_DEBUG_AT_AR 1 338 #define OHCI_PARAM_DEBUG_SELFIDS 2 339 #define OHCI_PARAM_DEBUG_IRQS 4 340 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 341 342 static int param_debug; 343 module_param_named(debug, param_debug, int, 0644); 344 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 345 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 346 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 347 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 348 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 349 ", or a combination, or all = -1)"); 350 351 static void log_irqs(struct fw_ohci *ohci, u32 evt) 352 { 353 if (likely(!(param_debug & 354 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 355 return; 356 357 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 358 !(evt & OHCI1394_busReset)) 359 return; 360 361 dev_notice(ohci->card.device, 362 "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 363 evt & OHCI1394_selfIDComplete ? " selfID" : "", 364 evt & OHCI1394_RQPkt ? " AR_req" : "", 365 evt & OHCI1394_RSPkt ? " AR_resp" : "", 366 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 367 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 368 evt & OHCI1394_isochRx ? " IR" : "", 369 evt & OHCI1394_isochTx ? " IT" : "", 370 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 371 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 372 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 373 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 374 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 375 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 376 evt & OHCI1394_busReset ? " busReset" : "", 377 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 378 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 379 OHCI1394_respTxComplete | OHCI1394_isochRx | 380 OHCI1394_isochTx | OHCI1394_postedWriteErr | 381 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 382 OHCI1394_cycleInconsistent | 383 OHCI1394_regAccessFail | OHCI1394_busReset) 384 ? " ?" : ""); 385 } 386 387 static const char *speed[] = { 388 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 389 }; 390 static const char *power[] = { 391 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 392 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 393 }; 394 static const char port[] = { '.', '-', 'p', 'c', }; 395 396 static char _p(u32 *s, int shift) 397 { 398 return port[*s >> shift & 3]; 399 } 400 401 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 402 { 403 u32 *s; 404 405 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 406 return; 407 408 dev_notice(ohci->card.device, 409 "%d selfIDs, generation %d, local node ID %04x\n", 410 self_id_count, generation, ohci->node_id); 411 412 for (s = ohci->self_id_buffer; self_id_count--; ++s) 413 if ((*s & 1 << 23) == 0) 414 dev_notice(ohci->card.device, 415 "selfID 0: %08x, phy %d [%c%c%c] " 416 "%s gc=%d %s %s%s%s\n", 417 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 418 speed[*s >> 14 & 3], *s >> 16 & 63, 419 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 420 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 421 else 422 dev_notice(ohci->card.device, 423 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 424 *s, *s >> 24 & 63, 425 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 426 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 427 } 428 429 static const char *evts[] = { 430 [0x00] = "evt_no_status", [0x01] = "-reserved-", 431 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 432 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 433 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 434 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 435 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 436 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 437 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 438 [0x10] = "-reserved-", [0x11] = "ack_complete", 439 [0x12] = "ack_pending ", [0x13] = "-reserved-", 440 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 441 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 442 [0x18] = "-reserved-", [0x19] = "-reserved-", 443 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 444 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 445 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 446 [0x20] = "pending/cancelled", 447 }; 448 static const char *tcodes[] = { 449 [0x0] = "QW req", [0x1] = "BW req", 450 [0x2] = "W resp", [0x3] = "-reserved-", 451 [0x4] = "QR req", [0x5] = "BR req", 452 [0x6] = "QR resp", [0x7] = "BR resp", 453 [0x8] = "cycle start", [0x9] = "Lk req", 454 [0xa] = "async stream packet", [0xb] = "Lk resp", 455 [0xc] = "-reserved-", [0xd] = "-reserved-", 456 [0xe] = "link internal", [0xf] = "-reserved-", 457 }; 458 459 static void log_ar_at_event(struct fw_ohci *ohci, 460 char dir, int speed, u32 *header, int evt) 461 { 462 int tcode = header[0] >> 4 & 0xf; 463 char specific[12]; 464 465 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 466 return; 467 468 if (unlikely(evt >= ARRAY_SIZE(evts))) 469 evt = 0x1f; 470 471 if (evt == OHCI1394_evt_bus_reset) { 472 dev_notice(ohci->card.device, 473 "A%c evt_bus_reset, generation %d\n", 474 dir, (header[2] >> 16) & 0xff); 475 return; 476 } 477 478 switch (tcode) { 479 case 0x0: case 0x6: case 0x8: 480 snprintf(specific, sizeof(specific), " = %08x", 481 be32_to_cpu((__force __be32)header[3])); 482 break; 483 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 484 snprintf(specific, sizeof(specific), " %x,%x", 485 header[3] >> 16, header[3] & 0xffff); 486 break; 487 default: 488 specific[0] = '\0'; 489 } 490 491 switch (tcode) { 492 case 0xa: 493 dev_notice(ohci->card.device, 494 "A%c %s, %s\n", 495 dir, evts[evt], tcodes[tcode]); 496 break; 497 case 0xe: 498 dev_notice(ohci->card.device, 499 "A%c %s, PHY %08x %08x\n", 500 dir, evts[evt], header[1], header[2]); 501 break; 502 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 503 dev_notice(ohci->card.device, 504 "A%c spd %x tl %02x, " 505 "%04x -> %04x, %s, " 506 "%s, %04x%08x%s\n", 507 dir, speed, header[0] >> 10 & 0x3f, 508 header[1] >> 16, header[0] >> 16, evts[evt], 509 tcodes[tcode], header[1] & 0xffff, header[2], specific); 510 break; 511 default: 512 dev_notice(ohci->card.device, 513 "A%c spd %x tl %02x, " 514 "%04x -> %04x, %s, " 515 "%s%s\n", 516 dir, speed, header[0] >> 10 & 0x3f, 517 header[1] >> 16, header[0] >> 16, evts[evt], 518 tcodes[tcode], specific); 519 } 520 } 521 522 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 523 { 524 writel(data, ohci->registers + offset); 525 } 526 527 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 528 { 529 return readl(ohci->registers + offset); 530 } 531 532 static inline void flush_writes(const struct fw_ohci *ohci) 533 { 534 /* Do a dummy read to flush writes. */ 535 reg_read(ohci, OHCI1394_Version); 536 } 537 538 /* 539 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 540 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 541 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 542 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 543 */ 544 static int read_phy_reg(struct fw_ohci *ohci, int addr) 545 { 546 u32 val; 547 int i; 548 549 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 550 for (i = 0; i < 3 + 100; i++) { 551 val = reg_read(ohci, OHCI1394_PhyControl); 552 if (!~val) 553 return -ENODEV; /* Card was ejected. */ 554 555 if (val & OHCI1394_PhyControl_ReadDone) 556 return OHCI1394_PhyControl_ReadData(val); 557 558 /* 559 * Try a few times without waiting. Sleeping is necessary 560 * only when the link/PHY interface is busy. 561 */ 562 if (i >= 3) 563 msleep(1); 564 } 565 dev_err(ohci->card.device, "failed to read phy reg\n"); 566 567 return -EBUSY; 568 } 569 570 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 571 { 572 int i; 573 574 reg_write(ohci, OHCI1394_PhyControl, 575 OHCI1394_PhyControl_Write(addr, val)); 576 for (i = 0; i < 3 + 100; i++) { 577 val = reg_read(ohci, OHCI1394_PhyControl); 578 if (!~val) 579 return -ENODEV; /* Card was ejected. */ 580 581 if (!(val & OHCI1394_PhyControl_WritePending)) 582 return 0; 583 584 if (i >= 3) 585 msleep(1); 586 } 587 dev_err(ohci->card.device, "failed to write phy reg\n"); 588 589 return -EBUSY; 590 } 591 592 static int update_phy_reg(struct fw_ohci *ohci, int addr, 593 int clear_bits, int set_bits) 594 { 595 int ret = read_phy_reg(ohci, addr); 596 if (ret < 0) 597 return ret; 598 599 /* 600 * The interrupt status bits are cleared by writing a one bit. 601 * Avoid clearing them unless explicitly requested in set_bits. 602 */ 603 if (addr == 5) 604 clear_bits |= PHY_INT_STATUS_BITS; 605 606 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 607 } 608 609 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 610 { 611 int ret; 612 613 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 614 if (ret < 0) 615 return ret; 616 617 return read_phy_reg(ohci, addr); 618 } 619 620 static int ohci_read_phy_reg(struct fw_card *card, int addr) 621 { 622 struct fw_ohci *ohci = fw_ohci(card); 623 int ret; 624 625 mutex_lock(&ohci->phy_reg_mutex); 626 ret = read_phy_reg(ohci, addr); 627 mutex_unlock(&ohci->phy_reg_mutex); 628 629 return ret; 630 } 631 632 static int ohci_update_phy_reg(struct fw_card *card, int addr, 633 int clear_bits, int set_bits) 634 { 635 struct fw_ohci *ohci = fw_ohci(card); 636 int ret; 637 638 mutex_lock(&ohci->phy_reg_mutex); 639 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 640 mutex_unlock(&ohci->phy_reg_mutex); 641 642 return ret; 643 } 644 645 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 646 { 647 return page_private(ctx->pages[i]); 648 } 649 650 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 651 { 652 struct descriptor *d; 653 654 d = &ctx->descriptors[index]; 655 d->branch_address &= cpu_to_le32(~0xf); 656 d->res_count = cpu_to_le16(PAGE_SIZE); 657 d->transfer_status = 0; 658 659 wmb(); /* finish init of new descriptors before branch_address update */ 660 d = &ctx->descriptors[ctx->last_buffer_index]; 661 d->branch_address |= cpu_to_le32(1); 662 663 ctx->last_buffer_index = index; 664 665 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 666 } 667 668 static void ar_context_release(struct ar_context *ctx) 669 { 670 unsigned int i; 671 672 if (ctx->buffer) 673 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); 674 675 for (i = 0; i < AR_BUFFERS; i++) 676 if (ctx->pages[i]) { 677 dma_unmap_page(ctx->ohci->card.device, 678 ar_buffer_bus(ctx, i), 679 PAGE_SIZE, DMA_FROM_DEVICE); 680 __free_page(ctx->pages[i]); 681 } 682 } 683 684 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 685 { 686 struct fw_ohci *ohci = ctx->ohci; 687 688 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 689 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 690 flush_writes(ohci); 691 692 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n", 693 error_msg); 694 } 695 /* FIXME: restart? */ 696 } 697 698 static inline unsigned int ar_next_buffer_index(unsigned int index) 699 { 700 return (index + 1) % AR_BUFFERS; 701 } 702 703 static inline unsigned int ar_prev_buffer_index(unsigned int index) 704 { 705 return (index - 1 + AR_BUFFERS) % AR_BUFFERS; 706 } 707 708 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 709 { 710 return ar_next_buffer_index(ctx->last_buffer_index); 711 } 712 713 /* 714 * We search for the buffer that contains the last AR packet DMA data written 715 * by the controller. 716 */ 717 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 718 unsigned int *buffer_offset) 719 { 720 unsigned int i, next_i, last = ctx->last_buffer_index; 721 __le16 res_count, next_res_count; 722 723 i = ar_first_buffer_index(ctx); 724 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); 725 726 /* A buffer that is not yet completely filled must be the last one. */ 727 while (i != last && res_count == 0) { 728 729 /* Peek at the next descriptor. */ 730 next_i = ar_next_buffer_index(i); 731 rmb(); /* read descriptors in order */ 732 next_res_count = ACCESS_ONCE( 733 ctx->descriptors[next_i].res_count); 734 /* 735 * If the next descriptor is still empty, we must stop at this 736 * descriptor. 737 */ 738 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 739 /* 740 * The exception is when the DMA data for one packet is 741 * split over three buffers; in this case, the middle 742 * buffer's descriptor might be never updated by the 743 * controller and look still empty, and we have to peek 744 * at the third one. 745 */ 746 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 747 next_i = ar_next_buffer_index(next_i); 748 rmb(); 749 next_res_count = ACCESS_ONCE( 750 ctx->descriptors[next_i].res_count); 751 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 752 goto next_buffer_is_active; 753 } 754 755 break; 756 } 757 758 next_buffer_is_active: 759 i = next_i; 760 res_count = next_res_count; 761 } 762 763 rmb(); /* read res_count before the DMA data */ 764 765 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 766 if (*buffer_offset > PAGE_SIZE) { 767 *buffer_offset = 0; 768 ar_context_abort(ctx, "corrupted descriptor"); 769 } 770 771 return i; 772 } 773 774 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 775 unsigned int end_buffer_index, 776 unsigned int end_buffer_offset) 777 { 778 unsigned int i; 779 780 i = ar_first_buffer_index(ctx); 781 while (i != end_buffer_index) { 782 dma_sync_single_for_cpu(ctx->ohci->card.device, 783 ar_buffer_bus(ctx, i), 784 PAGE_SIZE, DMA_FROM_DEVICE); 785 i = ar_next_buffer_index(i); 786 } 787 if (end_buffer_offset > 0) 788 dma_sync_single_for_cpu(ctx->ohci->card.device, 789 ar_buffer_bus(ctx, i), 790 end_buffer_offset, DMA_FROM_DEVICE); 791 } 792 793 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 794 #define cond_le32_to_cpu(v) \ 795 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 796 #else 797 #define cond_le32_to_cpu(v) le32_to_cpu(v) 798 #endif 799 800 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 801 { 802 struct fw_ohci *ohci = ctx->ohci; 803 struct fw_packet p; 804 u32 status, length, tcode; 805 int evt; 806 807 p.header[0] = cond_le32_to_cpu(buffer[0]); 808 p.header[1] = cond_le32_to_cpu(buffer[1]); 809 p.header[2] = cond_le32_to_cpu(buffer[2]); 810 811 tcode = (p.header[0] >> 4) & 0x0f; 812 switch (tcode) { 813 case TCODE_WRITE_QUADLET_REQUEST: 814 case TCODE_READ_QUADLET_RESPONSE: 815 p.header[3] = (__force __u32) buffer[3]; 816 p.header_length = 16; 817 p.payload_length = 0; 818 break; 819 820 case TCODE_READ_BLOCK_REQUEST : 821 p.header[3] = cond_le32_to_cpu(buffer[3]); 822 p.header_length = 16; 823 p.payload_length = 0; 824 break; 825 826 case TCODE_WRITE_BLOCK_REQUEST: 827 case TCODE_READ_BLOCK_RESPONSE: 828 case TCODE_LOCK_REQUEST: 829 case TCODE_LOCK_RESPONSE: 830 p.header[3] = cond_le32_to_cpu(buffer[3]); 831 p.header_length = 16; 832 p.payload_length = p.header[3] >> 16; 833 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 834 ar_context_abort(ctx, "invalid packet length"); 835 return NULL; 836 } 837 break; 838 839 case TCODE_WRITE_RESPONSE: 840 case TCODE_READ_QUADLET_REQUEST: 841 case OHCI_TCODE_PHY_PACKET: 842 p.header_length = 12; 843 p.payload_length = 0; 844 break; 845 846 default: 847 ar_context_abort(ctx, "invalid tcode"); 848 return NULL; 849 } 850 851 p.payload = (void *) buffer + p.header_length; 852 853 /* FIXME: What to do about evt_* errors? */ 854 length = (p.header_length + p.payload_length + 3) / 4; 855 status = cond_le32_to_cpu(buffer[length]); 856 evt = (status >> 16) & 0x1f; 857 858 p.ack = evt - 16; 859 p.speed = (status >> 21) & 0x7; 860 p.timestamp = status & 0xffff; 861 p.generation = ohci->request_generation; 862 863 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 864 865 /* 866 * Several controllers, notably from NEC and VIA, forget to 867 * write ack_complete status at PHY packet reception. 868 */ 869 if (evt == OHCI1394_evt_no_status && 870 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 871 p.ack = ACK_COMPLETE; 872 873 /* 874 * The OHCI bus reset handler synthesizes a PHY packet with 875 * the new generation number when a bus reset happens (see 876 * section 8.4.2.3). This helps us determine when a request 877 * was received and make sure we send the response in the same 878 * generation. We only need this for requests; for responses 879 * we use the unique tlabel for finding the matching 880 * request. 881 * 882 * Alas some chips sometimes emit bus reset packets with a 883 * wrong generation. We set the correct generation for these 884 * at a slightly incorrect time (in bus_reset_work). 885 */ 886 if (evt == OHCI1394_evt_bus_reset) { 887 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 888 ohci->request_generation = (p.header[2] >> 16) & 0xff; 889 } else if (ctx == &ohci->ar_request_ctx) { 890 fw_core_handle_request(&ohci->card, &p); 891 } else { 892 fw_core_handle_response(&ohci->card, &p); 893 } 894 895 return buffer + length + 1; 896 } 897 898 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 899 { 900 void *next; 901 902 while (p < end) { 903 next = handle_ar_packet(ctx, p); 904 if (!next) 905 return p; 906 p = next; 907 } 908 909 return p; 910 } 911 912 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 913 { 914 unsigned int i; 915 916 i = ar_first_buffer_index(ctx); 917 while (i != end_buffer) { 918 dma_sync_single_for_device(ctx->ohci->card.device, 919 ar_buffer_bus(ctx, i), 920 PAGE_SIZE, DMA_FROM_DEVICE); 921 ar_context_link_page(ctx, i); 922 i = ar_next_buffer_index(i); 923 } 924 } 925 926 static void ar_context_tasklet(unsigned long data) 927 { 928 struct ar_context *ctx = (struct ar_context *)data; 929 unsigned int end_buffer_index, end_buffer_offset; 930 void *p, *end; 931 932 p = ctx->pointer; 933 if (!p) 934 return; 935 936 end_buffer_index = ar_search_last_active_buffer(ctx, 937 &end_buffer_offset); 938 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 939 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 940 941 if (end_buffer_index < ar_first_buffer_index(ctx)) { 942 /* 943 * The filled part of the overall buffer wraps around; handle 944 * all packets up to the buffer end here. If the last packet 945 * wraps around, its tail will be visible after the buffer end 946 * because the buffer start pages are mapped there again. 947 */ 948 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 949 p = handle_ar_packets(ctx, p, buffer_end); 950 if (p < buffer_end) 951 goto error; 952 /* adjust p to point back into the actual buffer */ 953 p -= AR_BUFFERS * PAGE_SIZE; 954 } 955 956 p = handle_ar_packets(ctx, p, end); 957 if (p != end) { 958 if (p > end) 959 ar_context_abort(ctx, "inconsistent descriptor"); 960 goto error; 961 } 962 963 ctx->pointer = p; 964 ar_recycle_buffers(ctx, end_buffer_index); 965 966 return; 967 968 error: 969 ctx->pointer = NULL; 970 } 971 972 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 973 unsigned int descriptors_offset, u32 regs) 974 { 975 unsigned int i; 976 dma_addr_t dma_addr; 977 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 978 struct descriptor *d; 979 980 ctx->regs = regs; 981 ctx->ohci = ohci; 982 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 983 984 for (i = 0; i < AR_BUFFERS; i++) { 985 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); 986 if (!ctx->pages[i]) 987 goto out_of_memory; 988 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], 989 0, PAGE_SIZE, DMA_FROM_DEVICE); 990 if (dma_mapping_error(ohci->card.device, dma_addr)) { 991 __free_page(ctx->pages[i]); 992 ctx->pages[i] = NULL; 993 goto out_of_memory; 994 } 995 set_page_private(ctx->pages[i], dma_addr); 996 } 997 998 for (i = 0; i < AR_BUFFERS; i++) 999 pages[i] = ctx->pages[i]; 1000 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1001 pages[AR_BUFFERS + i] = ctx->pages[i]; 1002 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, 1003 -1, PAGE_KERNEL); 1004 if (!ctx->buffer) 1005 goto out_of_memory; 1006 1007 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1008 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1009 1010 for (i = 0; i < AR_BUFFERS; i++) { 1011 d = &ctx->descriptors[i]; 1012 d->req_count = cpu_to_le16(PAGE_SIZE); 1013 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1014 DESCRIPTOR_STATUS | 1015 DESCRIPTOR_BRANCH_ALWAYS); 1016 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1017 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1018 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1019 } 1020 1021 return 0; 1022 1023 out_of_memory: 1024 ar_context_release(ctx); 1025 1026 return -ENOMEM; 1027 } 1028 1029 static void ar_context_run(struct ar_context *ctx) 1030 { 1031 unsigned int i; 1032 1033 for (i = 0; i < AR_BUFFERS; i++) 1034 ar_context_link_page(ctx, i); 1035 1036 ctx->pointer = ctx->buffer; 1037 1038 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1039 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1040 } 1041 1042 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1043 { 1044 __le16 branch; 1045 1046 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1047 1048 /* figure out which descriptor the branch address goes in */ 1049 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1050 return d; 1051 else 1052 return d + z - 1; 1053 } 1054 1055 static void context_tasklet(unsigned long data) 1056 { 1057 struct context *ctx = (struct context *) data; 1058 struct descriptor *d, *last; 1059 u32 address; 1060 int z; 1061 struct descriptor_buffer *desc; 1062 1063 desc = list_entry(ctx->buffer_list.next, 1064 struct descriptor_buffer, list); 1065 last = ctx->last; 1066 while (last->branch_address != 0) { 1067 struct descriptor_buffer *old_desc = desc; 1068 address = le32_to_cpu(last->branch_address); 1069 z = address & 0xf; 1070 address &= ~0xf; 1071 ctx->current_bus = address; 1072 1073 /* If the branch address points to a buffer outside of the 1074 * current buffer, advance to the next buffer. */ 1075 if (address < desc->buffer_bus || 1076 address >= desc->buffer_bus + desc->used) 1077 desc = list_entry(desc->list.next, 1078 struct descriptor_buffer, list); 1079 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1080 last = find_branch_descriptor(d, z); 1081 1082 if (!ctx->callback(ctx, d, last)) 1083 break; 1084 1085 if (old_desc != desc) { 1086 /* If we've advanced to the next buffer, move the 1087 * previous buffer to the free list. */ 1088 unsigned long flags; 1089 old_desc->used = 0; 1090 spin_lock_irqsave(&ctx->ohci->lock, flags); 1091 list_move_tail(&old_desc->list, &ctx->buffer_list); 1092 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1093 } 1094 ctx->last = last; 1095 } 1096 } 1097 1098 /* 1099 * Allocate a new buffer and add it to the list of free buffers for this 1100 * context. Must be called with ohci->lock held. 1101 */ 1102 static int context_add_buffer(struct context *ctx) 1103 { 1104 struct descriptor_buffer *desc; 1105 dma_addr_t uninitialized_var(bus_addr); 1106 int offset; 1107 1108 /* 1109 * 16MB of descriptors should be far more than enough for any DMA 1110 * program. This will catch run-away userspace or DoS attacks. 1111 */ 1112 if (ctx->total_allocation >= 16*1024*1024) 1113 return -ENOMEM; 1114 1115 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1116 &bus_addr, GFP_ATOMIC); 1117 if (!desc) 1118 return -ENOMEM; 1119 1120 offset = (void *)&desc->buffer - (void *)desc; 1121 desc->buffer_size = PAGE_SIZE - offset; 1122 desc->buffer_bus = bus_addr + offset; 1123 desc->used = 0; 1124 1125 list_add_tail(&desc->list, &ctx->buffer_list); 1126 ctx->total_allocation += PAGE_SIZE; 1127 1128 return 0; 1129 } 1130 1131 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1132 u32 regs, descriptor_callback_t callback) 1133 { 1134 ctx->ohci = ohci; 1135 ctx->regs = regs; 1136 ctx->total_allocation = 0; 1137 1138 INIT_LIST_HEAD(&ctx->buffer_list); 1139 if (context_add_buffer(ctx) < 0) 1140 return -ENOMEM; 1141 1142 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1143 struct descriptor_buffer, list); 1144 1145 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1146 ctx->callback = callback; 1147 1148 /* 1149 * We put a dummy descriptor in the buffer that has a NULL 1150 * branch address and looks like it's been sent. That way we 1151 * have a descriptor to append DMA programs to. 1152 */ 1153 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1154 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1155 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1156 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1157 ctx->last = ctx->buffer_tail->buffer; 1158 ctx->prev = ctx->buffer_tail->buffer; 1159 1160 return 0; 1161 } 1162 1163 static void context_release(struct context *ctx) 1164 { 1165 struct fw_card *card = &ctx->ohci->card; 1166 struct descriptor_buffer *desc, *tmp; 1167 1168 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1169 dma_free_coherent(card->device, PAGE_SIZE, desc, 1170 desc->buffer_bus - 1171 ((void *)&desc->buffer - (void *)desc)); 1172 } 1173 1174 /* Must be called with ohci->lock held */ 1175 static struct descriptor *context_get_descriptors(struct context *ctx, 1176 int z, dma_addr_t *d_bus) 1177 { 1178 struct descriptor *d = NULL; 1179 struct descriptor_buffer *desc = ctx->buffer_tail; 1180 1181 if (z * sizeof(*d) > desc->buffer_size) 1182 return NULL; 1183 1184 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1185 /* No room for the descriptor in this buffer, so advance to the 1186 * next one. */ 1187 1188 if (desc->list.next == &ctx->buffer_list) { 1189 /* If there is no free buffer next in the list, 1190 * allocate one. */ 1191 if (context_add_buffer(ctx) < 0) 1192 return NULL; 1193 } 1194 desc = list_entry(desc->list.next, 1195 struct descriptor_buffer, list); 1196 ctx->buffer_tail = desc; 1197 } 1198 1199 d = desc->buffer + desc->used / sizeof(*d); 1200 memset(d, 0, z * sizeof(*d)); 1201 *d_bus = desc->buffer_bus + desc->used; 1202 1203 return d; 1204 } 1205 1206 static void context_run(struct context *ctx, u32 extra) 1207 { 1208 struct fw_ohci *ohci = ctx->ohci; 1209 1210 reg_write(ohci, COMMAND_PTR(ctx->regs), 1211 le32_to_cpu(ctx->last->branch_address)); 1212 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1213 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1214 ctx->running = true; 1215 flush_writes(ohci); 1216 } 1217 1218 static void context_append(struct context *ctx, 1219 struct descriptor *d, int z, int extra) 1220 { 1221 dma_addr_t d_bus; 1222 struct descriptor_buffer *desc = ctx->buffer_tail; 1223 1224 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1225 1226 desc->used += (z + extra) * sizeof(*d); 1227 1228 wmb(); /* finish init of new descriptors before branch_address update */ 1229 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1230 ctx->prev = find_branch_descriptor(d, z); 1231 } 1232 1233 static void context_stop(struct context *ctx) 1234 { 1235 struct fw_ohci *ohci = ctx->ohci; 1236 u32 reg; 1237 int i; 1238 1239 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1240 ctx->running = false; 1241 1242 for (i = 0; i < 1000; i++) { 1243 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1244 if ((reg & CONTEXT_ACTIVE) == 0) 1245 return; 1246 1247 if (i) 1248 udelay(10); 1249 } 1250 dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg); 1251 } 1252 1253 struct driver_data { 1254 u8 inline_data[8]; 1255 struct fw_packet *packet; 1256 }; 1257 1258 /* 1259 * This function apppends a packet to the DMA queue for transmission. 1260 * Must always be called with the ochi->lock held to ensure proper 1261 * generation handling and locking around packet queue manipulation. 1262 */ 1263 static int at_context_queue_packet(struct context *ctx, 1264 struct fw_packet *packet) 1265 { 1266 struct fw_ohci *ohci = ctx->ohci; 1267 dma_addr_t d_bus, uninitialized_var(payload_bus); 1268 struct driver_data *driver_data; 1269 struct descriptor *d, *last; 1270 __le32 *header; 1271 int z, tcode; 1272 1273 d = context_get_descriptors(ctx, 4, &d_bus); 1274 if (d == NULL) { 1275 packet->ack = RCODE_SEND_ERROR; 1276 return -1; 1277 } 1278 1279 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1280 d[0].res_count = cpu_to_le16(packet->timestamp); 1281 1282 /* 1283 * The DMA format for asyncronous link packets is different 1284 * from the IEEE1394 layout, so shift the fields around 1285 * accordingly. 1286 */ 1287 1288 tcode = (packet->header[0] >> 4) & 0x0f; 1289 header = (__le32 *) &d[1]; 1290 switch (tcode) { 1291 case TCODE_WRITE_QUADLET_REQUEST: 1292 case TCODE_WRITE_BLOCK_REQUEST: 1293 case TCODE_WRITE_RESPONSE: 1294 case TCODE_READ_QUADLET_REQUEST: 1295 case TCODE_READ_BLOCK_REQUEST: 1296 case TCODE_READ_QUADLET_RESPONSE: 1297 case TCODE_READ_BLOCK_RESPONSE: 1298 case TCODE_LOCK_REQUEST: 1299 case TCODE_LOCK_RESPONSE: 1300 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1301 (packet->speed << 16)); 1302 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1303 (packet->header[0] & 0xffff0000)); 1304 header[2] = cpu_to_le32(packet->header[2]); 1305 1306 if (TCODE_IS_BLOCK_PACKET(tcode)) 1307 header[3] = cpu_to_le32(packet->header[3]); 1308 else 1309 header[3] = (__force __le32) packet->header[3]; 1310 1311 d[0].req_count = cpu_to_le16(packet->header_length); 1312 break; 1313 1314 case TCODE_LINK_INTERNAL: 1315 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1316 (packet->speed << 16)); 1317 header[1] = cpu_to_le32(packet->header[1]); 1318 header[2] = cpu_to_le32(packet->header[2]); 1319 d[0].req_count = cpu_to_le16(12); 1320 1321 if (is_ping_packet(&packet->header[1])) 1322 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1323 break; 1324 1325 case TCODE_STREAM_DATA: 1326 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1327 (packet->speed << 16)); 1328 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1329 d[0].req_count = cpu_to_le16(8); 1330 break; 1331 1332 default: 1333 /* BUG(); */ 1334 packet->ack = RCODE_SEND_ERROR; 1335 return -1; 1336 } 1337 1338 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1339 driver_data = (struct driver_data *) &d[3]; 1340 driver_data->packet = packet; 1341 packet->driver_data = driver_data; 1342 1343 if (packet->payload_length > 0) { 1344 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1345 payload_bus = dma_map_single(ohci->card.device, 1346 packet->payload, 1347 packet->payload_length, 1348 DMA_TO_DEVICE); 1349 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1350 packet->ack = RCODE_SEND_ERROR; 1351 return -1; 1352 } 1353 packet->payload_bus = payload_bus; 1354 packet->payload_mapped = true; 1355 } else { 1356 memcpy(driver_data->inline_data, packet->payload, 1357 packet->payload_length); 1358 payload_bus = d_bus + 3 * sizeof(*d); 1359 } 1360 1361 d[2].req_count = cpu_to_le16(packet->payload_length); 1362 d[2].data_address = cpu_to_le32(payload_bus); 1363 last = &d[2]; 1364 z = 3; 1365 } else { 1366 last = &d[0]; 1367 z = 2; 1368 } 1369 1370 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1371 DESCRIPTOR_IRQ_ALWAYS | 1372 DESCRIPTOR_BRANCH_ALWAYS); 1373 1374 /* FIXME: Document how the locking works. */ 1375 if (ohci->generation != packet->generation) { 1376 if (packet->payload_mapped) 1377 dma_unmap_single(ohci->card.device, payload_bus, 1378 packet->payload_length, DMA_TO_DEVICE); 1379 packet->ack = RCODE_GENERATION; 1380 return -1; 1381 } 1382 1383 context_append(ctx, d, z, 4 - z); 1384 1385 if (ctx->running) 1386 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1387 else 1388 context_run(ctx, 0); 1389 1390 return 0; 1391 } 1392 1393 static void at_context_flush(struct context *ctx) 1394 { 1395 tasklet_disable(&ctx->tasklet); 1396 1397 ctx->flushing = true; 1398 context_tasklet((unsigned long)ctx); 1399 ctx->flushing = false; 1400 1401 tasklet_enable(&ctx->tasklet); 1402 } 1403 1404 static int handle_at_packet(struct context *context, 1405 struct descriptor *d, 1406 struct descriptor *last) 1407 { 1408 struct driver_data *driver_data; 1409 struct fw_packet *packet; 1410 struct fw_ohci *ohci = context->ohci; 1411 int evt; 1412 1413 if (last->transfer_status == 0 && !context->flushing) 1414 /* This descriptor isn't done yet, stop iteration. */ 1415 return 0; 1416 1417 driver_data = (struct driver_data *) &d[3]; 1418 packet = driver_data->packet; 1419 if (packet == NULL) 1420 /* This packet was cancelled, just continue. */ 1421 return 1; 1422 1423 if (packet->payload_mapped) 1424 dma_unmap_single(ohci->card.device, packet->payload_bus, 1425 packet->payload_length, DMA_TO_DEVICE); 1426 1427 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1428 packet->timestamp = le16_to_cpu(last->res_count); 1429 1430 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1431 1432 switch (evt) { 1433 case OHCI1394_evt_timeout: 1434 /* Async response transmit timed out. */ 1435 packet->ack = RCODE_CANCELLED; 1436 break; 1437 1438 case OHCI1394_evt_flushed: 1439 /* 1440 * The packet was flushed should give same error as 1441 * when we try to use a stale generation count. 1442 */ 1443 packet->ack = RCODE_GENERATION; 1444 break; 1445 1446 case OHCI1394_evt_missing_ack: 1447 if (context->flushing) 1448 packet->ack = RCODE_GENERATION; 1449 else { 1450 /* 1451 * Using a valid (current) generation count, but the 1452 * node is not on the bus or not sending acks. 1453 */ 1454 packet->ack = RCODE_NO_ACK; 1455 } 1456 break; 1457 1458 case ACK_COMPLETE + 0x10: 1459 case ACK_PENDING + 0x10: 1460 case ACK_BUSY_X + 0x10: 1461 case ACK_BUSY_A + 0x10: 1462 case ACK_BUSY_B + 0x10: 1463 case ACK_DATA_ERROR + 0x10: 1464 case ACK_TYPE_ERROR + 0x10: 1465 packet->ack = evt - 0x10; 1466 break; 1467 1468 case OHCI1394_evt_no_status: 1469 if (context->flushing) { 1470 packet->ack = RCODE_GENERATION; 1471 break; 1472 } 1473 /* fall through */ 1474 1475 default: 1476 packet->ack = RCODE_SEND_ERROR; 1477 break; 1478 } 1479 1480 packet->callback(packet, &ohci->card, packet->ack); 1481 1482 return 1; 1483 } 1484 1485 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1486 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1487 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1488 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1489 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1490 1491 static void handle_local_rom(struct fw_ohci *ohci, 1492 struct fw_packet *packet, u32 csr) 1493 { 1494 struct fw_packet response; 1495 int tcode, length, i; 1496 1497 tcode = HEADER_GET_TCODE(packet->header[0]); 1498 if (TCODE_IS_BLOCK_PACKET(tcode)) 1499 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1500 else 1501 length = 4; 1502 1503 i = csr - CSR_CONFIG_ROM; 1504 if (i + length > CONFIG_ROM_SIZE) { 1505 fw_fill_response(&response, packet->header, 1506 RCODE_ADDRESS_ERROR, NULL, 0); 1507 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1508 fw_fill_response(&response, packet->header, 1509 RCODE_TYPE_ERROR, NULL, 0); 1510 } else { 1511 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1512 (void *) ohci->config_rom + i, length); 1513 } 1514 1515 fw_core_handle_response(&ohci->card, &response); 1516 } 1517 1518 static void handle_local_lock(struct fw_ohci *ohci, 1519 struct fw_packet *packet, u32 csr) 1520 { 1521 struct fw_packet response; 1522 int tcode, length, ext_tcode, sel, try; 1523 __be32 *payload, lock_old; 1524 u32 lock_arg, lock_data; 1525 1526 tcode = HEADER_GET_TCODE(packet->header[0]); 1527 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1528 payload = packet->payload; 1529 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1530 1531 if (tcode == TCODE_LOCK_REQUEST && 1532 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1533 lock_arg = be32_to_cpu(payload[0]); 1534 lock_data = be32_to_cpu(payload[1]); 1535 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1536 lock_arg = 0; 1537 lock_data = 0; 1538 } else { 1539 fw_fill_response(&response, packet->header, 1540 RCODE_TYPE_ERROR, NULL, 0); 1541 goto out; 1542 } 1543 1544 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1545 reg_write(ohci, OHCI1394_CSRData, lock_data); 1546 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1547 reg_write(ohci, OHCI1394_CSRControl, sel); 1548 1549 for (try = 0; try < 20; try++) 1550 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1551 lock_old = cpu_to_be32(reg_read(ohci, 1552 OHCI1394_CSRData)); 1553 fw_fill_response(&response, packet->header, 1554 RCODE_COMPLETE, 1555 &lock_old, sizeof(lock_old)); 1556 goto out; 1557 } 1558 1559 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n"); 1560 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1561 1562 out: 1563 fw_core_handle_response(&ohci->card, &response); 1564 } 1565 1566 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1567 { 1568 u64 offset, csr; 1569 1570 if (ctx == &ctx->ohci->at_request_ctx) { 1571 packet->ack = ACK_PENDING; 1572 packet->callback(packet, &ctx->ohci->card, packet->ack); 1573 } 1574 1575 offset = 1576 ((unsigned long long) 1577 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1578 packet->header[2]; 1579 csr = offset - CSR_REGISTER_BASE; 1580 1581 /* Handle config rom reads. */ 1582 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1583 handle_local_rom(ctx->ohci, packet, csr); 1584 else switch (csr) { 1585 case CSR_BUS_MANAGER_ID: 1586 case CSR_BANDWIDTH_AVAILABLE: 1587 case CSR_CHANNELS_AVAILABLE_HI: 1588 case CSR_CHANNELS_AVAILABLE_LO: 1589 handle_local_lock(ctx->ohci, packet, csr); 1590 break; 1591 default: 1592 if (ctx == &ctx->ohci->at_request_ctx) 1593 fw_core_handle_request(&ctx->ohci->card, packet); 1594 else 1595 fw_core_handle_response(&ctx->ohci->card, packet); 1596 break; 1597 } 1598 1599 if (ctx == &ctx->ohci->at_response_ctx) { 1600 packet->ack = ACK_COMPLETE; 1601 packet->callback(packet, &ctx->ohci->card, packet->ack); 1602 } 1603 } 1604 1605 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1606 { 1607 unsigned long flags; 1608 int ret; 1609 1610 spin_lock_irqsave(&ctx->ohci->lock, flags); 1611 1612 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1613 ctx->ohci->generation == packet->generation) { 1614 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1615 handle_local_request(ctx, packet); 1616 return; 1617 } 1618 1619 ret = at_context_queue_packet(ctx, packet); 1620 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1621 1622 if (ret < 0) 1623 packet->callback(packet, &ctx->ohci->card, packet->ack); 1624 1625 } 1626 1627 static void detect_dead_context(struct fw_ohci *ohci, 1628 const char *name, unsigned int regs) 1629 { 1630 u32 ctl; 1631 1632 ctl = reg_read(ohci, CONTROL_SET(regs)); 1633 if (ctl & CONTEXT_DEAD) 1634 dev_err(ohci->card.device, 1635 "DMA context %s has stopped, error code: %s\n", 1636 name, evts[ctl & 0x1f]); 1637 } 1638 1639 static void handle_dead_contexts(struct fw_ohci *ohci) 1640 { 1641 unsigned int i; 1642 char name[8]; 1643 1644 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1645 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1646 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1647 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1648 for (i = 0; i < 32; ++i) { 1649 if (!(ohci->it_context_support & (1 << i))) 1650 continue; 1651 sprintf(name, "IT%u", i); 1652 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1653 } 1654 for (i = 0; i < 32; ++i) { 1655 if (!(ohci->ir_context_support & (1 << i))) 1656 continue; 1657 sprintf(name, "IR%u", i); 1658 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1659 } 1660 /* TODO: maybe try to flush and restart the dead contexts */ 1661 } 1662 1663 static u32 cycle_timer_ticks(u32 cycle_timer) 1664 { 1665 u32 ticks; 1666 1667 ticks = cycle_timer & 0xfff; 1668 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1669 ticks += (3072 * 8000) * (cycle_timer >> 25); 1670 1671 return ticks; 1672 } 1673 1674 /* 1675 * Some controllers exhibit one or more of the following bugs when updating the 1676 * iso cycle timer register: 1677 * - When the lowest six bits are wrapping around to zero, a read that happens 1678 * at the same time will return garbage in the lowest ten bits. 1679 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1680 * not incremented for about 60 ns. 1681 * - Occasionally, the entire register reads zero. 1682 * 1683 * To catch these, we read the register three times and ensure that the 1684 * difference between each two consecutive reads is approximately the same, i.e. 1685 * less than twice the other. Furthermore, any negative difference indicates an 1686 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1687 * execute, so we have enough precision to compute the ratio of the differences.) 1688 */ 1689 static u32 get_cycle_time(struct fw_ohci *ohci) 1690 { 1691 u32 c0, c1, c2; 1692 u32 t0, t1, t2; 1693 s32 diff01, diff12; 1694 int i; 1695 1696 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1697 1698 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1699 i = 0; 1700 c1 = c2; 1701 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1702 do { 1703 c0 = c1; 1704 c1 = c2; 1705 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1706 t0 = cycle_timer_ticks(c0); 1707 t1 = cycle_timer_ticks(c1); 1708 t2 = cycle_timer_ticks(c2); 1709 diff01 = t1 - t0; 1710 diff12 = t2 - t1; 1711 } while ((diff01 <= 0 || diff12 <= 0 || 1712 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1713 && i++ < 20); 1714 } 1715 1716 return c2; 1717 } 1718 1719 /* 1720 * This function has to be called at least every 64 seconds. The bus_time 1721 * field stores not only the upper 25 bits of the BUS_TIME register but also 1722 * the most significant bit of the cycle timer in bit 6 so that we can detect 1723 * changes in this bit. 1724 */ 1725 static u32 update_bus_time(struct fw_ohci *ohci) 1726 { 1727 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1728 1729 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1730 ohci->bus_time += 0x40; 1731 1732 return ohci->bus_time | cycle_time_seconds; 1733 } 1734 1735 static int get_status_for_port(struct fw_ohci *ohci, int port_index) 1736 { 1737 int reg; 1738 1739 mutex_lock(&ohci->phy_reg_mutex); 1740 reg = write_phy_reg(ohci, 7, port_index); 1741 if (reg >= 0) 1742 reg = read_phy_reg(ohci, 8); 1743 mutex_unlock(&ohci->phy_reg_mutex); 1744 if (reg < 0) 1745 return reg; 1746 1747 switch (reg & 0x0f) { 1748 case 0x06: 1749 return 2; /* is child node (connected to parent node) */ 1750 case 0x0e: 1751 return 3; /* is parent node (connected to child node) */ 1752 } 1753 return 1; /* not connected */ 1754 } 1755 1756 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1757 int self_id_count) 1758 { 1759 int i; 1760 u32 entry; 1761 1762 for (i = 0; i < self_id_count; i++) { 1763 entry = ohci->self_id_buffer[i]; 1764 if ((self_id & 0xff000000) == (entry & 0xff000000)) 1765 return -1; 1766 if ((self_id & 0xff000000) < (entry & 0xff000000)) 1767 return i; 1768 } 1769 return i; 1770 } 1771 1772 /* 1773 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1774 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1775 * Construct the selfID from phy register contents. 1776 * FIXME: How to determine the selfID.i flag? 1777 */ 1778 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1779 { 1780 int reg, i, pos, status; 1781 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */ 1782 u32 self_id = 0x8040c800; 1783 1784 reg = reg_read(ohci, OHCI1394_NodeID); 1785 if (!(reg & OHCI1394_NodeID_idValid)) { 1786 dev_notice(ohci->card.device, 1787 "node ID not valid, new bus reset in progress\n"); 1788 return -EBUSY; 1789 } 1790 self_id |= ((reg & 0x3f) << 24); /* phy ID */ 1791 1792 reg = ohci_read_phy_reg(&ohci->card, 4); 1793 if (reg < 0) 1794 return reg; 1795 self_id |= ((reg & 0x07) << 8); /* power class */ 1796 1797 reg = ohci_read_phy_reg(&ohci->card, 1); 1798 if (reg < 0) 1799 return reg; 1800 self_id |= ((reg & 0x3f) << 16); /* gap count */ 1801 1802 for (i = 0; i < 3; i++) { 1803 status = get_status_for_port(ohci, i); 1804 if (status < 0) 1805 return status; 1806 self_id |= ((status & 0x3) << (6 - (i * 2))); 1807 } 1808 1809 pos = get_self_id_pos(ohci, self_id, self_id_count); 1810 if (pos >= 0) { 1811 memmove(&(ohci->self_id_buffer[pos+1]), 1812 &(ohci->self_id_buffer[pos]), 1813 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 1814 ohci->self_id_buffer[pos] = self_id; 1815 self_id_count++; 1816 } 1817 return self_id_count; 1818 } 1819 1820 static void bus_reset_work(struct work_struct *work) 1821 { 1822 struct fw_ohci *ohci = 1823 container_of(work, struct fw_ohci, bus_reset_work); 1824 int self_id_count, generation, new_generation, i, j; 1825 u32 reg; 1826 void *free_rom = NULL; 1827 dma_addr_t free_rom_bus = 0; 1828 bool is_new_root; 1829 1830 reg = reg_read(ohci, OHCI1394_NodeID); 1831 if (!(reg & OHCI1394_NodeID_idValid)) { 1832 dev_notice(ohci->card.device, 1833 "node ID not valid, new bus reset in progress\n"); 1834 return; 1835 } 1836 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1837 dev_notice(ohci->card.device, "malconfigured bus\n"); 1838 return; 1839 } 1840 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1841 OHCI1394_NodeID_nodeNumber); 1842 1843 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1844 if (!(ohci->is_root && is_new_root)) 1845 reg_write(ohci, OHCI1394_LinkControlSet, 1846 OHCI1394_LinkControl_cycleMaster); 1847 ohci->is_root = is_new_root; 1848 1849 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1850 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1851 dev_notice(ohci->card.device, "inconsistent self IDs\n"); 1852 return; 1853 } 1854 /* 1855 * The count in the SelfIDCount register is the number of 1856 * bytes in the self ID receive buffer. Since we also receive 1857 * the inverted quadlets and a header quadlet, we shift one 1858 * bit extra to get the actual number of self IDs. 1859 */ 1860 self_id_count = (reg >> 3) & 0xff; 1861 1862 if (self_id_count > 252) { 1863 dev_notice(ohci->card.device, "inconsistent self IDs\n"); 1864 return; 1865 } 1866 1867 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 1868 rmb(); 1869 1870 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1871 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { 1872 /* 1873 * If the invalid data looks like a cycle start packet, 1874 * it's likely to be the result of the cycle master 1875 * having a wrong gap count. In this case, the self IDs 1876 * so far are valid and should be processed so that the 1877 * bus manager can then correct the gap count. 1878 */ 1879 if (cond_le32_to_cpu(ohci->self_id_cpu[i]) 1880 == 0xffff008f) { 1881 dev_notice(ohci->card.device, 1882 "ignoring spurious self IDs\n"); 1883 self_id_count = j; 1884 break; 1885 } else { 1886 dev_notice(ohci->card.device, 1887 "inconsistent self IDs\n"); 1888 return; 1889 } 1890 } 1891 ohci->self_id_buffer[j] = 1892 cond_le32_to_cpu(ohci->self_id_cpu[i]); 1893 } 1894 1895 if (ohci->quirks & QUIRK_TI_SLLZ059) { 1896 self_id_count = find_and_insert_self_id(ohci, self_id_count); 1897 if (self_id_count < 0) { 1898 dev_notice(ohci->card.device, 1899 "could not construct local self ID\n"); 1900 return; 1901 } 1902 } 1903 1904 if (self_id_count == 0) { 1905 dev_notice(ohci->card.device, "inconsistent self IDs\n"); 1906 return; 1907 } 1908 rmb(); 1909 1910 /* 1911 * Check the consistency of the self IDs we just read. The 1912 * problem we face is that a new bus reset can start while we 1913 * read out the self IDs from the DMA buffer. If this happens, 1914 * the DMA buffer will be overwritten with new self IDs and we 1915 * will read out inconsistent data. The OHCI specification 1916 * (section 11.2) recommends a technique similar to 1917 * linux/seqlock.h, where we remember the generation of the 1918 * self IDs in the buffer before reading them out and compare 1919 * it to the current generation after reading them out. If 1920 * the two generations match we know we have a consistent set 1921 * of self IDs. 1922 */ 1923 1924 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1925 if (new_generation != generation) { 1926 dev_notice(ohci->card.device, 1927 "new bus reset, discarding self ids\n"); 1928 return; 1929 } 1930 1931 /* FIXME: Document how the locking works. */ 1932 spin_lock_irq(&ohci->lock); 1933 1934 ohci->generation = -1; /* prevent AT packet queueing */ 1935 context_stop(&ohci->at_request_ctx); 1936 context_stop(&ohci->at_response_ctx); 1937 1938 spin_unlock_irq(&ohci->lock); 1939 1940 /* 1941 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 1942 * packets in the AT queues and software needs to drain them. 1943 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 1944 */ 1945 at_context_flush(&ohci->at_request_ctx); 1946 at_context_flush(&ohci->at_response_ctx); 1947 1948 spin_lock_irq(&ohci->lock); 1949 1950 ohci->generation = generation; 1951 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 1952 1953 if (ohci->quirks & QUIRK_RESET_PACKET) 1954 ohci->request_generation = generation; 1955 1956 /* 1957 * This next bit is unrelated to the AT context stuff but we 1958 * have to do it under the spinlock also. If a new config rom 1959 * was set up before this reset, the old one is now no longer 1960 * in use and we can free it. Update the config rom pointers 1961 * to point to the current config rom and clear the 1962 * next_config_rom pointer so a new update can take place. 1963 */ 1964 1965 if (ohci->next_config_rom != NULL) { 1966 if (ohci->next_config_rom != ohci->config_rom) { 1967 free_rom = ohci->config_rom; 1968 free_rom_bus = ohci->config_rom_bus; 1969 } 1970 ohci->config_rom = ohci->next_config_rom; 1971 ohci->config_rom_bus = ohci->next_config_rom_bus; 1972 ohci->next_config_rom = NULL; 1973 1974 /* 1975 * Restore config_rom image and manually update 1976 * config_rom registers. Writing the header quadlet 1977 * will indicate that the config rom is ready, so we 1978 * do that last. 1979 */ 1980 reg_write(ohci, OHCI1394_BusOptions, 1981 be32_to_cpu(ohci->config_rom[2])); 1982 ohci->config_rom[0] = ohci->next_header; 1983 reg_write(ohci, OHCI1394_ConfigROMhdr, 1984 be32_to_cpu(ohci->next_header)); 1985 } 1986 1987 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 1988 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 1989 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 1990 #endif 1991 1992 spin_unlock_irq(&ohci->lock); 1993 1994 if (free_rom) 1995 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1996 free_rom, free_rom_bus); 1997 1998 log_selfids(ohci, generation, self_id_count); 1999 2000 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2001 self_id_count, ohci->self_id_buffer, 2002 ohci->csr_state_setclear_abdicate); 2003 ohci->csr_state_setclear_abdicate = false; 2004 } 2005 2006 static irqreturn_t irq_handler(int irq, void *data) 2007 { 2008 struct fw_ohci *ohci = data; 2009 u32 event, iso_event; 2010 int i; 2011 2012 event = reg_read(ohci, OHCI1394_IntEventClear); 2013 2014 if (!event || !~event) 2015 return IRQ_NONE; 2016 2017 /* 2018 * busReset and postedWriteErr must not be cleared yet 2019 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2020 */ 2021 reg_write(ohci, OHCI1394_IntEventClear, 2022 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2023 log_irqs(ohci, event); 2024 2025 if (event & OHCI1394_selfIDComplete) 2026 queue_work(fw_workqueue, &ohci->bus_reset_work); 2027 2028 if (event & OHCI1394_RQPkt) 2029 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2030 2031 if (event & OHCI1394_RSPkt) 2032 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2033 2034 if (event & OHCI1394_reqTxComplete) 2035 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2036 2037 if (event & OHCI1394_respTxComplete) 2038 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2039 2040 if (event & OHCI1394_isochRx) { 2041 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2042 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2043 2044 while (iso_event) { 2045 i = ffs(iso_event) - 1; 2046 tasklet_schedule( 2047 &ohci->ir_context_list[i].context.tasklet); 2048 iso_event &= ~(1 << i); 2049 } 2050 } 2051 2052 if (event & OHCI1394_isochTx) { 2053 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2054 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2055 2056 while (iso_event) { 2057 i = ffs(iso_event) - 1; 2058 tasklet_schedule( 2059 &ohci->it_context_list[i].context.tasklet); 2060 iso_event &= ~(1 << i); 2061 } 2062 } 2063 2064 if (unlikely(event & OHCI1394_regAccessFail)) 2065 dev_err(ohci->card.device, "register access failure\n"); 2066 2067 if (unlikely(event & OHCI1394_postedWriteErr)) { 2068 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2069 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2070 reg_write(ohci, OHCI1394_IntEventClear, 2071 OHCI1394_postedWriteErr); 2072 if (printk_ratelimit()) 2073 dev_err(ohci->card.device, "PCI posted write error\n"); 2074 } 2075 2076 if (unlikely(event & OHCI1394_cycleTooLong)) { 2077 if (printk_ratelimit()) 2078 dev_notice(ohci->card.device, 2079 "isochronous cycle too long\n"); 2080 reg_write(ohci, OHCI1394_LinkControlSet, 2081 OHCI1394_LinkControl_cycleMaster); 2082 } 2083 2084 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2085 /* 2086 * We need to clear this event bit in order to make 2087 * cycleMatch isochronous I/O work. In theory we should 2088 * stop active cycleMatch iso contexts now and restart 2089 * them at least two cycles later. (FIXME?) 2090 */ 2091 if (printk_ratelimit()) 2092 dev_notice(ohci->card.device, 2093 "isochronous cycle inconsistent\n"); 2094 } 2095 2096 if (unlikely(event & OHCI1394_unrecoverableError)) 2097 handle_dead_contexts(ohci); 2098 2099 if (event & OHCI1394_cycle64Seconds) { 2100 spin_lock(&ohci->lock); 2101 update_bus_time(ohci); 2102 spin_unlock(&ohci->lock); 2103 } else 2104 flush_writes(ohci); 2105 2106 return IRQ_HANDLED; 2107 } 2108 2109 static int software_reset(struct fw_ohci *ohci) 2110 { 2111 u32 val; 2112 int i; 2113 2114 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2115 for (i = 0; i < 500; i++) { 2116 val = reg_read(ohci, OHCI1394_HCControlSet); 2117 if (!~val) 2118 return -ENODEV; /* Card was ejected. */ 2119 2120 if (!(val & OHCI1394_HCControl_softReset)) 2121 return 0; 2122 2123 msleep(1); 2124 } 2125 2126 return -EBUSY; 2127 } 2128 2129 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2130 { 2131 size_t size = length * 4; 2132 2133 memcpy(dest, src, size); 2134 if (size < CONFIG_ROM_SIZE) 2135 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2136 } 2137 2138 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2139 { 2140 bool enable_1394a; 2141 int ret, clear, set, offset; 2142 2143 /* Check if the driver should configure link and PHY. */ 2144 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2145 OHCI1394_HCControl_programPhyEnable)) 2146 return 0; 2147 2148 /* Paranoia: check whether the PHY supports 1394a, too. */ 2149 enable_1394a = false; 2150 ret = read_phy_reg(ohci, 2); 2151 if (ret < 0) 2152 return ret; 2153 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2154 ret = read_paged_phy_reg(ohci, 1, 8); 2155 if (ret < 0) 2156 return ret; 2157 if (ret >= 1) 2158 enable_1394a = true; 2159 } 2160 2161 if (ohci->quirks & QUIRK_NO_1394A) 2162 enable_1394a = false; 2163 2164 /* Configure PHY and link consistently. */ 2165 if (enable_1394a) { 2166 clear = 0; 2167 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2168 } else { 2169 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2170 set = 0; 2171 } 2172 ret = update_phy_reg(ohci, 5, clear, set); 2173 if (ret < 0) 2174 return ret; 2175 2176 if (enable_1394a) 2177 offset = OHCI1394_HCControlSet; 2178 else 2179 offset = OHCI1394_HCControlClear; 2180 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2181 2182 /* Clean up: configuration has been taken care of. */ 2183 reg_write(ohci, OHCI1394_HCControlClear, 2184 OHCI1394_HCControl_programPhyEnable); 2185 2186 return 0; 2187 } 2188 2189 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2190 { 2191 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2192 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2193 int reg, i; 2194 2195 reg = read_phy_reg(ohci, 2); 2196 if (reg < 0) 2197 return reg; 2198 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2199 return 0; 2200 2201 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2202 reg = read_paged_phy_reg(ohci, 1, i + 10); 2203 if (reg < 0) 2204 return reg; 2205 if (reg != id[i]) 2206 return 0; 2207 } 2208 return 1; 2209 } 2210 2211 static int ohci_enable(struct fw_card *card, 2212 const __be32 *config_rom, size_t length) 2213 { 2214 struct fw_ohci *ohci = fw_ohci(card); 2215 struct pci_dev *dev = to_pci_dev(card->device); 2216 u32 lps, seconds, version, irqs; 2217 int i, ret; 2218 2219 if (software_reset(ohci)) { 2220 dev_err(card->device, "failed to reset ohci card\n"); 2221 return -EBUSY; 2222 } 2223 2224 /* 2225 * Now enable LPS, which we need in order to start accessing 2226 * most of the registers. In fact, on some cards (ALI M5251), 2227 * accessing registers in the SClk domain without LPS enabled 2228 * will lock up the machine. Wait 50msec to make sure we have 2229 * full link enabled. However, with some cards (well, at least 2230 * a JMicron PCIe card), we have to try again sometimes. 2231 */ 2232 reg_write(ohci, OHCI1394_HCControlSet, 2233 OHCI1394_HCControl_LPS | 2234 OHCI1394_HCControl_postedWriteEnable); 2235 flush_writes(ohci); 2236 2237 for (lps = 0, i = 0; !lps && i < 3; i++) { 2238 msleep(50); 2239 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2240 OHCI1394_HCControl_LPS; 2241 } 2242 2243 if (!lps) { 2244 dev_err(card->device, "failed to set Link Power Status\n"); 2245 return -EIO; 2246 } 2247 2248 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2249 ret = probe_tsb41ba3d(ohci); 2250 if (ret < 0) 2251 return ret; 2252 if (ret) 2253 dev_notice(card->device, "local TSB41BA3D phy\n"); 2254 else 2255 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2256 } 2257 2258 reg_write(ohci, OHCI1394_HCControlClear, 2259 OHCI1394_HCControl_noByteSwapData); 2260 2261 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2262 reg_write(ohci, OHCI1394_LinkControlSet, 2263 OHCI1394_LinkControl_cycleTimerEnable | 2264 OHCI1394_LinkControl_cycleMaster); 2265 2266 reg_write(ohci, OHCI1394_ATRetries, 2267 OHCI1394_MAX_AT_REQ_RETRIES | 2268 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2269 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2270 (200 << 16)); 2271 2272 seconds = lower_32_bits(get_seconds()); 2273 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 2274 ohci->bus_time = seconds & ~0x3f; 2275 2276 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2277 if (version >= OHCI_VERSION_1_1) { 2278 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2279 0xfffffffe); 2280 card->broadcast_channel_auto_allocated = true; 2281 } 2282 2283 /* Get implemented bits of the priority arbitration request counter. */ 2284 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2285 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2286 reg_write(ohci, OHCI1394_FairnessControl, 0); 2287 card->priority_budget_implemented = ohci->pri_req_max != 0; 2288 2289 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 2290 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2291 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2292 2293 ret = configure_1394a_enhancements(ohci); 2294 if (ret < 0) 2295 return ret; 2296 2297 /* Activate link_on bit and contender bit in our self ID packets.*/ 2298 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2299 if (ret < 0) 2300 return ret; 2301 2302 /* 2303 * When the link is not yet enabled, the atomic config rom 2304 * update mechanism described below in ohci_set_config_rom() 2305 * is not active. We have to update ConfigRomHeader and 2306 * BusOptions manually, and the write to ConfigROMmap takes 2307 * effect immediately. We tie this to the enabling of the 2308 * link, so we have a valid config rom before enabling - the 2309 * OHCI requires that ConfigROMhdr and BusOptions have valid 2310 * values before enabling. 2311 * 2312 * However, when the ConfigROMmap is written, some controllers 2313 * always read back quadlets 0 and 2 from the config rom to 2314 * the ConfigRomHeader and BusOptions registers on bus reset. 2315 * They shouldn't do that in this initial case where the link 2316 * isn't enabled. This means we have to use the same 2317 * workaround here, setting the bus header to 0 and then write 2318 * the right values in the bus reset tasklet. 2319 */ 2320 2321 if (config_rom) { 2322 ohci->next_config_rom = 2323 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2324 &ohci->next_config_rom_bus, 2325 GFP_KERNEL); 2326 if (ohci->next_config_rom == NULL) 2327 return -ENOMEM; 2328 2329 copy_config_rom(ohci->next_config_rom, config_rom, length); 2330 } else { 2331 /* 2332 * In the suspend case, config_rom is NULL, which 2333 * means that we just reuse the old config rom. 2334 */ 2335 ohci->next_config_rom = ohci->config_rom; 2336 ohci->next_config_rom_bus = ohci->config_rom_bus; 2337 } 2338 2339 ohci->next_header = ohci->next_config_rom[0]; 2340 ohci->next_config_rom[0] = 0; 2341 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2342 reg_write(ohci, OHCI1394_BusOptions, 2343 be32_to_cpu(ohci->next_config_rom[2])); 2344 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2345 2346 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2347 2348 if (!(ohci->quirks & QUIRK_NO_MSI)) 2349 pci_enable_msi(dev); 2350 if (request_irq(dev->irq, irq_handler, 2351 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 2352 ohci_driver_name, ohci)) { 2353 dev_err(card->device, "failed to allocate interrupt %d\n", 2354 dev->irq); 2355 pci_disable_msi(dev); 2356 2357 if (config_rom) { 2358 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2359 ohci->next_config_rom, 2360 ohci->next_config_rom_bus); 2361 ohci->next_config_rom = NULL; 2362 } 2363 return -EIO; 2364 } 2365 2366 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2367 OHCI1394_RQPkt | OHCI1394_RSPkt | 2368 OHCI1394_isochTx | OHCI1394_isochRx | 2369 OHCI1394_postedWriteErr | 2370 OHCI1394_selfIDComplete | 2371 OHCI1394_regAccessFail | 2372 OHCI1394_cycle64Seconds | 2373 OHCI1394_cycleInconsistent | 2374 OHCI1394_unrecoverableError | 2375 OHCI1394_cycleTooLong | 2376 OHCI1394_masterIntEnable; 2377 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2378 irqs |= OHCI1394_busReset; 2379 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2380 2381 reg_write(ohci, OHCI1394_HCControlSet, 2382 OHCI1394_HCControl_linkEnable | 2383 OHCI1394_HCControl_BIBimageValid); 2384 2385 reg_write(ohci, OHCI1394_LinkControlSet, 2386 OHCI1394_LinkControl_rcvSelfID | 2387 OHCI1394_LinkControl_rcvPhyPkt); 2388 2389 ar_context_run(&ohci->ar_request_ctx); 2390 ar_context_run(&ohci->ar_response_ctx); 2391 2392 flush_writes(ohci); 2393 2394 /* We are ready to go, reset bus to finish initialization. */ 2395 fw_schedule_bus_reset(&ohci->card, false, true); 2396 2397 return 0; 2398 } 2399 2400 static int ohci_set_config_rom(struct fw_card *card, 2401 const __be32 *config_rom, size_t length) 2402 { 2403 struct fw_ohci *ohci; 2404 __be32 *next_config_rom; 2405 dma_addr_t uninitialized_var(next_config_rom_bus); 2406 2407 ohci = fw_ohci(card); 2408 2409 /* 2410 * When the OHCI controller is enabled, the config rom update 2411 * mechanism is a bit tricky, but easy enough to use. See 2412 * section 5.5.6 in the OHCI specification. 2413 * 2414 * The OHCI controller caches the new config rom address in a 2415 * shadow register (ConfigROMmapNext) and needs a bus reset 2416 * for the changes to take place. When the bus reset is 2417 * detected, the controller loads the new values for the 2418 * ConfigRomHeader and BusOptions registers from the specified 2419 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2420 * shadow register. All automatically and atomically. 2421 * 2422 * Now, there's a twist to this story. The automatic load of 2423 * ConfigRomHeader and BusOptions doesn't honor the 2424 * noByteSwapData bit, so with a be32 config rom, the 2425 * controller will load be32 values in to these registers 2426 * during the atomic update, even on litte endian 2427 * architectures. The workaround we use is to put a 0 in the 2428 * header quadlet; 0 is endian agnostic and means that the 2429 * config rom isn't ready yet. In the bus reset tasklet we 2430 * then set up the real values for the two registers. 2431 * 2432 * We use ohci->lock to avoid racing with the code that sets 2433 * ohci->next_config_rom to NULL (see bus_reset_work). 2434 */ 2435 2436 next_config_rom = 2437 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2438 &next_config_rom_bus, GFP_KERNEL); 2439 if (next_config_rom == NULL) 2440 return -ENOMEM; 2441 2442 spin_lock_irq(&ohci->lock); 2443 2444 /* 2445 * If there is not an already pending config_rom update, 2446 * push our new allocation into the ohci->next_config_rom 2447 * and then mark the local variable as null so that we 2448 * won't deallocate the new buffer. 2449 * 2450 * OTOH, if there is a pending config_rom update, just 2451 * use that buffer with the new config_rom data, and 2452 * let this routine free the unused DMA allocation. 2453 */ 2454 2455 if (ohci->next_config_rom == NULL) { 2456 ohci->next_config_rom = next_config_rom; 2457 ohci->next_config_rom_bus = next_config_rom_bus; 2458 next_config_rom = NULL; 2459 } 2460 2461 copy_config_rom(ohci->next_config_rom, config_rom, length); 2462 2463 ohci->next_header = config_rom[0]; 2464 ohci->next_config_rom[0] = 0; 2465 2466 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2467 2468 spin_unlock_irq(&ohci->lock); 2469 2470 /* If we didn't use the DMA allocation, delete it. */ 2471 if (next_config_rom != NULL) 2472 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2473 next_config_rom, next_config_rom_bus); 2474 2475 /* 2476 * Now initiate a bus reset to have the changes take 2477 * effect. We clean up the old config rom memory and DMA 2478 * mappings in the bus reset tasklet, since the OHCI 2479 * controller could need to access it before the bus reset 2480 * takes effect. 2481 */ 2482 2483 fw_schedule_bus_reset(&ohci->card, true, true); 2484 2485 return 0; 2486 } 2487 2488 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2489 { 2490 struct fw_ohci *ohci = fw_ohci(card); 2491 2492 at_context_transmit(&ohci->at_request_ctx, packet); 2493 } 2494 2495 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2496 { 2497 struct fw_ohci *ohci = fw_ohci(card); 2498 2499 at_context_transmit(&ohci->at_response_ctx, packet); 2500 } 2501 2502 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2503 { 2504 struct fw_ohci *ohci = fw_ohci(card); 2505 struct context *ctx = &ohci->at_request_ctx; 2506 struct driver_data *driver_data = packet->driver_data; 2507 int ret = -ENOENT; 2508 2509 tasklet_disable(&ctx->tasklet); 2510 2511 if (packet->ack != 0) 2512 goto out; 2513 2514 if (packet->payload_mapped) 2515 dma_unmap_single(ohci->card.device, packet->payload_bus, 2516 packet->payload_length, DMA_TO_DEVICE); 2517 2518 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2519 driver_data->packet = NULL; 2520 packet->ack = RCODE_CANCELLED; 2521 packet->callback(packet, &ohci->card, packet->ack); 2522 ret = 0; 2523 out: 2524 tasklet_enable(&ctx->tasklet); 2525 2526 return ret; 2527 } 2528 2529 static int ohci_enable_phys_dma(struct fw_card *card, 2530 int node_id, int generation) 2531 { 2532 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2533 return 0; 2534 #else 2535 struct fw_ohci *ohci = fw_ohci(card); 2536 unsigned long flags; 2537 int n, ret = 0; 2538 2539 /* 2540 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2541 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2542 */ 2543 2544 spin_lock_irqsave(&ohci->lock, flags); 2545 2546 if (ohci->generation != generation) { 2547 ret = -ESTALE; 2548 goto out; 2549 } 2550 2551 /* 2552 * Note, if the node ID contains a non-local bus ID, physical DMA is 2553 * enabled for _all_ nodes on remote buses. 2554 */ 2555 2556 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2557 if (n < 32) 2558 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2559 else 2560 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2561 2562 flush_writes(ohci); 2563 out: 2564 spin_unlock_irqrestore(&ohci->lock, flags); 2565 2566 return ret; 2567 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2568 } 2569 2570 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2571 { 2572 struct fw_ohci *ohci = fw_ohci(card); 2573 unsigned long flags; 2574 u32 value; 2575 2576 switch (csr_offset) { 2577 case CSR_STATE_CLEAR: 2578 case CSR_STATE_SET: 2579 if (ohci->is_root && 2580 (reg_read(ohci, OHCI1394_LinkControlSet) & 2581 OHCI1394_LinkControl_cycleMaster)) 2582 value = CSR_STATE_BIT_CMSTR; 2583 else 2584 value = 0; 2585 if (ohci->csr_state_setclear_abdicate) 2586 value |= CSR_STATE_BIT_ABDICATE; 2587 2588 return value; 2589 2590 case CSR_NODE_IDS: 2591 return reg_read(ohci, OHCI1394_NodeID) << 16; 2592 2593 case CSR_CYCLE_TIME: 2594 return get_cycle_time(ohci); 2595 2596 case CSR_BUS_TIME: 2597 /* 2598 * We might be called just after the cycle timer has wrapped 2599 * around but just before the cycle64Seconds handler, so we 2600 * better check here, too, if the bus time needs to be updated. 2601 */ 2602 spin_lock_irqsave(&ohci->lock, flags); 2603 value = update_bus_time(ohci); 2604 spin_unlock_irqrestore(&ohci->lock, flags); 2605 return value; 2606 2607 case CSR_BUSY_TIMEOUT: 2608 value = reg_read(ohci, OHCI1394_ATRetries); 2609 return (value >> 4) & 0x0ffff00f; 2610 2611 case CSR_PRIORITY_BUDGET: 2612 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2613 (ohci->pri_req_max << 8); 2614 2615 default: 2616 WARN_ON(1); 2617 return 0; 2618 } 2619 } 2620 2621 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2622 { 2623 struct fw_ohci *ohci = fw_ohci(card); 2624 unsigned long flags; 2625 2626 switch (csr_offset) { 2627 case CSR_STATE_CLEAR: 2628 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2629 reg_write(ohci, OHCI1394_LinkControlClear, 2630 OHCI1394_LinkControl_cycleMaster); 2631 flush_writes(ohci); 2632 } 2633 if (value & CSR_STATE_BIT_ABDICATE) 2634 ohci->csr_state_setclear_abdicate = false; 2635 break; 2636 2637 case CSR_STATE_SET: 2638 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2639 reg_write(ohci, OHCI1394_LinkControlSet, 2640 OHCI1394_LinkControl_cycleMaster); 2641 flush_writes(ohci); 2642 } 2643 if (value & CSR_STATE_BIT_ABDICATE) 2644 ohci->csr_state_setclear_abdicate = true; 2645 break; 2646 2647 case CSR_NODE_IDS: 2648 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2649 flush_writes(ohci); 2650 break; 2651 2652 case CSR_CYCLE_TIME: 2653 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2654 reg_write(ohci, OHCI1394_IntEventSet, 2655 OHCI1394_cycleInconsistent); 2656 flush_writes(ohci); 2657 break; 2658 2659 case CSR_BUS_TIME: 2660 spin_lock_irqsave(&ohci->lock, flags); 2661 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); 2662 spin_unlock_irqrestore(&ohci->lock, flags); 2663 break; 2664 2665 case CSR_BUSY_TIMEOUT: 2666 value = (value & 0xf) | ((value & 0xf) << 4) | 2667 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2668 reg_write(ohci, OHCI1394_ATRetries, value); 2669 flush_writes(ohci); 2670 break; 2671 2672 case CSR_PRIORITY_BUDGET: 2673 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2674 flush_writes(ohci); 2675 break; 2676 2677 default: 2678 WARN_ON(1); 2679 break; 2680 } 2681 } 2682 2683 static void flush_iso_completions(struct iso_context *ctx) 2684 { 2685 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2686 ctx->header_length, ctx->header, 2687 ctx->base.callback_data); 2688 ctx->header_length = 0; 2689 } 2690 2691 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2692 { 2693 u32 *ctx_hdr; 2694 2695 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) 2696 flush_iso_completions(ctx); 2697 2698 ctx_hdr = ctx->header + ctx->header_length; 2699 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2700 2701 /* 2702 * The two iso header quadlets are byteswapped to little 2703 * endian by the controller, but we want to present them 2704 * as big endian for consistency with the bus endianness. 2705 */ 2706 if (ctx->base.header_size > 0) 2707 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2708 if (ctx->base.header_size > 4) 2709 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2710 if (ctx->base.header_size > 8) 2711 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2712 ctx->header_length += ctx->base.header_size; 2713 } 2714 2715 static int handle_ir_packet_per_buffer(struct context *context, 2716 struct descriptor *d, 2717 struct descriptor *last) 2718 { 2719 struct iso_context *ctx = 2720 container_of(context, struct iso_context, context); 2721 struct descriptor *pd; 2722 u32 buffer_dma; 2723 2724 for (pd = d; pd <= last; pd++) 2725 if (pd->transfer_status) 2726 break; 2727 if (pd > last) 2728 /* Descriptor(s) not done yet, stop iteration */ 2729 return 0; 2730 2731 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2732 d++; 2733 buffer_dma = le32_to_cpu(d->data_address); 2734 dma_sync_single_range_for_cpu(context->ohci->card.device, 2735 buffer_dma & PAGE_MASK, 2736 buffer_dma & ~PAGE_MASK, 2737 le16_to_cpu(d->req_count), 2738 DMA_FROM_DEVICE); 2739 } 2740 2741 copy_iso_headers(ctx, (u32 *) (last + 1)); 2742 2743 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2744 flush_iso_completions(ctx); 2745 2746 return 1; 2747 } 2748 2749 /* d == last because each descriptor block is only a single descriptor. */ 2750 static int handle_ir_buffer_fill(struct context *context, 2751 struct descriptor *d, 2752 struct descriptor *last) 2753 { 2754 struct iso_context *ctx = 2755 container_of(context, struct iso_context, context); 2756 unsigned int req_count, res_count, completed; 2757 u32 buffer_dma; 2758 2759 req_count = le16_to_cpu(last->req_count); 2760 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count)); 2761 completed = req_count - res_count; 2762 buffer_dma = le32_to_cpu(last->data_address); 2763 2764 if (completed > 0) { 2765 ctx->mc_buffer_bus = buffer_dma; 2766 ctx->mc_completed = completed; 2767 } 2768 2769 if (res_count != 0) 2770 /* Descriptor(s) not done yet, stop iteration */ 2771 return 0; 2772 2773 dma_sync_single_range_for_cpu(context->ohci->card.device, 2774 buffer_dma & PAGE_MASK, 2775 buffer_dma & ~PAGE_MASK, 2776 completed, DMA_FROM_DEVICE); 2777 2778 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2779 ctx->base.callback.mc(&ctx->base, 2780 buffer_dma + completed, 2781 ctx->base.callback_data); 2782 ctx->mc_completed = 0; 2783 } 2784 2785 return 1; 2786 } 2787 2788 static void flush_ir_buffer_fill(struct iso_context *ctx) 2789 { 2790 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2791 ctx->mc_buffer_bus & PAGE_MASK, 2792 ctx->mc_buffer_bus & ~PAGE_MASK, 2793 ctx->mc_completed, DMA_FROM_DEVICE); 2794 2795 ctx->base.callback.mc(&ctx->base, 2796 ctx->mc_buffer_bus + ctx->mc_completed, 2797 ctx->base.callback_data); 2798 ctx->mc_completed = 0; 2799 } 2800 2801 static inline void sync_it_packet_for_cpu(struct context *context, 2802 struct descriptor *pd) 2803 { 2804 __le16 control; 2805 u32 buffer_dma; 2806 2807 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2808 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2809 return; 2810 2811 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2812 pd += 2; 2813 2814 /* 2815 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2816 * data buffer is in the context program's coherent page and must not 2817 * be synced. 2818 */ 2819 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2820 (context->current_bus & PAGE_MASK)) { 2821 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2822 return; 2823 pd++; 2824 } 2825 2826 do { 2827 buffer_dma = le32_to_cpu(pd->data_address); 2828 dma_sync_single_range_for_cpu(context->ohci->card.device, 2829 buffer_dma & PAGE_MASK, 2830 buffer_dma & ~PAGE_MASK, 2831 le16_to_cpu(pd->req_count), 2832 DMA_TO_DEVICE); 2833 control = pd->control; 2834 pd++; 2835 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 2836 } 2837 2838 static int handle_it_packet(struct context *context, 2839 struct descriptor *d, 2840 struct descriptor *last) 2841 { 2842 struct iso_context *ctx = 2843 container_of(context, struct iso_context, context); 2844 struct descriptor *pd; 2845 __be32 *ctx_hdr; 2846 2847 for (pd = d; pd <= last; pd++) 2848 if (pd->transfer_status) 2849 break; 2850 if (pd > last) 2851 /* Descriptor(s) not done yet, stop iteration */ 2852 return 0; 2853 2854 sync_it_packet_for_cpu(context, d); 2855 2856 if (ctx->header_length + 4 > PAGE_SIZE) 2857 flush_iso_completions(ctx); 2858 2859 ctx_hdr = ctx->header + ctx->header_length; 2860 ctx->last_timestamp = le16_to_cpu(last->res_count); 2861 /* Present this value as big-endian to match the receive code */ 2862 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 2863 le16_to_cpu(pd->res_count)); 2864 ctx->header_length += 4; 2865 2866 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2867 flush_iso_completions(ctx); 2868 2869 return 1; 2870 } 2871 2872 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2873 { 2874 u32 hi = channels >> 32, lo = channels; 2875 2876 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2877 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2878 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2879 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2880 mmiowb(); 2881 ohci->mc_channels = channels; 2882 } 2883 2884 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2885 int type, int channel, size_t header_size) 2886 { 2887 struct fw_ohci *ohci = fw_ohci(card); 2888 struct iso_context *uninitialized_var(ctx); 2889 descriptor_callback_t uninitialized_var(callback); 2890 u64 *uninitialized_var(channels); 2891 u32 *uninitialized_var(mask), uninitialized_var(regs); 2892 int index, ret = -EBUSY; 2893 2894 spin_lock_irq(&ohci->lock); 2895 2896 switch (type) { 2897 case FW_ISO_CONTEXT_TRANSMIT: 2898 mask = &ohci->it_context_mask; 2899 callback = handle_it_packet; 2900 index = ffs(*mask) - 1; 2901 if (index >= 0) { 2902 *mask &= ~(1 << index); 2903 regs = OHCI1394_IsoXmitContextBase(index); 2904 ctx = &ohci->it_context_list[index]; 2905 } 2906 break; 2907 2908 case FW_ISO_CONTEXT_RECEIVE: 2909 channels = &ohci->ir_context_channels; 2910 mask = &ohci->ir_context_mask; 2911 callback = handle_ir_packet_per_buffer; 2912 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2913 if (index >= 0) { 2914 *channels &= ~(1ULL << channel); 2915 *mask &= ~(1 << index); 2916 regs = OHCI1394_IsoRcvContextBase(index); 2917 ctx = &ohci->ir_context_list[index]; 2918 } 2919 break; 2920 2921 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2922 mask = &ohci->ir_context_mask; 2923 callback = handle_ir_buffer_fill; 2924 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2925 if (index >= 0) { 2926 ohci->mc_allocated = true; 2927 *mask &= ~(1 << index); 2928 regs = OHCI1394_IsoRcvContextBase(index); 2929 ctx = &ohci->ir_context_list[index]; 2930 } 2931 break; 2932 2933 default: 2934 index = -1; 2935 ret = -ENOSYS; 2936 } 2937 2938 spin_unlock_irq(&ohci->lock); 2939 2940 if (index < 0) 2941 return ERR_PTR(ret); 2942 2943 memset(ctx, 0, sizeof(*ctx)); 2944 ctx->header_length = 0; 2945 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2946 if (ctx->header == NULL) { 2947 ret = -ENOMEM; 2948 goto out; 2949 } 2950 ret = context_init(&ctx->context, ohci, regs, callback); 2951 if (ret < 0) 2952 goto out_with_header; 2953 2954 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 2955 set_multichannel_mask(ohci, 0); 2956 ctx->mc_completed = 0; 2957 } 2958 2959 return &ctx->base; 2960 2961 out_with_header: 2962 free_page((unsigned long)ctx->header); 2963 out: 2964 spin_lock_irq(&ohci->lock); 2965 2966 switch (type) { 2967 case FW_ISO_CONTEXT_RECEIVE: 2968 *channels |= 1ULL << channel; 2969 break; 2970 2971 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2972 ohci->mc_allocated = false; 2973 break; 2974 } 2975 *mask |= 1 << index; 2976 2977 spin_unlock_irq(&ohci->lock); 2978 2979 return ERR_PTR(ret); 2980 } 2981 2982 static int ohci_start_iso(struct fw_iso_context *base, 2983 s32 cycle, u32 sync, u32 tags) 2984 { 2985 struct iso_context *ctx = container_of(base, struct iso_context, base); 2986 struct fw_ohci *ohci = ctx->context.ohci; 2987 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 2988 int index; 2989 2990 /* the controller cannot start without any queued packets */ 2991 if (ctx->context.last->branch_address == 0) 2992 return -ENODATA; 2993 2994 switch (ctx->base.type) { 2995 case FW_ISO_CONTEXT_TRANSMIT: 2996 index = ctx - ohci->it_context_list; 2997 match = 0; 2998 if (cycle >= 0) 2999 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3000 (cycle & 0x7fff) << 16; 3001 3002 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3003 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3004 context_run(&ctx->context, match); 3005 break; 3006 3007 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3008 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3009 /* fall through */ 3010 case FW_ISO_CONTEXT_RECEIVE: 3011 index = ctx - ohci->ir_context_list; 3012 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3013 if (cycle >= 0) { 3014 match |= (cycle & 0x07fff) << 12; 3015 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3016 } 3017 3018 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3019 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3020 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3021 context_run(&ctx->context, control); 3022 3023 ctx->sync = sync; 3024 ctx->tags = tags; 3025 3026 break; 3027 } 3028 3029 return 0; 3030 } 3031 3032 static int ohci_stop_iso(struct fw_iso_context *base) 3033 { 3034 struct fw_ohci *ohci = fw_ohci(base->card); 3035 struct iso_context *ctx = container_of(base, struct iso_context, base); 3036 int index; 3037 3038 switch (ctx->base.type) { 3039 case FW_ISO_CONTEXT_TRANSMIT: 3040 index = ctx - ohci->it_context_list; 3041 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3042 break; 3043 3044 case FW_ISO_CONTEXT_RECEIVE: 3045 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3046 index = ctx - ohci->ir_context_list; 3047 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3048 break; 3049 } 3050 flush_writes(ohci); 3051 context_stop(&ctx->context); 3052 tasklet_kill(&ctx->context.tasklet); 3053 3054 return 0; 3055 } 3056 3057 static void ohci_free_iso_context(struct fw_iso_context *base) 3058 { 3059 struct fw_ohci *ohci = fw_ohci(base->card); 3060 struct iso_context *ctx = container_of(base, struct iso_context, base); 3061 unsigned long flags; 3062 int index; 3063 3064 ohci_stop_iso(base); 3065 context_release(&ctx->context); 3066 free_page((unsigned long)ctx->header); 3067 3068 spin_lock_irqsave(&ohci->lock, flags); 3069 3070 switch (base->type) { 3071 case FW_ISO_CONTEXT_TRANSMIT: 3072 index = ctx - ohci->it_context_list; 3073 ohci->it_context_mask |= 1 << index; 3074 break; 3075 3076 case FW_ISO_CONTEXT_RECEIVE: 3077 index = ctx - ohci->ir_context_list; 3078 ohci->ir_context_mask |= 1 << index; 3079 ohci->ir_context_channels |= 1ULL << base->channel; 3080 break; 3081 3082 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3083 index = ctx - ohci->ir_context_list; 3084 ohci->ir_context_mask |= 1 << index; 3085 ohci->ir_context_channels |= ohci->mc_channels; 3086 ohci->mc_channels = 0; 3087 ohci->mc_allocated = false; 3088 break; 3089 } 3090 3091 spin_unlock_irqrestore(&ohci->lock, flags); 3092 } 3093 3094 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3095 { 3096 struct fw_ohci *ohci = fw_ohci(base->card); 3097 unsigned long flags; 3098 int ret; 3099 3100 switch (base->type) { 3101 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3102 3103 spin_lock_irqsave(&ohci->lock, flags); 3104 3105 /* Don't allow multichannel to grab other contexts' channels. */ 3106 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3107 *channels = ohci->ir_context_channels; 3108 ret = -EBUSY; 3109 } else { 3110 set_multichannel_mask(ohci, *channels); 3111 ret = 0; 3112 } 3113 3114 spin_unlock_irqrestore(&ohci->lock, flags); 3115 3116 break; 3117 default: 3118 ret = -EINVAL; 3119 } 3120 3121 return ret; 3122 } 3123 3124 #ifdef CONFIG_PM 3125 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3126 { 3127 int i; 3128 struct iso_context *ctx; 3129 3130 for (i = 0 ; i < ohci->n_ir ; i++) { 3131 ctx = &ohci->ir_context_list[i]; 3132 if (ctx->context.running) 3133 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3134 } 3135 3136 for (i = 0 ; i < ohci->n_it ; i++) { 3137 ctx = &ohci->it_context_list[i]; 3138 if (ctx->context.running) 3139 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3140 } 3141 } 3142 #endif 3143 3144 static int queue_iso_transmit(struct iso_context *ctx, 3145 struct fw_iso_packet *packet, 3146 struct fw_iso_buffer *buffer, 3147 unsigned long payload) 3148 { 3149 struct descriptor *d, *last, *pd; 3150 struct fw_iso_packet *p; 3151 __le32 *header; 3152 dma_addr_t d_bus, page_bus; 3153 u32 z, header_z, payload_z, irq; 3154 u32 payload_index, payload_end_index, next_page_index; 3155 int page, end_page, i, length, offset; 3156 3157 p = packet; 3158 payload_index = payload; 3159 3160 if (p->skip) 3161 z = 1; 3162 else 3163 z = 2; 3164 if (p->header_length > 0) 3165 z++; 3166 3167 /* Determine the first page the payload isn't contained in. */ 3168 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3169 if (p->payload_length > 0) 3170 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3171 else 3172 payload_z = 0; 3173 3174 z += payload_z; 3175 3176 /* Get header size in number of descriptors. */ 3177 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3178 3179 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3180 if (d == NULL) 3181 return -ENOMEM; 3182 3183 if (!p->skip) { 3184 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3185 d[0].req_count = cpu_to_le16(8); 3186 /* 3187 * Link the skip address to this descriptor itself. This causes 3188 * a context to skip a cycle whenever lost cycles or FIFO 3189 * overruns occur, without dropping the data. The application 3190 * should then decide whether this is an error condition or not. 3191 * FIXME: Make the context's cycle-lost behaviour configurable? 3192 */ 3193 d[0].branch_address = cpu_to_le32(d_bus | z); 3194 3195 header = (__le32 *) &d[1]; 3196 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3197 IT_HEADER_TAG(p->tag) | 3198 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3199 IT_HEADER_CHANNEL(ctx->base.channel) | 3200 IT_HEADER_SPEED(ctx->base.speed)); 3201 header[1] = 3202 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3203 p->payload_length)); 3204 } 3205 3206 if (p->header_length > 0) { 3207 d[2].req_count = cpu_to_le16(p->header_length); 3208 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3209 memcpy(&d[z], p->header, p->header_length); 3210 } 3211 3212 pd = d + z - payload_z; 3213 payload_end_index = payload_index + p->payload_length; 3214 for (i = 0; i < payload_z; i++) { 3215 page = payload_index >> PAGE_SHIFT; 3216 offset = payload_index & ~PAGE_MASK; 3217 next_page_index = (page + 1) << PAGE_SHIFT; 3218 length = 3219 min(next_page_index, payload_end_index) - payload_index; 3220 pd[i].req_count = cpu_to_le16(length); 3221 3222 page_bus = page_private(buffer->pages[page]); 3223 pd[i].data_address = cpu_to_le32(page_bus + offset); 3224 3225 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3226 page_bus, offset, length, 3227 DMA_TO_DEVICE); 3228 3229 payload_index += length; 3230 } 3231 3232 if (p->interrupt) 3233 irq = DESCRIPTOR_IRQ_ALWAYS; 3234 else 3235 irq = DESCRIPTOR_NO_IRQ; 3236 3237 last = z == 2 ? d : d + z - 1; 3238 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3239 DESCRIPTOR_STATUS | 3240 DESCRIPTOR_BRANCH_ALWAYS | 3241 irq); 3242 3243 context_append(&ctx->context, d, z, header_z); 3244 3245 return 0; 3246 } 3247 3248 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3249 struct fw_iso_packet *packet, 3250 struct fw_iso_buffer *buffer, 3251 unsigned long payload) 3252 { 3253 struct device *device = ctx->context.ohci->card.device; 3254 struct descriptor *d, *pd; 3255 dma_addr_t d_bus, page_bus; 3256 u32 z, header_z, rest; 3257 int i, j, length; 3258 int page, offset, packet_count, header_size, payload_per_buffer; 3259 3260 /* 3261 * The OHCI controller puts the isochronous header and trailer in the 3262 * buffer, so we need at least 8 bytes. 3263 */ 3264 packet_count = packet->header_length / ctx->base.header_size; 3265 header_size = max(ctx->base.header_size, (size_t)8); 3266 3267 /* Get header size in number of descriptors. */ 3268 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3269 page = payload >> PAGE_SHIFT; 3270 offset = payload & ~PAGE_MASK; 3271 payload_per_buffer = packet->payload_length / packet_count; 3272 3273 for (i = 0; i < packet_count; i++) { 3274 /* d points to the header descriptor */ 3275 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3276 d = context_get_descriptors(&ctx->context, 3277 z + header_z, &d_bus); 3278 if (d == NULL) 3279 return -ENOMEM; 3280 3281 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3282 DESCRIPTOR_INPUT_MORE); 3283 if (packet->skip && i == 0) 3284 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3285 d->req_count = cpu_to_le16(header_size); 3286 d->res_count = d->req_count; 3287 d->transfer_status = 0; 3288 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3289 3290 rest = payload_per_buffer; 3291 pd = d; 3292 for (j = 1; j < z; j++) { 3293 pd++; 3294 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3295 DESCRIPTOR_INPUT_MORE); 3296 3297 if (offset + rest < PAGE_SIZE) 3298 length = rest; 3299 else 3300 length = PAGE_SIZE - offset; 3301 pd->req_count = cpu_to_le16(length); 3302 pd->res_count = pd->req_count; 3303 pd->transfer_status = 0; 3304 3305 page_bus = page_private(buffer->pages[page]); 3306 pd->data_address = cpu_to_le32(page_bus + offset); 3307 3308 dma_sync_single_range_for_device(device, page_bus, 3309 offset, length, 3310 DMA_FROM_DEVICE); 3311 3312 offset = (offset + length) & ~PAGE_MASK; 3313 rest -= length; 3314 if (offset == 0) 3315 page++; 3316 } 3317 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3318 DESCRIPTOR_INPUT_LAST | 3319 DESCRIPTOR_BRANCH_ALWAYS); 3320 if (packet->interrupt && i == packet_count - 1) 3321 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3322 3323 context_append(&ctx->context, d, z, header_z); 3324 } 3325 3326 return 0; 3327 } 3328 3329 static int queue_iso_buffer_fill(struct iso_context *ctx, 3330 struct fw_iso_packet *packet, 3331 struct fw_iso_buffer *buffer, 3332 unsigned long payload) 3333 { 3334 struct descriptor *d; 3335 dma_addr_t d_bus, page_bus; 3336 int page, offset, rest, z, i, length; 3337 3338 page = payload >> PAGE_SHIFT; 3339 offset = payload & ~PAGE_MASK; 3340 rest = packet->payload_length; 3341 3342 /* We need one descriptor for each page in the buffer. */ 3343 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3344 3345 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3346 return -EFAULT; 3347 3348 for (i = 0; i < z; i++) { 3349 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3350 if (d == NULL) 3351 return -ENOMEM; 3352 3353 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3354 DESCRIPTOR_BRANCH_ALWAYS); 3355 if (packet->skip && i == 0) 3356 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3357 if (packet->interrupt && i == z - 1) 3358 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3359 3360 if (offset + rest < PAGE_SIZE) 3361 length = rest; 3362 else 3363 length = PAGE_SIZE - offset; 3364 d->req_count = cpu_to_le16(length); 3365 d->res_count = d->req_count; 3366 d->transfer_status = 0; 3367 3368 page_bus = page_private(buffer->pages[page]); 3369 d->data_address = cpu_to_le32(page_bus + offset); 3370 3371 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3372 page_bus, offset, length, 3373 DMA_FROM_DEVICE); 3374 3375 rest -= length; 3376 offset = 0; 3377 page++; 3378 3379 context_append(&ctx->context, d, 1, 0); 3380 } 3381 3382 return 0; 3383 } 3384 3385 static int ohci_queue_iso(struct fw_iso_context *base, 3386 struct fw_iso_packet *packet, 3387 struct fw_iso_buffer *buffer, 3388 unsigned long payload) 3389 { 3390 struct iso_context *ctx = container_of(base, struct iso_context, base); 3391 unsigned long flags; 3392 int ret = -ENOSYS; 3393 3394 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3395 switch (base->type) { 3396 case FW_ISO_CONTEXT_TRANSMIT: 3397 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3398 break; 3399 case FW_ISO_CONTEXT_RECEIVE: 3400 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3401 break; 3402 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3403 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3404 break; 3405 } 3406 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3407 3408 return ret; 3409 } 3410 3411 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3412 { 3413 struct context *ctx = 3414 &container_of(base, struct iso_context, base)->context; 3415 3416 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3417 } 3418 3419 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3420 { 3421 struct iso_context *ctx = container_of(base, struct iso_context, base); 3422 int ret = 0; 3423 3424 tasklet_disable(&ctx->context.tasklet); 3425 3426 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3427 context_tasklet((unsigned long)&ctx->context); 3428 3429 switch (base->type) { 3430 case FW_ISO_CONTEXT_TRANSMIT: 3431 case FW_ISO_CONTEXT_RECEIVE: 3432 if (ctx->header_length != 0) 3433 flush_iso_completions(ctx); 3434 break; 3435 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3436 if (ctx->mc_completed != 0) 3437 flush_ir_buffer_fill(ctx); 3438 break; 3439 default: 3440 ret = -ENOSYS; 3441 } 3442 3443 clear_bit_unlock(0, &ctx->flushing_completions); 3444 smp_mb__after_clear_bit(); 3445 } 3446 3447 tasklet_enable(&ctx->context.tasklet); 3448 3449 return ret; 3450 } 3451 3452 static const struct fw_card_driver ohci_driver = { 3453 .enable = ohci_enable, 3454 .read_phy_reg = ohci_read_phy_reg, 3455 .update_phy_reg = ohci_update_phy_reg, 3456 .set_config_rom = ohci_set_config_rom, 3457 .send_request = ohci_send_request, 3458 .send_response = ohci_send_response, 3459 .cancel_packet = ohci_cancel_packet, 3460 .enable_phys_dma = ohci_enable_phys_dma, 3461 .read_csr = ohci_read_csr, 3462 .write_csr = ohci_write_csr, 3463 3464 .allocate_iso_context = ohci_allocate_iso_context, 3465 .free_iso_context = ohci_free_iso_context, 3466 .set_iso_channels = ohci_set_iso_channels, 3467 .queue_iso = ohci_queue_iso, 3468 .flush_queue_iso = ohci_flush_queue_iso, 3469 .flush_iso_completions = ohci_flush_iso_completions, 3470 .start_iso = ohci_start_iso, 3471 .stop_iso = ohci_stop_iso, 3472 }; 3473 3474 #ifdef CONFIG_PPC_PMAC 3475 static void pmac_ohci_on(struct pci_dev *dev) 3476 { 3477 if (machine_is(powermac)) { 3478 struct device_node *ofn = pci_device_to_OF_node(dev); 3479 3480 if (ofn) { 3481 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3482 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3483 } 3484 } 3485 } 3486 3487 static void pmac_ohci_off(struct pci_dev *dev) 3488 { 3489 if (machine_is(powermac)) { 3490 struct device_node *ofn = pci_device_to_OF_node(dev); 3491 3492 if (ofn) { 3493 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3494 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3495 } 3496 } 3497 } 3498 #else 3499 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3500 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3501 #endif /* CONFIG_PPC_PMAC */ 3502 3503 static int __devinit pci_probe(struct pci_dev *dev, 3504 const struct pci_device_id *ent) 3505 { 3506 struct fw_ohci *ohci; 3507 u32 bus_options, max_receive, link_speed, version; 3508 u64 guid; 3509 int i, err; 3510 size_t size; 3511 3512 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3513 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3514 return -ENOSYS; 3515 } 3516 3517 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3518 if (ohci == NULL) { 3519 err = -ENOMEM; 3520 goto fail; 3521 } 3522 3523 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3524 3525 pmac_ohci_on(dev); 3526 3527 err = pci_enable_device(dev); 3528 if (err) { 3529 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3530 goto fail_free; 3531 } 3532 3533 pci_set_master(dev); 3534 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3535 pci_set_drvdata(dev, ohci); 3536 3537 spin_lock_init(&ohci->lock); 3538 mutex_init(&ohci->phy_reg_mutex); 3539 3540 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3541 3542 err = pci_request_region(dev, 0, ohci_driver_name); 3543 if (err) { 3544 dev_err(&dev->dev, "MMIO resource unavailable\n"); 3545 goto fail_disable; 3546 } 3547 3548 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3549 if (ohci->registers == NULL) { 3550 dev_err(&dev->dev, "failed to remap registers\n"); 3551 err = -ENXIO; 3552 goto fail_iomem; 3553 } 3554 3555 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3556 if ((ohci_quirks[i].vendor == dev->vendor) && 3557 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3558 ohci_quirks[i].device == dev->device) && 3559 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3560 ohci_quirks[i].revision >= dev->revision)) { 3561 ohci->quirks = ohci_quirks[i].flags; 3562 break; 3563 } 3564 if (param_quirks) 3565 ohci->quirks = param_quirks; 3566 3567 /* 3568 * Because dma_alloc_coherent() allocates at least one page, 3569 * we save space by using a common buffer for the AR request/ 3570 * response descriptors and the self IDs buffer. 3571 */ 3572 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3573 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3574 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3575 PAGE_SIZE, 3576 &ohci->misc_buffer_bus, 3577 GFP_KERNEL); 3578 if (!ohci->misc_buffer) { 3579 err = -ENOMEM; 3580 goto fail_iounmap; 3581 } 3582 3583 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3584 OHCI1394_AsReqRcvContextControlSet); 3585 if (err < 0) 3586 goto fail_misc_buf; 3587 3588 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3589 OHCI1394_AsRspRcvContextControlSet); 3590 if (err < 0) 3591 goto fail_arreq_ctx; 3592 3593 err = context_init(&ohci->at_request_ctx, ohci, 3594 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3595 if (err < 0) 3596 goto fail_arrsp_ctx; 3597 3598 err = context_init(&ohci->at_response_ctx, ohci, 3599 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3600 if (err < 0) 3601 goto fail_atreq_ctx; 3602 3603 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3604 ohci->ir_context_channels = ~0ULL; 3605 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3606 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3607 ohci->ir_context_mask = ohci->ir_context_support; 3608 ohci->n_ir = hweight32(ohci->ir_context_mask); 3609 size = sizeof(struct iso_context) * ohci->n_ir; 3610 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3611 3612 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3613 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3614 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3615 ohci->it_context_mask = ohci->it_context_support; 3616 ohci->n_it = hweight32(ohci->it_context_mask); 3617 size = sizeof(struct iso_context) * ohci->n_it; 3618 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3619 3620 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3621 err = -ENOMEM; 3622 goto fail_contexts; 3623 } 3624 3625 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2; 3626 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3627 3628 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3629 max_receive = (bus_options >> 12) & 0xf; 3630 link_speed = bus_options & 0x7; 3631 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3632 reg_read(ohci, OHCI1394_GUIDLo); 3633 3634 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3635 if (err) 3636 goto fail_contexts; 3637 3638 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3639 dev_notice(&dev->dev, 3640 "added OHCI v%x.%x device as card %d, " 3641 "%d IR + %d IT contexts, quirks 0x%x\n", 3642 version >> 16, version & 0xff, ohci->card.index, 3643 ohci->n_ir, ohci->n_it, ohci->quirks); 3644 3645 return 0; 3646 3647 fail_contexts: 3648 kfree(ohci->ir_context_list); 3649 kfree(ohci->it_context_list); 3650 context_release(&ohci->at_response_ctx); 3651 fail_atreq_ctx: 3652 context_release(&ohci->at_request_ctx); 3653 fail_arrsp_ctx: 3654 ar_context_release(&ohci->ar_response_ctx); 3655 fail_arreq_ctx: 3656 ar_context_release(&ohci->ar_request_ctx); 3657 fail_misc_buf: 3658 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3659 ohci->misc_buffer, ohci->misc_buffer_bus); 3660 fail_iounmap: 3661 pci_iounmap(dev, ohci->registers); 3662 fail_iomem: 3663 pci_release_region(dev, 0); 3664 fail_disable: 3665 pci_disable_device(dev); 3666 fail_free: 3667 kfree(ohci); 3668 pmac_ohci_off(dev); 3669 fail: 3670 if (err == -ENOMEM) 3671 dev_err(&dev->dev, "out of memory\n"); 3672 3673 return err; 3674 } 3675 3676 static void pci_remove(struct pci_dev *dev) 3677 { 3678 struct fw_ohci *ohci; 3679 3680 ohci = pci_get_drvdata(dev); 3681 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3682 flush_writes(ohci); 3683 cancel_work_sync(&ohci->bus_reset_work); 3684 fw_core_remove_card(&ohci->card); 3685 3686 /* 3687 * FIXME: Fail all pending packets here, now that the upper 3688 * layers can't queue any more. 3689 */ 3690 3691 software_reset(ohci); 3692 free_irq(dev->irq, ohci); 3693 3694 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3695 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3696 ohci->next_config_rom, ohci->next_config_rom_bus); 3697 if (ohci->config_rom) 3698 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3699 ohci->config_rom, ohci->config_rom_bus); 3700 ar_context_release(&ohci->ar_request_ctx); 3701 ar_context_release(&ohci->ar_response_ctx); 3702 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3703 ohci->misc_buffer, ohci->misc_buffer_bus); 3704 context_release(&ohci->at_request_ctx); 3705 context_release(&ohci->at_response_ctx); 3706 kfree(ohci->it_context_list); 3707 kfree(ohci->ir_context_list); 3708 pci_disable_msi(dev); 3709 pci_iounmap(dev, ohci->registers); 3710 pci_release_region(dev, 0); 3711 pci_disable_device(dev); 3712 kfree(ohci); 3713 pmac_ohci_off(dev); 3714 3715 dev_notice(&dev->dev, "removed fw-ohci device\n"); 3716 } 3717 3718 #ifdef CONFIG_PM 3719 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3720 { 3721 struct fw_ohci *ohci = pci_get_drvdata(dev); 3722 int err; 3723 3724 software_reset(ohci); 3725 free_irq(dev->irq, ohci); 3726 pci_disable_msi(dev); 3727 err = pci_save_state(dev); 3728 if (err) { 3729 dev_err(&dev->dev, "pci_save_state failed\n"); 3730 return err; 3731 } 3732 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3733 if (err) 3734 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err); 3735 pmac_ohci_off(dev); 3736 3737 return 0; 3738 } 3739 3740 static int pci_resume(struct pci_dev *dev) 3741 { 3742 struct fw_ohci *ohci = pci_get_drvdata(dev); 3743 int err; 3744 3745 pmac_ohci_on(dev); 3746 pci_set_power_state(dev, PCI_D0); 3747 pci_restore_state(dev); 3748 err = pci_enable_device(dev); 3749 if (err) { 3750 dev_err(&dev->dev, "pci_enable_device failed\n"); 3751 return err; 3752 } 3753 3754 /* Some systems don't setup GUID register on resume from ram */ 3755 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3756 !reg_read(ohci, OHCI1394_GUIDHi)) { 3757 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3758 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3759 } 3760 3761 err = ohci_enable(&ohci->card, NULL, 0); 3762 if (err) 3763 return err; 3764 3765 ohci_resume_iso_dma(ohci); 3766 3767 return 0; 3768 } 3769 #endif 3770 3771 static const struct pci_device_id pci_table[] = { 3772 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3773 { } 3774 }; 3775 3776 MODULE_DEVICE_TABLE(pci, pci_table); 3777 3778 static struct pci_driver fw_ohci_pci_driver = { 3779 .name = ohci_driver_name, 3780 .id_table = pci_table, 3781 .probe = pci_probe, 3782 .remove = pci_remove, 3783 #ifdef CONFIG_PM 3784 .resume = pci_resume, 3785 .suspend = pci_suspend, 3786 #endif 3787 }; 3788 3789 module_pci_driver(fw_ohci_pci_driver); 3790 3791 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3792 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3793 MODULE_LICENSE("GPL"); 3794 3795 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3796 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE 3797 MODULE_ALIAS("ohci1394"); 3798 #endif 3799