1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bug.h> 22 #include <linux/compiler.h> 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/firewire.h> 27 #include <linux/firewire-constants.h> 28 #include <linux/init.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/kernel.h> 32 #include <linux/list.h> 33 #include <linux/mm.h> 34 #include <linux/module.h> 35 #include <linux/moduleparam.h> 36 #include <linux/mutex.h> 37 #include <linux/pci.h> 38 #include <linux/pci_ids.h> 39 #include <linux/slab.h> 40 #include <linux/spinlock.h> 41 #include <linux/string.h> 42 #include <linux/time.h> 43 44 #include <asm/byteorder.h> 45 #include <asm/page.h> 46 #include <asm/system.h> 47 48 #ifdef CONFIG_PPC_PMAC 49 #include <asm/pmac_feature.h> 50 #endif 51 52 #include "core.h" 53 #include "ohci.h" 54 55 #define DESCRIPTOR_OUTPUT_MORE 0 56 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 57 #define DESCRIPTOR_INPUT_MORE (2 << 12) 58 #define DESCRIPTOR_INPUT_LAST (3 << 12) 59 #define DESCRIPTOR_STATUS (1 << 11) 60 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 61 #define DESCRIPTOR_PING (1 << 7) 62 #define DESCRIPTOR_YY (1 << 6) 63 #define DESCRIPTOR_NO_IRQ (0 << 4) 64 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 65 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 66 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 67 #define DESCRIPTOR_WAIT (3 << 0) 68 69 struct descriptor { 70 __le16 req_count; 71 __le16 control; 72 __le32 data_address; 73 __le32 branch_address; 74 __le16 res_count; 75 __le16 transfer_status; 76 } __attribute__((aligned(16))); 77 78 #define CONTROL_SET(regs) (regs) 79 #define CONTROL_CLEAR(regs) ((regs) + 4) 80 #define COMMAND_PTR(regs) ((regs) + 12) 81 #define CONTEXT_MATCH(regs) ((regs) + 16) 82 83 struct ar_buffer { 84 struct descriptor descriptor; 85 struct ar_buffer *next; 86 __le32 data[0]; 87 }; 88 89 struct ar_context { 90 struct fw_ohci *ohci; 91 struct ar_buffer *current_buffer; 92 struct ar_buffer *last_buffer; 93 void *pointer; 94 u32 regs; 95 struct tasklet_struct tasklet; 96 }; 97 98 struct context; 99 100 typedef int (*descriptor_callback_t)(struct context *ctx, 101 struct descriptor *d, 102 struct descriptor *last); 103 104 /* 105 * A buffer that contains a block of DMA-able coherent memory used for 106 * storing a portion of a DMA descriptor program. 107 */ 108 struct descriptor_buffer { 109 struct list_head list; 110 dma_addr_t buffer_bus; 111 size_t buffer_size; 112 size_t used; 113 struct descriptor buffer[0]; 114 }; 115 116 struct context { 117 struct fw_ohci *ohci; 118 u32 regs; 119 int total_allocation; 120 121 /* 122 * List of page-sized buffers for storing DMA descriptors. 123 * Head of list contains buffers in use and tail of list contains 124 * free buffers. 125 */ 126 struct list_head buffer_list; 127 128 /* 129 * Pointer to a buffer inside buffer_list that contains the tail 130 * end of the current DMA program. 131 */ 132 struct descriptor_buffer *buffer_tail; 133 134 /* 135 * The descriptor containing the branch address of the first 136 * descriptor that has not yet been filled by the device. 137 */ 138 struct descriptor *last; 139 140 /* 141 * The last descriptor in the DMA program. It contains the branch 142 * address that must be updated upon appending a new descriptor. 143 */ 144 struct descriptor *prev; 145 146 descriptor_callback_t callback; 147 148 struct tasklet_struct tasklet; 149 }; 150 151 #define IT_HEADER_SY(v) ((v) << 0) 152 #define IT_HEADER_TCODE(v) ((v) << 4) 153 #define IT_HEADER_CHANNEL(v) ((v) << 8) 154 #define IT_HEADER_TAG(v) ((v) << 14) 155 #define IT_HEADER_SPEED(v) ((v) << 16) 156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 157 158 struct iso_context { 159 struct fw_iso_context base; 160 struct context context; 161 int excess_bytes; 162 void *header; 163 size_t header_length; 164 }; 165 166 #define CONFIG_ROM_SIZE 1024 167 168 struct fw_ohci { 169 struct fw_card card; 170 171 __iomem char *registers; 172 int node_id; 173 int generation; 174 int request_generation; /* for timestamping incoming requests */ 175 unsigned quirks; 176 unsigned int pri_req_max; 177 u32 bus_time; 178 bool is_root; 179 bool csr_state_setclear_abdicate; 180 181 /* 182 * Spinlock for accessing fw_ohci data. Never call out of 183 * this driver with this lock held. 184 */ 185 spinlock_t lock; 186 187 struct mutex phy_reg_mutex; 188 189 struct ar_context ar_request_ctx; 190 struct ar_context ar_response_ctx; 191 struct context at_request_ctx; 192 struct context at_response_ctx; 193 194 u32 it_context_mask; /* unoccupied IT contexts */ 195 struct iso_context *it_context_list; 196 u64 ir_context_channels; /* unoccupied channels */ 197 u32 ir_context_mask; /* unoccupied IR contexts */ 198 struct iso_context *ir_context_list; 199 u64 mc_channels; /* channels in use by the multichannel IR context */ 200 bool mc_allocated; 201 202 __be32 *config_rom; 203 dma_addr_t config_rom_bus; 204 __be32 *next_config_rom; 205 dma_addr_t next_config_rom_bus; 206 __be32 next_header; 207 208 __le32 *self_id_cpu; 209 dma_addr_t self_id_bus; 210 struct tasklet_struct bus_reset_tasklet; 211 212 u32 self_id_buffer[512]; 213 }; 214 215 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 216 { 217 return container_of(card, struct fw_ohci, card); 218 } 219 220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 221 #define IR_CONTEXT_BUFFER_FILL 0x80000000 222 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 224 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 225 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 226 227 #define CONTEXT_RUN 0x8000 228 #define CONTEXT_WAKE 0x1000 229 #define CONTEXT_DEAD 0x0800 230 #define CONTEXT_ACTIVE 0x0400 231 232 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 233 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 234 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 235 236 #define OHCI1394_REGISTER_SIZE 0x800 237 #define OHCI_LOOP_COUNT 500 238 #define OHCI1394_PCI_HCI_Control 0x40 239 #define SELF_ID_BUF_SIZE 0x800 240 #define OHCI_TCODE_PHY_PACKET 0x0e 241 #define OHCI_VERSION_1_1 0x010010 242 243 static char ohci_driver_name[] = KBUILD_MODNAME; 244 245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 246 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 247 248 #define QUIRK_CYCLE_TIMER 1 249 #define QUIRK_RESET_PACKET 2 250 #define QUIRK_BE_HEADERS 4 251 #define QUIRK_NO_1394A 8 252 #define QUIRK_NO_MSI 16 253 254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 255 static const struct { 256 unsigned short vendor, device, flags; 257 } ohci_quirks[] = { 258 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER | 259 QUIRK_RESET_PACKET | 260 QUIRK_NO_1394A}, 261 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET}, 262 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, 263 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI}, 264 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, 265 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, 266 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, 267 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS}, 268 }; 269 270 /* This overrides anything that was found in ohci_quirks[]. */ 271 static int param_quirks; 272 module_param_named(quirks, param_quirks, int, 0644); 273 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 274 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 275 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 276 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) 277 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 278 ", disable MSI = " __stringify(QUIRK_NO_MSI) 279 ")"); 280 281 #define OHCI_PARAM_DEBUG_AT_AR 1 282 #define OHCI_PARAM_DEBUG_SELFIDS 2 283 #define OHCI_PARAM_DEBUG_IRQS 4 284 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 285 286 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 287 288 static int param_debug; 289 module_param_named(debug, param_debug, int, 0644); 290 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 291 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 292 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 293 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 294 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 295 ", or a combination, or all = -1)"); 296 297 static void log_irqs(u32 evt) 298 { 299 if (likely(!(param_debug & 300 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 301 return; 302 303 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 304 !(evt & OHCI1394_busReset)) 305 return; 306 307 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 308 evt & OHCI1394_selfIDComplete ? " selfID" : "", 309 evt & OHCI1394_RQPkt ? " AR_req" : "", 310 evt & OHCI1394_RSPkt ? " AR_resp" : "", 311 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 312 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 313 evt & OHCI1394_isochRx ? " IR" : "", 314 evt & OHCI1394_isochTx ? " IT" : "", 315 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 316 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 317 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 318 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 319 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 320 evt & OHCI1394_busReset ? " busReset" : "", 321 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 322 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 323 OHCI1394_respTxComplete | OHCI1394_isochRx | 324 OHCI1394_isochTx | OHCI1394_postedWriteErr | 325 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 326 OHCI1394_cycleInconsistent | 327 OHCI1394_regAccessFail | OHCI1394_busReset) 328 ? " ?" : ""); 329 } 330 331 static const char *speed[] = { 332 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 333 }; 334 static const char *power[] = { 335 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 336 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 337 }; 338 static const char port[] = { '.', '-', 'p', 'c', }; 339 340 static char _p(u32 *s, int shift) 341 { 342 return port[*s >> shift & 3]; 343 } 344 345 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) 346 { 347 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 348 return; 349 350 fw_notify("%d selfIDs, generation %d, local node ID %04x\n", 351 self_id_count, generation, node_id); 352 353 for (; self_id_count--; ++s) 354 if ((*s & 1 << 23) == 0) 355 fw_notify("selfID 0: %08x, phy %d [%c%c%c] " 356 "%s gc=%d %s %s%s%s\n", 357 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 358 speed[*s >> 14 & 3], *s >> 16 & 63, 359 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 360 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 361 else 362 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 363 *s, *s >> 24 & 63, 364 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 365 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 366 } 367 368 static const char *evts[] = { 369 [0x00] = "evt_no_status", [0x01] = "-reserved-", 370 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 371 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 372 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 373 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 374 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 375 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 376 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 377 [0x10] = "-reserved-", [0x11] = "ack_complete", 378 [0x12] = "ack_pending ", [0x13] = "-reserved-", 379 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 380 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 381 [0x18] = "-reserved-", [0x19] = "-reserved-", 382 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 383 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 384 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 385 [0x20] = "pending/cancelled", 386 }; 387 static const char *tcodes[] = { 388 [0x0] = "QW req", [0x1] = "BW req", 389 [0x2] = "W resp", [0x3] = "-reserved-", 390 [0x4] = "QR req", [0x5] = "BR req", 391 [0x6] = "QR resp", [0x7] = "BR resp", 392 [0x8] = "cycle start", [0x9] = "Lk req", 393 [0xa] = "async stream packet", [0xb] = "Lk resp", 394 [0xc] = "-reserved-", [0xd] = "-reserved-", 395 [0xe] = "link internal", [0xf] = "-reserved-", 396 }; 397 static const char *phys[] = { 398 [0x0] = "phy config packet", [0x1] = "link-on packet", 399 [0x2] = "self-id packet", [0x3] = "-reserved-", 400 }; 401 402 static void log_ar_at_event(char dir, int speed, u32 *header, int evt) 403 { 404 int tcode = header[0] >> 4 & 0xf; 405 char specific[12]; 406 407 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 408 return; 409 410 if (unlikely(evt >= ARRAY_SIZE(evts))) 411 evt = 0x1f; 412 413 if (evt == OHCI1394_evt_bus_reset) { 414 fw_notify("A%c evt_bus_reset, generation %d\n", 415 dir, (header[2] >> 16) & 0xff); 416 return; 417 } 418 419 if (header[0] == ~header[1]) { 420 fw_notify("A%c %s, %s, %08x\n", 421 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); 422 return; 423 } 424 425 switch (tcode) { 426 case 0x0: case 0x6: case 0x8: 427 snprintf(specific, sizeof(specific), " = %08x", 428 be32_to_cpu((__force __be32)header[3])); 429 break; 430 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 431 snprintf(specific, sizeof(specific), " %x,%x", 432 header[3] >> 16, header[3] & 0xffff); 433 break; 434 default: 435 specific[0] = '\0'; 436 } 437 438 switch (tcode) { 439 case 0xe: case 0xa: 440 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); 441 break; 442 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 443 fw_notify("A%c spd %x tl %02x, " 444 "%04x -> %04x, %s, " 445 "%s, %04x%08x%s\n", 446 dir, speed, header[0] >> 10 & 0x3f, 447 header[1] >> 16, header[0] >> 16, evts[evt], 448 tcodes[tcode], header[1] & 0xffff, header[2], specific); 449 break; 450 default: 451 fw_notify("A%c spd %x tl %02x, " 452 "%04x -> %04x, %s, " 453 "%s%s\n", 454 dir, speed, header[0] >> 10 & 0x3f, 455 header[1] >> 16, header[0] >> 16, evts[evt], 456 tcodes[tcode], specific); 457 } 458 } 459 460 #else 461 462 #define param_debug 0 463 static inline void log_irqs(u32 evt) {} 464 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} 465 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} 466 467 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ 468 469 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 470 { 471 writel(data, ohci->registers + offset); 472 } 473 474 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 475 { 476 return readl(ohci->registers + offset); 477 } 478 479 static inline void flush_writes(const struct fw_ohci *ohci) 480 { 481 /* Do a dummy read to flush writes. */ 482 reg_read(ohci, OHCI1394_Version); 483 } 484 485 static int read_phy_reg(struct fw_ohci *ohci, int addr) 486 { 487 u32 val; 488 int i; 489 490 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 491 for (i = 0; i < 3 + 100; i++) { 492 val = reg_read(ohci, OHCI1394_PhyControl); 493 if (val & OHCI1394_PhyControl_ReadDone) 494 return OHCI1394_PhyControl_ReadData(val); 495 496 /* 497 * Try a few times without waiting. Sleeping is necessary 498 * only when the link/PHY interface is busy. 499 */ 500 if (i >= 3) 501 msleep(1); 502 } 503 fw_error("failed to read phy reg\n"); 504 505 return -EBUSY; 506 } 507 508 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 509 { 510 int i; 511 512 reg_write(ohci, OHCI1394_PhyControl, 513 OHCI1394_PhyControl_Write(addr, val)); 514 for (i = 0; i < 3 + 100; i++) { 515 val = reg_read(ohci, OHCI1394_PhyControl); 516 if (!(val & OHCI1394_PhyControl_WritePending)) 517 return 0; 518 519 if (i >= 3) 520 msleep(1); 521 } 522 fw_error("failed to write phy reg\n"); 523 524 return -EBUSY; 525 } 526 527 static int update_phy_reg(struct fw_ohci *ohci, int addr, 528 int clear_bits, int set_bits) 529 { 530 int ret = read_phy_reg(ohci, addr); 531 if (ret < 0) 532 return ret; 533 534 /* 535 * The interrupt status bits are cleared by writing a one bit. 536 * Avoid clearing them unless explicitly requested in set_bits. 537 */ 538 if (addr == 5) 539 clear_bits |= PHY_INT_STATUS_BITS; 540 541 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 542 } 543 544 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 545 { 546 int ret; 547 548 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 549 if (ret < 0) 550 return ret; 551 552 return read_phy_reg(ohci, addr); 553 } 554 555 static int ohci_read_phy_reg(struct fw_card *card, int addr) 556 { 557 struct fw_ohci *ohci = fw_ohci(card); 558 int ret; 559 560 mutex_lock(&ohci->phy_reg_mutex); 561 ret = read_phy_reg(ohci, addr); 562 mutex_unlock(&ohci->phy_reg_mutex); 563 564 return ret; 565 } 566 567 static int ohci_update_phy_reg(struct fw_card *card, int addr, 568 int clear_bits, int set_bits) 569 { 570 struct fw_ohci *ohci = fw_ohci(card); 571 int ret; 572 573 mutex_lock(&ohci->phy_reg_mutex); 574 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 575 mutex_unlock(&ohci->phy_reg_mutex); 576 577 return ret; 578 } 579 580 static int ar_context_add_page(struct ar_context *ctx) 581 { 582 struct device *dev = ctx->ohci->card.device; 583 struct ar_buffer *ab; 584 dma_addr_t uninitialized_var(ab_bus); 585 size_t offset; 586 587 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); 588 if (ab == NULL) 589 return -ENOMEM; 590 591 ab->next = NULL; 592 memset(&ab->descriptor, 0, sizeof(ab->descriptor)); 593 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 594 DESCRIPTOR_STATUS | 595 DESCRIPTOR_BRANCH_ALWAYS); 596 offset = offsetof(struct ar_buffer, data); 597 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); 598 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); 599 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); 600 ab->descriptor.branch_address = 0; 601 602 wmb(); /* finish init of new descriptors before branch_address update */ 603 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); 604 ctx->last_buffer->next = ab; 605 ctx->last_buffer = ab; 606 607 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 608 flush_writes(ctx->ohci); 609 610 return 0; 611 } 612 613 static void ar_context_release(struct ar_context *ctx) 614 { 615 struct ar_buffer *ab, *ab_next; 616 size_t offset; 617 dma_addr_t ab_bus; 618 619 for (ab = ctx->current_buffer; ab; ab = ab_next) { 620 ab_next = ab->next; 621 offset = offsetof(struct ar_buffer, data); 622 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; 623 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE, 624 ab, ab_bus); 625 } 626 } 627 628 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 629 #define cond_le32_to_cpu(v) \ 630 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 631 #else 632 #define cond_le32_to_cpu(v) le32_to_cpu(v) 633 #endif 634 635 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 636 { 637 struct fw_ohci *ohci = ctx->ohci; 638 struct fw_packet p; 639 u32 status, length, tcode; 640 int evt; 641 642 p.header[0] = cond_le32_to_cpu(buffer[0]); 643 p.header[1] = cond_le32_to_cpu(buffer[1]); 644 p.header[2] = cond_le32_to_cpu(buffer[2]); 645 646 tcode = (p.header[0] >> 4) & 0x0f; 647 switch (tcode) { 648 case TCODE_WRITE_QUADLET_REQUEST: 649 case TCODE_READ_QUADLET_RESPONSE: 650 p.header[3] = (__force __u32) buffer[3]; 651 p.header_length = 16; 652 p.payload_length = 0; 653 break; 654 655 case TCODE_READ_BLOCK_REQUEST : 656 p.header[3] = cond_le32_to_cpu(buffer[3]); 657 p.header_length = 16; 658 p.payload_length = 0; 659 break; 660 661 case TCODE_WRITE_BLOCK_REQUEST: 662 case TCODE_READ_BLOCK_RESPONSE: 663 case TCODE_LOCK_REQUEST: 664 case TCODE_LOCK_RESPONSE: 665 p.header[3] = cond_le32_to_cpu(buffer[3]); 666 p.header_length = 16; 667 p.payload_length = p.header[3] >> 16; 668 break; 669 670 case TCODE_WRITE_RESPONSE: 671 case TCODE_READ_QUADLET_REQUEST: 672 case OHCI_TCODE_PHY_PACKET: 673 p.header_length = 12; 674 p.payload_length = 0; 675 break; 676 677 default: 678 /* FIXME: Stop context, discard everything, and restart? */ 679 p.header_length = 0; 680 p.payload_length = 0; 681 } 682 683 p.payload = (void *) buffer + p.header_length; 684 685 /* FIXME: What to do about evt_* errors? */ 686 length = (p.header_length + p.payload_length + 3) / 4; 687 status = cond_le32_to_cpu(buffer[length]); 688 evt = (status >> 16) & 0x1f; 689 690 p.ack = evt - 16; 691 p.speed = (status >> 21) & 0x7; 692 p.timestamp = status & 0xffff; 693 p.generation = ohci->request_generation; 694 695 log_ar_at_event('R', p.speed, p.header, evt); 696 697 /* 698 * Several controllers, notably from NEC and VIA, forget to 699 * write ack_complete status at PHY packet reception. 700 */ 701 if (evt == OHCI1394_evt_no_status && 702 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 703 p.ack = ACK_COMPLETE; 704 705 /* 706 * The OHCI bus reset handler synthesizes a PHY packet with 707 * the new generation number when a bus reset happens (see 708 * section 8.4.2.3). This helps us determine when a request 709 * was received and make sure we send the response in the same 710 * generation. We only need this for requests; for responses 711 * we use the unique tlabel for finding the matching 712 * request. 713 * 714 * Alas some chips sometimes emit bus reset packets with a 715 * wrong generation. We set the correct generation for these 716 * at a slightly incorrect time (in bus_reset_tasklet). 717 */ 718 if (evt == OHCI1394_evt_bus_reset) { 719 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 720 ohci->request_generation = (p.header[2] >> 16) & 0xff; 721 } else if (ctx == &ohci->ar_request_ctx) { 722 fw_core_handle_request(&ohci->card, &p); 723 } else { 724 fw_core_handle_response(&ohci->card, &p); 725 } 726 727 return buffer + length + 1; 728 } 729 730 static void ar_context_tasklet(unsigned long data) 731 { 732 struct ar_context *ctx = (struct ar_context *)data; 733 struct fw_ohci *ohci = ctx->ohci; 734 struct ar_buffer *ab; 735 struct descriptor *d; 736 void *buffer, *end; 737 738 ab = ctx->current_buffer; 739 d = &ab->descriptor; 740 741 if (d->res_count == 0) { 742 size_t size, rest, offset; 743 dma_addr_t start_bus; 744 void *start; 745 746 /* 747 * This descriptor is finished and we may have a 748 * packet split across this and the next buffer. We 749 * reuse the page for reassembling the split packet. 750 */ 751 752 offset = offsetof(struct ar_buffer, data); 753 start = buffer = ab; 754 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; 755 756 ab = ab->next; 757 d = &ab->descriptor; 758 size = buffer + PAGE_SIZE - ctx->pointer; 759 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); 760 memmove(buffer, ctx->pointer, size); 761 memcpy(buffer + size, ab->data, rest); 762 ctx->current_buffer = ab; 763 ctx->pointer = (void *) ab->data + rest; 764 end = buffer + size + rest; 765 766 while (buffer < end) 767 buffer = handle_ar_packet(ctx, buffer); 768 769 dma_free_coherent(ohci->card.device, PAGE_SIZE, 770 start, start_bus); 771 ar_context_add_page(ctx); 772 } else { 773 buffer = ctx->pointer; 774 ctx->pointer = end = 775 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); 776 777 while (buffer < end) 778 buffer = handle_ar_packet(ctx, buffer); 779 } 780 } 781 782 static int ar_context_init(struct ar_context *ctx, 783 struct fw_ohci *ohci, u32 regs) 784 { 785 struct ar_buffer ab; 786 787 ctx->regs = regs; 788 ctx->ohci = ohci; 789 ctx->last_buffer = &ab; 790 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 791 792 ar_context_add_page(ctx); 793 ar_context_add_page(ctx); 794 ctx->current_buffer = ab.next; 795 ctx->pointer = ctx->current_buffer->data; 796 797 return 0; 798 } 799 800 static void ar_context_run(struct ar_context *ctx) 801 { 802 struct ar_buffer *ab = ctx->current_buffer; 803 dma_addr_t ab_bus; 804 size_t offset; 805 806 offset = offsetof(struct ar_buffer, data); 807 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; 808 809 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); 810 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 811 flush_writes(ctx->ohci); 812 } 813 814 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 815 { 816 int b, key; 817 818 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; 819 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; 820 821 /* figure out which descriptor the branch address goes in */ 822 if (z == 2 && (b == 3 || key == 2)) 823 return d; 824 else 825 return d + z - 1; 826 } 827 828 static void context_tasklet(unsigned long data) 829 { 830 struct context *ctx = (struct context *) data; 831 struct descriptor *d, *last; 832 u32 address; 833 int z; 834 struct descriptor_buffer *desc; 835 836 desc = list_entry(ctx->buffer_list.next, 837 struct descriptor_buffer, list); 838 last = ctx->last; 839 while (last->branch_address != 0) { 840 struct descriptor_buffer *old_desc = desc; 841 address = le32_to_cpu(last->branch_address); 842 z = address & 0xf; 843 address &= ~0xf; 844 845 /* If the branch address points to a buffer outside of the 846 * current buffer, advance to the next buffer. */ 847 if (address < desc->buffer_bus || 848 address >= desc->buffer_bus + desc->used) 849 desc = list_entry(desc->list.next, 850 struct descriptor_buffer, list); 851 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 852 last = find_branch_descriptor(d, z); 853 854 if (!ctx->callback(ctx, d, last)) 855 break; 856 857 if (old_desc != desc) { 858 /* If we've advanced to the next buffer, move the 859 * previous buffer to the free list. */ 860 unsigned long flags; 861 old_desc->used = 0; 862 spin_lock_irqsave(&ctx->ohci->lock, flags); 863 list_move_tail(&old_desc->list, &ctx->buffer_list); 864 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 865 } 866 ctx->last = last; 867 } 868 } 869 870 /* 871 * Allocate a new buffer and add it to the list of free buffers for this 872 * context. Must be called with ohci->lock held. 873 */ 874 static int context_add_buffer(struct context *ctx) 875 { 876 struct descriptor_buffer *desc; 877 dma_addr_t uninitialized_var(bus_addr); 878 int offset; 879 880 /* 881 * 16MB of descriptors should be far more than enough for any DMA 882 * program. This will catch run-away userspace or DoS attacks. 883 */ 884 if (ctx->total_allocation >= 16*1024*1024) 885 return -ENOMEM; 886 887 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 888 &bus_addr, GFP_ATOMIC); 889 if (!desc) 890 return -ENOMEM; 891 892 offset = (void *)&desc->buffer - (void *)desc; 893 desc->buffer_size = PAGE_SIZE - offset; 894 desc->buffer_bus = bus_addr + offset; 895 desc->used = 0; 896 897 list_add_tail(&desc->list, &ctx->buffer_list); 898 ctx->total_allocation += PAGE_SIZE; 899 900 return 0; 901 } 902 903 static int context_init(struct context *ctx, struct fw_ohci *ohci, 904 u32 regs, descriptor_callback_t callback) 905 { 906 ctx->ohci = ohci; 907 ctx->regs = regs; 908 ctx->total_allocation = 0; 909 910 INIT_LIST_HEAD(&ctx->buffer_list); 911 if (context_add_buffer(ctx) < 0) 912 return -ENOMEM; 913 914 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 915 struct descriptor_buffer, list); 916 917 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 918 ctx->callback = callback; 919 920 /* 921 * We put a dummy descriptor in the buffer that has a NULL 922 * branch address and looks like it's been sent. That way we 923 * have a descriptor to append DMA programs to. 924 */ 925 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 926 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 927 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 928 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 929 ctx->last = ctx->buffer_tail->buffer; 930 ctx->prev = ctx->buffer_tail->buffer; 931 932 return 0; 933 } 934 935 static void context_release(struct context *ctx) 936 { 937 struct fw_card *card = &ctx->ohci->card; 938 struct descriptor_buffer *desc, *tmp; 939 940 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 941 dma_free_coherent(card->device, PAGE_SIZE, desc, 942 desc->buffer_bus - 943 ((void *)&desc->buffer - (void *)desc)); 944 } 945 946 /* Must be called with ohci->lock held */ 947 static struct descriptor *context_get_descriptors(struct context *ctx, 948 int z, dma_addr_t *d_bus) 949 { 950 struct descriptor *d = NULL; 951 struct descriptor_buffer *desc = ctx->buffer_tail; 952 953 if (z * sizeof(*d) > desc->buffer_size) 954 return NULL; 955 956 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 957 /* No room for the descriptor in this buffer, so advance to the 958 * next one. */ 959 960 if (desc->list.next == &ctx->buffer_list) { 961 /* If there is no free buffer next in the list, 962 * allocate one. */ 963 if (context_add_buffer(ctx) < 0) 964 return NULL; 965 } 966 desc = list_entry(desc->list.next, 967 struct descriptor_buffer, list); 968 ctx->buffer_tail = desc; 969 } 970 971 d = desc->buffer + desc->used / sizeof(*d); 972 memset(d, 0, z * sizeof(*d)); 973 *d_bus = desc->buffer_bus + desc->used; 974 975 return d; 976 } 977 978 static void context_run(struct context *ctx, u32 extra) 979 { 980 struct fw_ohci *ohci = ctx->ohci; 981 982 reg_write(ohci, COMMAND_PTR(ctx->regs), 983 le32_to_cpu(ctx->last->branch_address)); 984 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 985 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 986 flush_writes(ohci); 987 } 988 989 static void context_append(struct context *ctx, 990 struct descriptor *d, int z, int extra) 991 { 992 dma_addr_t d_bus; 993 struct descriptor_buffer *desc = ctx->buffer_tail; 994 995 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 996 997 desc->used += (z + extra) * sizeof(*d); 998 999 wmb(); /* finish init of new descriptors before branch_address update */ 1000 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1001 ctx->prev = find_branch_descriptor(d, z); 1002 1003 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1004 flush_writes(ctx->ohci); 1005 } 1006 1007 static void context_stop(struct context *ctx) 1008 { 1009 u32 reg; 1010 int i; 1011 1012 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1013 flush_writes(ctx->ohci); 1014 1015 for (i = 0; i < 10; i++) { 1016 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); 1017 if ((reg & CONTEXT_ACTIVE) == 0) 1018 return; 1019 1020 mdelay(1); 1021 } 1022 fw_error("Error: DMA context still active (0x%08x)\n", reg); 1023 } 1024 1025 struct driver_data { 1026 struct fw_packet *packet; 1027 }; 1028 1029 /* 1030 * This function apppends a packet to the DMA queue for transmission. 1031 * Must always be called with the ochi->lock held to ensure proper 1032 * generation handling and locking around packet queue manipulation. 1033 */ 1034 static int at_context_queue_packet(struct context *ctx, 1035 struct fw_packet *packet) 1036 { 1037 struct fw_ohci *ohci = ctx->ohci; 1038 dma_addr_t d_bus, uninitialized_var(payload_bus); 1039 struct driver_data *driver_data; 1040 struct descriptor *d, *last; 1041 __le32 *header; 1042 int z, tcode; 1043 u32 reg; 1044 1045 d = context_get_descriptors(ctx, 4, &d_bus); 1046 if (d == NULL) { 1047 packet->ack = RCODE_SEND_ERROR; 1048 return -1; 1049 } 1050 1051 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1052 d[0].res_count = cpu_to_le16(packet->timestamp); 1053 1054 /* 1055 * The DMA format for asyncronous link packets is different 1056 * from the IEEE1394 layout, so shift the fields around 1057 * accordingly. If header_length is 8, it's a PHY packet, to 1058 * which we need to prepend an extra quadlet. 1059 */ 1060 1061 header = (__le32 *) &d[1]; 1062 switch (packet->header_length) { 1063 case 16: 1064 case 12: 1065 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1066 (packet->speed << 16)); 1067 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1068 (packet->header[0] & 0xffff0000)); 1069 header[2] = cpu_to_le32(packet->header[2]); 1070 1071 tcode = (packet->header[0] >> 4) & 0x0f; 1072 if (TCODE_IS_BLOCK_PACKET(tcode)) 1073 header[3] = cpu_to_le32(packet->header[3]); 1074 else 1075 header[3] = (__force __le32) packet->header[3]; 1076 1077 d[0].req_count = cpu_to_le16(packet->header_length); 1078 break; 1079 1080 case 8: 1081 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1082 (packet->speed << 16)); 1083 header[1] = cpu_to_le32(packet->header[0]); 1084 header[2] = cpu_to_le32(packet->header[1]); 1085 d[0].req_count = cpu_to_le16(12); 1086 1087 if (is_ping_packet(packet->header)) 1088 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1089 break; 1090 1091 case 4: 1092 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1093 (packet->speed << 16)); 1094 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1095 d[0].req_count = cpu_to_le16(8); 1096 break; 1097 1098 default: 1099 /* BUG(); */ 1100 packet->ack = RCODE_SEND_ERROR; 1101 return -1; 1102 } 1103 1104 driver_data = (struct driver_data *) &d[3]; 1105 driver_data->packet = packet; 1106 packet->driver_data = driver_data; 1107 1108 if (packet->payload_length > 0) { 1109 payload_bus = 1110 dma_map_single(ohci->card.device, packet->payload, 1111 packet->payload_length, DMA_TO_DEVICE); 1112 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1113 packet->ack = RCODE_SEND_ERROR; 1114 return -1; 1115 } 1116 packet->payload_bus = payload_bus; 1117 packet->payload_mapped = true; 1118 1119 d[2].req_count = cpu_to_le16(packet->payload_length); 1120 d[2].data_address = cpu_to_le32(payload_bus); 1121 last = &d[2]; 1122 z = 3; 1123 } else { 1124 last = &d[0]; 1125 z = 2; 1126 } 1127 1128 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1129 DESCRIPTOR_IRQ_ALWAYS | 1130 DESCRIPTOR_BRANCH_ALWAYS); 1131 1132 /* 1133 * If the controller and packet generations don't match, we need to 1134 * bail out and try again. If IntEvent.busReset is set, the AT context 1135 * is halted, so appending to the context and trying to run it is 1136 * futile. Most controllers do the right thing and just flush the AT 1137 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but 1138 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind 1139 * up stalling out. So we just bail out in software and try again 1140 * later, and everyone is happy. 1141 * FIXME: Document how the locking works. 1142 */ 1143 if (ohci->generation != packet->generation || 1144 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { 1145 if (packet->payload_mapped) 1146 dma_unmap_single(ohci->card.device, payload_bus, 1147 packet->payload_length, DMA_TO_DEVICE); 1148 packet->ack = RCODE_GENERATION; 1149 return -1; 1150 } 1151 1152 context_append(ctx, d, z, 4 - z); 1153 1154 /* If the context isn't already running, start it up. */ 1155 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); 1156 if ((reg & CONTEXT_RUN) == 0) 1157 context_run(ctx, 0); 1158 1159 return 0; 1160 } 1161 1162 static int handle_at_packet(struct context *context, 1163 struct descriptor *d, 1164 struct descriptor *last) 1165 { 1166 struct driver_data *driver_data; 1167 struct fw_packet *packet; 1168 struct fw_ohci *ohci = context->ohci; 1169 int evt; 1170 1171 if (last->transfer_status == 0) 1172 /* This descriptor isn't done yet, stop iteration. */ 1173 return 0; 1174 1175 driver_data = (struct driver_data *) &d[3]; 1176 packet = driver_data->packet; 1177 if (packet == NULL) 1178 /* This packet was cancelled, just continue. */ 1179 return 1; 1180 1181 if (packet->payload_mapped) 1182 dma_unmap_single(ohci->card.device, packet->payload_bus, 1183 packet->payload_length, DMA_TO_DEVICE); 1184 1185 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1186 packet->timestamp = le16_to_cpu(last->res_count); 1187 1188 log_ar_at_event('T', packet->speed, packet->header, evt); 1189 1190 switch (evt) { 1191 case OHCI1394_evt_timeout: 1192 /* Async response transmit timed out. */ 1193 packet->ack = RCODE_CANCELLED; 1194 break; 1195 1196 case OHCI1394_evt_flushed: 1197 /* 1198 * The packet was flushed should give same error as 1199 * when we try to use a stale generation count. 1200 */ 1201 packet->ack = RCODE_GENERATION; 1202 break; 1203 1204 case OHCI1394_evt_missing_ack: 1205 /* 1206 * Using a valid (current) generation count, but the 1207 * node is not on the bus or not sending acks. 1208 */ 1209 packet->ack = RCODE_NO_ACK; 1210 break; 1211 1212 case ACK_COMPLETE + 0x10: 1213 case ACK_PENDING + 0x10: 1214 case ACK_BUSY_X + 0x10: 1215 case ACK_BUSY_A + 0x10: 1216 case ACK_BUSY_B + 0x10: 1217 case ACK_DATA_ERROR + 0x10: 1218 case ACK_TYPE_ERROR + 0x10: 1219 packet->ack = evt - 0x10; 1220 break; 1221 1222 default: 1223 packet->ack = RCODE_SEND_ERROR; 1224 break; 1225 } 1226 1227 packet->callback(packet, &ohci->card, packet->ack); 1228 1229 return 1; 1230 } 1231 1232 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1233 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1234 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1235 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1236 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1237 1238 static void handle_local_rom(struct fw_ohci *ohci, 1239 struct fw_packet *packet, u32 csr) 1240 { 1241 struct fw_packet response; 1242 int tcode, length, i; 1243 1244 tcode = HEADER_GET_TCODE(packet->header[0]); 1245 if (TCODE_IS_BLOCK_PACKET(tcode)) 1246 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1247 else 1248 length = 4; 1249 1250 i = csr - CSR_CONFIG_ROM; 1251 if (i + length > CONFIG_ROM_SIZE) { 1252 fw_fill_response(&response, packet->header, 1253 RCODE_ADDRESS_ERROR, NULL, 0); 1254 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1255 fw_fill_response(&response, packet->header, 1256 RCODE_TYPE_ERROR, NULL, 0); 1257 } else { 1258 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1259 (void *) ohci->config_rom + i, length); 1260 } 1261 1262 fw_core_handle_response(&ohci->card, &response); 1263 } 1264 1265 static void handle_local_lock(struct fw_ohci *ohci, 1266 struct fw_packet *packet, u32 csr) 1267 { 1268 struct fw_packet response; 1269 int tcode, length, ext_tcode, sel, try; 1270 __be32 *payload, lock_old; 1271 u32 lock_arg, lock_data; 1272 1273 tcode = HEADER_GET_TCODE(packet->header[0]); 1274 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1275 payload = packet->payload; 1276 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1277 1278 if (tcode == TCODE_LOCK_REQUEST && 1279 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1280 lock_arg = be32_to_cpu(payload[0]); 1281 lock_data = be32_to_cpu(payload[1]); 1282 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1283 lock_arg = 0; 1284 lock_data = 0; 1285 } else { 1286 fw_fill_response(&response, packet->header, 1287 RCODE_TYPE_ERROR, NULL, 0); 1288 goto out; 1289 } 1290 1291 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1292 reg_write(ohci, OHCI1394_CSRData, lock_data); 1293 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1294 reg_write(ohci, OHCI1394_CSRControl, sel); 1295 1296 for (try = 0; try < 20; try++) 1297 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1298 lock_old = cpu_to_be32(reg_read(ohci, 1299 OHCI1394_CSRData)); 1300 fw_fill_response(&response, packet->header, 1301 RCODE_COMPLETE, 1302 &lock_old, sizeof(lock_old)); 1303 goto out; 1304 } 1305 1306 fw_error("swap not done (CSR lock timeout)\n"); 1307 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1308 1309 out: 1310 fw_core_handle_response(&ohci->card, &response); 1311 } 1312 1313 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1314 { 1315 u64 offset, csr; 1316 1317 if (ctx == &ctx->ohci->at_request_ctx) { 1318 packet->ack = ACK_PENDING; 1319 packet->callback(packet, &ctx->ohci->card, packet->ack); 1320 } 1321 1322 offset = 1323 ((unsigned long long) 1324 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1325 packet->header[2]; 1326 csr = offset - CSR_REGISTER_BASE; 1327 1328 /* Handle config rom reads. */ 1329 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1330 handle_local_rom(ctx->ohci, packet, csr); 1331 else switch (csr) { 1332 case CSR_BUS_MANAGER_ID: 1333 case CSR_BANDWIDTH_AVAILABLE: 1334 case CSR_CHANNELS_AVAILABLE_HI: 1335 case CSR_CHANNELS_AVAILABLE_LO: 1336 handle_local_lock(ctx->ohci, packet, csr); 1337 break; 1338 default: 1339 if (ctx == &ctx->ohci->at_request_ctx) 1340 fw_core_handle_request(&ctx->ohci->card, packet); 1341 else 1342 fw_core_handle_response(&ctx->ohci->card, packet); 1343 break; 1344 } 1345 1346 if (ctx == &ctx->ohci->at_response_ctx) { 1347 packet->ack = ACK_COMPLETE; 1348 packet->callback(packet, &ctx->ohci->card, packet->ack); 1349 } 1350 } 1351 1352 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1353 { 1354 unsigned long flags; 1355 int ret; 1356 1357 spin_lock_irqsave(&ctx->ohci->lock, flags); 1358 1359 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1360 ctx->ohci->generation == packet->generation) { 1361 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1362 handle_local_request(ctx, packet); 1363 return; 1364 } 1365 1366 ret = at_context_queue_packet(ctx, packet); 1367 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1368 1369 if (ret < 0) 1370 packet->callback(packet, &ctx->ohci->card, packet->ack); 1371 1372 } 1373 1374 static u32 cycle_timer_ticks(u32 cycle_timer) 1375 { 1376 u32 ticks; 1377 1378 ticks = cycle_timer & 0xfff; 1379 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1380 ticks += (3072 * 8000) * (cycle_timer >> 25); 1381 1382 return ticks; 1383 } 1384 1385 /* 1386 * Some controllers exhibit one or more of the following bugs when updating the 1387 * iso cycle timer register: 1388 * - When the lowest six bits are wrapping around to zero, a read that happens 1389 * at the same time will return garbage in the lowest ten bits. 1390 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1391 * not incremented for about 60 ns. 1392 * - Occasionally, the entire register reads zero. 1393 * 1394 * To catch these, we read the register three times and ensure that the 1395 * difference between each two consecutive reads is approximately the same, i.e. 1396 * less than twice the other. Furthermore, any negative difference indicates an 1397 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1398 * execute, so we have enough precision to compute the ratio of the differences.) 1399 */ 1400 static u32 get_cycle_time(struct fw_ohci *ohci) 1401 { 1402 u32 c0, c1, c2; 1403 u32 t0, t1, t2; 1404 s32 diff01, diff12; 1405 int i; 1406 1407 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1408 1409 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1410 i = 0; 1411 c1 = c2; 1412 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1413 do { 1414 c0 = c1; 1415 c1 = c2; 1416 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1417 t0 = cycle_timer_ticks(c0); 1418 t1 = cycle_timer_ticks(c1); 1419 t2 = cycle_timer_ticks(c2); 1420 diff01 = t1 - t0; 1421 diff12 = t2 - t1; 1422 } while ((diff01 <= 0 || diff12 <= 0 || 1423 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1424 && i++ < 20); 1425 } 1426 1427 return c2; 1428 } 1429 1430 /* 1431 * This function has to be called at least every 64 seconds. The bus_time 1432 * field stores not only the upper 25 bits of the BUS_TIME register but also 1433 * the most significant bit of the cycle timer in bit 6 so that we can detect 1434 * changes in this bit. 1435 */ 1436 static u32 update_bus_time(struct fw_ohci *ohci) 1437 { 1438 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1439 1440 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1441 ohci->bus_time += 0x40; 1442 1443 return ohci->bus_time | cycle_time_seconds; 1444 } 1445 1446 static void bus_reset_tasklet(unsigned long data) 1447 { 1448 struct fw_ohci *ohci = (struct fw_ohci *)data; 1449 int self_id_count, i, j, reg; 1450 int generation, new_generation; 1451 unsigned long flags; 1452 void *free_rom = NULL; 1453 dma_addr_t free_rom_bus = 0; 1454 bool is_new_root; 1455 1456 reg = reg_read(ohci, OHCI1394_NodeID); 1457 if (!(reg & OHCI1394_NodeID_idValid)) { 1458 fw_notify("node ID not valid, new bus reset in progress\n"); 1459 return; 1460 } 1461 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1462 fw_notify("malconfigured bus\n"); 1463 return; 1464 } 1465 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1466 OHCI1394_NodeID_nodeNumber); 1467 1468 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1469 if (!(ohci->is_root && is_new_root)) 1470 reg_write(ohci, OHCI1394_LinkControlSet, 1471 OHCI1394_LinkControl_cycleMaster); 1472 ohci->is_root = is_new_root; 1473 1474 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1475 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1476 fw_notify("inconsistent self IDs\n"); 1477 return; 1478 } 1479 /* 1480 * The count in the SelfIDCount register is the number of 1481 * bytes in the self ID receive buffer. Since we also receive 1482 * the inverted quadlets and a header quadlet, we shift one 1483 * bit extra to get the actual number of self IDs. 1484 */ 1485 self_id_count = (reg >> 3) & 0xff; 1486 if (self_id_count == 0 || self_id_count > 252) { 1487 fw_notify("inconsistent self IDs\n"); 1488 return; 1489 } 1490 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 1491 rmb(); 1492 1493 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1494 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { 1495 fw_notify("inconsistent self IDs\n"); 1496 return; 1497 } 1498 ohci->self_id_buffer[j] = 1499 cond_le32_to_cpu(ohci->self_id_cpu[i]); 1500 } 1501 rmb(); 1502 1503 /* 1504 * Check the consistency of the self IDs we just read. The 1505 * problem we face is that a new bus reset can start while we 1506 * read out the self IDs from the DMA buffer. If this happens, 1507 * the DMA buffer will be overwritten with new self IDs and we 1508 * will read out inconsistent data. The OHCI specification 1509 * (section 11.2) recommends a technique similar to 1510 * linux/seqlock.h, where we remember the generation of the 1511 * self IDs in the buffer before reading them out and compare 1512 * it to the current generation after reading them out. If 1513 * the two generations match we know we have a consistent set 1514 * of self IDs. 1515 */ 1516 1517 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1518 if (new_generation != generation) { 1519 fw_notify("recursive bus reset detected, " 1520 "discarding self ids\n"); 1521 return; 1522 } 1523 1524 /* FIXME: Document how the locking works. */ 1525 spin_lock_irqsave(&ohci->lock, flags); 1526 1527 ohci->generation = generation; 1528 context_stop(&ohci->at_request_ctx); 1529 context_stop(&ohci->at_response_ctx); 1530 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 1531 1532 if (ohci->quirks & QUIRK_RESET_PACKET) 1533 ohci->request_generation = generation; 1534 1535 /* 1536 * This next bit is unrelated to the AT context stuff but we 1537 * have to do it under the spinlock also. If a new config rom 1538 * was set up before this reset, the old one is now no longer 1539 * in use and we can free it. Update the config rom pointers 1540 * to point to the current config rom and clear the 1541 * next_config_rom pointer so a new update can take place. 1542 */ 1543 1544 if (ohci->next_config_rom != NULL) { 1545 if (ohci->next_config_rom != ohci->config_rom) { 1546 free_rom = ohci->config_rom; 1547 free_rom_bus = ohci->config_rom_bus; 1548 } 1549 ohci->config_rom = ohci->next_config_rom; 1550 ohci->config_rom_bus = ohci->next_config_rom_bus; 1551 ohci->next_config_rom = NULL; 1552 1553 /* 1554 * Restore config_rom image and manually update 1555 * config_rom registers. Writing the header quadlet 1556 * will indicate that the config rom is ready, so we 1557 * do that last. 1558 */ 1559 reg_write(ohci, OHCI1394_BusOptions, 1560 be32_to_cpu(ohci->config_rom[2])); 1561 ohci->config_rom[0] = ohci->next_header; 1562 reg_write(ohci, OHCI1394_ConfigROMhdr, 1563 be32_to_cpu(ohci->next_header)); 1564 } 1565 1566 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 1567 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 1568 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 1569 #endif 1570 1571 spin_unlock_irqrestore(&ohci->lock, flags); 1572 1573 if (free_rom) 1574 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1575 free_rom, free_rom_bus); 1576 1577 log_selfids(ohci->node_id, generation, 1578 self_id_count, ohci->self_id_buffer); 1579 1580 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 1581 self_id_count, ohci->self_id_buffer, 1582 ohci->csr_state_setclear_abdicate); 1583 ohci->csr_state_setclear_abdicate = false; 1584 } 1585 1586 static irqreturn_t irq_handler(int irq, void *data) 1587 { 1588 struct fw_ohci *ohci = data; 1589 u32 event, iso_event; 1590 int i; 1591 1592 event = reg_read(ohci, OHCI1394_IntEventClear); 1593 1594 if (!event || !~event) 1595 return IRQ_NONE; 1596 1597 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */ 1598 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); 1599 log_irqs(event); 1600 1601 if (event & OHCI1394_selfIDComplete) 1602 tasklet_schedule(&ohci->bus_reset_tasklet); 1603 1604 if (event & OHCI1394_RQPkt) 1605 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 1606 1607 if (event & OHCI1394_RSPkt) 1608 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 1609 1610 if (event & OHCI1394_reqTxComplete) 1611 tasklet_schedule(&ohci->at_request_ctx.tasklet); 1612 1613 if (event & OHCI1394_respTxComplete) 1614 tasklet_schedule(&ohci->at_response_ctx.tasklet); 1615 1616 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 1617 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 1618 1619 while (iso_event) { 1620 i = ffs(iso_event) - 1; 1621 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); 1622 iso_event &= ~(1 << i); 1623 } 1624 1625 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 1626 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 1627 1628 while (iso_event) { 1629 i = ffs(iso_event) - 1; 1630 tasklet_schedule(&ohci->it_context_list[i].context.tasklet); 1631 iso_event &= ~(1 << i); 1632 } 1633 1634 if (unlikely(event & OHCI1394_regAccessFail)) 1635 fw_error("Register access failure - " 1636 "please notify linux1394-devel@lists.sf.net\n"); 1637 1638 if (unlikely(event & OHCI1394_postedWriteErr)) 1639 fw_error("PCI posted write error\n"); 1640 1641 if (unlikely(event & OHCI1394_cycleTooLong)) { 1642 if (printk_ratelimit()) 1643 fw_notify("isochronous cycle too long\n"); 1644 reg_write(ohci, OHCI1394_LinkControlSet, 1645 OHCI1394_LinkControl_cycleMaster); 1646 } 1647 1648 if (unlikely(event & OHCI1394_cycleInconsistent)) { 1649 /* 1650 * We need to clear this event bit in order to make 1651 * cycleMatch isochronous I/O work. In theory we should 1652 * stop active cycleMatch iso contexts now and restart 1653 * them at least two cycles later. (FIXME?) 1654 */ 1655 if (printk_ratelimit()) 1656 fw_notify("isochronous cycle inconsistent\n"); 1657 } 1658 1659 if (event & OHCI1394_cycle64Seconds) { 1660 spin_lock(&ohci->lock); 1661 update_bus_time(ohci); 1662 spin_unlock(&ohci->lock); 1663 } 1664 1665 return IRQ_HANDLED; 1666 } 1667 1668 static int software_reset(struct fw_ohci *ohci) 1669 { 1670 int i; 1671 1672 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 1673 1674 for (i = 0; i < OHCI_LOOP_COUNT; i++) { 1675 if ((reg_read(ohci, OHCI1394_HCControlSet) & 1676 OHCI1394_HCControl_softReset) == 0) 1677 return 0; 1678 msleep(1); 1679 } 1680 1681 return -EBUSY; 1682 } 1683 1684 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 1685 { 1686 size_t size = length * 4; 1687 1688 memcpy(dest, src, size); 1689 if (size < CONFIG_ROM_SIZE) 1690 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 1691 } 1692 1693 static int configure_1394a_enhancements(struct fw_ohci *ohci) 1694 { 1695 bool enable_1394a; 1696 int ret, clear, set, offset; 1697 1698 /* Check if the driver should configure link and PHY. */ 1699 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 1700 OHCI1394_HCControl_programPhyEnable)) 1701 return 0; 1702 1703 /* Paranoia: check whether the PHY supports 1394a, too. */ 1704 enable_1394a = false; 1705 ret = read_phy_reg(ohci, 2); 1706 if (ret < 0) 1707 return ret; 1708 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 1709 ret = read_paged_phy_reg(ohci, 1, 8); 1710 if (ret < 0) 1711 return ret; 1712 if (ret >= 1) 1713 enable_1394a = true; 1714 } 1715 1716 if (ohci->quirks & QUIRK_NO_1394A) 1717 enable_1394a = false; 1718 1719 /* Configure PHY and link consistently. */ 1720 if (enable_1394a) { 1721 clear = 0; 1722 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 1723 } else { 1724 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 1725 set = 0; 1726 } 1727 ret = update_phy_reg(ohci, 5, clear, set); 1728 if (ret < 0) 1729 return ret; 1730 1731 if (enable_1394a) 1732 offset = OHCI1394_HCControlSet; 1733 else 1734 offset = OHCI1394_HCControlClear; 1735 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 1736 1737 /* Clean up: configuration has been taken care of. */ 1738 reg_write(ohci, OHCI1394_HCControlClear, 1739 OHCI1394_HCControl_programPhyEnable); 1740 1741 return 0; 1742 } 1743 1744 static int ohci_enable(struct fw_card *card, 1745 const __be32 *config_rom, size_t length) 1746 { 1747 struct fw_ohci *ohci = fw_ohci(card); 1748 struct pci_dev *dev = to_pci_dev(card->device); 1749 u32 lps, seconds, version, irqs; 1750 int i, ret; 1751 1752 if (software_reset(ohci)) { 1753 fw_error("Failed to reset ohci card.\n"); 1754 return -EBUSY; 1755 } 1756 1757 /* 1758 * Now enable LPS, which we need in order to start accessing 1759 * most of the registers. In fact, on some cards (ALI M5251), 1760 * accessing registers in the SClk domain without LPS enabled 1761 * will lock up the machine. Wait 50msec to make sure we have 1762 * full link enabled. However, with some cards (well, at least 1763 * a JMicron PCIe card), we have to try again sometimes. 1764 */ 1765 reg_write(ohci, OHCI1394_HCControlSet, 1766 OHCI1394_HCControl_LPS | 1767 OHCI1394_HCControl_postedWriteEnable); 1768 flush_writes(ohci); 1769 1770 for (lps = 0, i = 0; !lps && i < 3; i++) { 1771 msleep(50); 1772 lps = reg_read(ohci, OHCI1394_HCControlSet) & 1773 OHCI1394_HCControl_LPS; 1774 } 1775 1776 if (!lps) { 1777 fw_error("Failed to set Link Power Status\n"); 1778 return -EIO; 1779 } 1780 1781 reg_write(ohci, OHCI1394_HCControlClear, 1782 OHCI1394_HCControl_noByteSwapData); 1783 1784 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 1785 reg_write(ohci, OHCI1394_LinkControlSet, 1786 OHCI1394_LinkControl_rcvSelfID | 1787 OHCI1394_LinkControl_rcvPhyPkt | 1788 OHCI1394_LinkControl_cycleTimerEnable | 1789 OHCI1394_LinkControl_cycleMaster); 1790 1791 reg_write(ohci, OHCI1394_ATRetries, 1792 OHCI1394_MAX_AT_REQ_RETRIES | 1793 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 1794 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 1795 (200 << 16)); 1796 1797 seconds = lower_32_bits(get_seconds()); 1798 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 1799 ohci->bus_time = seconds & ~0x3f; 1800 1801 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 1802 if (version >= OHCI_VERSION_1_1) { 1803 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 1804 0xfffffffe); 1805 card->broadcast_channel_auto_allocated = true; 1806 } 1807 1808 /* Get implemented bits of the priority arbitration request counter. */ 1809 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 1810 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 1811 reg_write(ohci, OHCI1394_FairnessControl, 0); 1812 card->priority_budget_implemented = ohci->pri_req_max != 0; 1813 1814 ar_context_run(&ohci->ar_request_ctx); 1815 ar_context_run(&ohci->ar_response_ctx); 1816 1817 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 1818 reg_write(ohci, OHCI1394_IntEventClear, ~0); 1819 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 1820 1821 ret = configure_1394a_enhancements(ohci); 1822 if (ret < 0) 1823 return ret; 1824 1825 /* Activate link_on bit and contender bit in our self ID packets.*/ 1826 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 1827 if (ret < 0) 1828 return ret; 1829 1830 /* 1831 * When the link is not yet enabled, the atomic config rom 1832 * update mechanism described below in ohci_set_config_rom() 1833 * is not active. We have to update ConfigRomHeader and 1834 * BusOptions manually, and the write to ConfigROMmap takes 1835 * effect immediately. We tie this to the enabling of the 1836 * link, so we have a valid config rom before enabling - the 1837 * OHCI requires that ConfigROMhdr and BusOptions have valid 1838 * values before enabling. 1839 * 1840 * However, when the ConfigROMmap is written, some controllers 1841 * always read back quadlets 0 and 2 from the config rom to 1842 * the ConfigRomHeader and BusOptions registers on bus reset. 1843 * They shouldn't do that in this initial case where the link 1844 * isn't enabled. This means we have to use the same 1845 * workaround here, setting the bus header to 0 and then write 1846 * the right values in the bus reset tasklet. 1847 */ 1848 1849 if (config_rom) { 1850 ohci->next_config_rom = 1851 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1852 &ohci->next_config_rom_bus, 1853 GFP_KERNEL); 1854 if (ohci->next_config_rom == NULL) 1855 return -ENOMEM; 1856 1857 copy_config_rom(ohci->next_config_rom, config_rom, length); 1858 } else { 1859 /* 1860 * In the suspend case, config_rom is NULL, which 1861 * means that we just reuse the old config rom. 1862 */ 1863 ohci->next_config_rom = ohci->config_rom; 1864 ohci->next_config_rom_bus = ohci->config_rom_bus; 1865 } 1866 1867 ohci->next_header = ohci->next_config_rom[0]; 1868 ohci->next_config_rom[0] = 0; 1869 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 1870 reg_write(ohci, OHCI1394_BusOptions, 1871 be32_to_cpu(ohci->next_config_rom[2])); 1872 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 1873 1874 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 1875 1876 if (!(ohci->quirks & QUIRK_NO_MSI)) 1877 pci_enable_msi(dev); 1878 if (request_irq(dev->irq, irq_handler, 1879 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 1880 ohci_driver_name, ohci)) { 1881 fw_error("Failed to allocate interrupt %d.\n", dev->irq); 1882 pci_disable_msi(dev); 1883 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1884 ohci->config_rom, ohci->config_rom_bus); 1885 return -EIO; 1886 } 1887 1888 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 1889 OHCI1394_RQPkt | OHCI1394_RSPkt | 1890 OHCI1394_isochTx | OHCI1394_isochRx | 1891 OHCI1394_postedWriteErr | 1892 OHCI1394_selfIDComplete | 1893 OHCI1394_regAccessFail | 1894 OHCI1394_cycle64Seconds | 1895 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong | 1896 OHCI1394_masterIntEnable; 1897 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 1898 irqs |= OHCI1394_busReset; 1899 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 1900 1901 reg_write(ohci, OHCI1394_HCControlSet, 1902 OHCI1394_HCControl_linkEnable | 1903 OHCI1394_HCControl_BIBimageValid); 1904 flush_writes(ohci); 1905 1906 /* We are ready to go, reset bus to finish initialization. */ 1907 fw_schedule_bus_reset(&ohci->card, false, true); 1908 1909 return 0; 1910 } 1911 1912 static int ohci_set_config_rom(struct fw_card *card, 1913 const __be32 *config_rom, size_t length) 1914 { 1915 struct fw_ohci *ohci; 1916 unsigned long flags; 1917 int ret = -EBUSY; 1918 __be32 *next_config_rom; 1919 dma_addr_t uninitialized_var(next_config_rom_bus); 1920 1921 ohci = fw_ohci(card); 1922 1923 /* 1924 * When the OHCI controller is enabled, the config rom update 1925 * mechanism is a bit tricky, but easy enough to use. See 1926 * section 5.5.6 in the OHCI specification. 1927 * 1928 * The OHCI controller caches the new config rom address in a 1929 * shadow register (ConfigROMmapNext) and needs a bus reset 1930 * for the changes to take place. When the bus reset is 1931 * detected, the controller loads the new values for the 1932 * ConfigRomHeader and BusOptions registers from the specified 1933 * config rom and loads ConfigROMmap from the ConfigROMmapNext 1934 * shadow register. All automatically and atomically. 1935 * 1936 * Now, there's a twist to this story. The automatic load of 1937 * ConfigRomHeader and BusOptions doesn't honor the 1938 * noByteSwapData bit, so with a be32 config rom, the 1939 * controller will load be32 values in to these registers 1940 * during the atomic update, even on litte endian 1941 * architectures. The workaround we use is to put a 0 in the 1942 * header quadlet; 0 is endian agnostic and means that the 1943 * config rom isn't ready yet. In the bus reset tasklet we 1944 * then set up the real values for the two registers. 1945 * 1946 * We use ohci->lock to avoid racing with the code that sets 1947 * ohci->next_config_rom to NULL (see bus_reset_tasklet). 1948 */ 1949 1950 next_config_rom = 1951 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1952 &next_config_rom_bus, GFP_KERNEL); 1953 if (next_config_rom == NULL) 1954 return -ENOMEM; 1955 1956 spin_lock_irqsave(&ohci->lock, flags); 1957 1958 if (ohci->next_config_rom == NULL) { 1959 ohci->next_config_rom = next_config_rom; 1960 ohci->next_config_rom_bus = next_config_rom_bus; 1961 1962 copy_config_rom(ohci->next_config_rom, config_rom, length); 1963 1964 ohci->next_header = config_rom[0]; 1965 ohci->next_config_rom[0] = 0; 1966 1967 reg_write(ohci, OHCI1394_ConfigROMmap, 1968 ohci->next_config_rom_bus); 1969 ret = 0; 1970 } 1971 1972 spin_unlock_irqrestore(&ohci->lock, flags); 1973 1974 /* 1975 * Now initiate a bus reset to have the changes take 1976 * effect. We clean up the old config rom memory and DMA 1977 * mappings in the bus reset tasklet, since the OHCI 1978 * controller could need to access it before the bus reset 1979 * takes effect. 1980 */ 1981 if (ret == 0) 1982 fw_schedule_bus_reset(&ohci->card, true, true); 1983 else 1984 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1985 next_config_rom, next_config_rom_bus); 1986 1987 return ret; 1988 } 1989 1990 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 1991 { 1992 struct fw_ohci *ohci = fw_ohci(card); 1993 1994 at_context_transmit(&ohci->at_request_ctx, packet); 1995 } 1996 1997 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 1998 { 1999 struct fw_ohci *ohci = fw_ohci(card); 2000 2001 at_context_transmit(&ohci->at_response_ctx, packet); 2002 } 2003 2004 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2005 { 2006 struct fw_ohci *ohci = fw_ohci(card); 2007 struct context *ctx = &ohci->at_request_ctx; 2008 struct driver_data *driver_data = packet->driver_data; 2009 int ret = -ENOENT; 2010 2011 tasklet_disable(&ctx->tasklet); 2012 2013 if (packet->ack != 0) 2014 goto out; 2015 2016 if (packet->payload_mapped) 2017 dma_unmap_single(ohci->card.device, packet->payload_bus, 2018 packet->payload_length, DMA_TO_DEVICE); 2019 2020 log_ar_at_event('T', packet->speed, packet->header, 0x20); 2021 driver_data->packet = NULL; 2022 packet->ack = RCODE_CANCELLED; 2023 packet->callback(packet, &ohci->card, packet->ack); 2024 ret = 0; 2025 out: 2026 tasklet_enable(&ctx->tasklet); 2027 2028 return ret; 2029 } 2030 2031 static int ohci_enable_phys_dma(struct fw_card *card, 2032 int node_id, int generation) 2033 { 2034 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2035 return 0; 2036 #else 2037 struct fw_ohci *ohci = fw_ohci(card); 2038 unsigned long flags; 2039 int n, ret = 0; 2040 2041 /* 2042 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2043 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2044 */ 2045 2046 spin_lock_irqsave(&ohci->lock, flags); 2047 2048 if (ohci->generation != generation) { 2049 ret = -ESTALE; 2050 goto out; 2051 } 2052 2053 /* 2054 * Note, if the node ID contains a non-local bus ID, physical DMA is 2055 * enabled for _all_ nodes on remote buses. 2056 */ 2057 2058 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2059 if (n < 32) 2060 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2061 else 2062 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2063 2064 flush_writes(ohci); 2065 out: 2066 spin_unlock_irqrestore(&ohci->lock, flags); 2067 2068 return ret; 2069 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2070 } 2071 2072 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2073 { 2074 struct fw_ohci *ohci = fw_ohci(card); 2075 unsigned long flags; 2076 u32 value; 2077 2078 switch (csr_offset) { 2079 case CSR_STATE_CLEAR: 2080 case CSR_STATE_SET: 2081 if (ohci->is_root && 2082 (reg_read(ohci, OHCI1394_LinkControlSet) & 2083 OHCI1394_LinkControl_cycleMaster)) 2084 value = CSR_STATE_BIT_CMSTR; 2085 else 2086 value = 0; 2087 if (ohci->csr_state_setclear_abdicate) 2088 value |= CSR_STATE_BIT_ABDICATE; 2089 2090 return value; 2091 2092 case CSR_NODE_IDS: 2093 return reg_read(ohci, OHCI1394_NodeID) << 16; 2094 2095 case CSR_CYCLE_TIME: 2096 return get_cycle_time(ohci); 2097 2098 case CSR_BUS_TIME: 2099 /* 2100 * We might be called just after the cycle timer has wrapped 2101 * around but just before the cycle64Seconds handler, so we 2102 * better check here, too, if the bus time needs to be updated. 2103 */ 2104 spin_lock_irqsave(&ohci->lock, flags); 2105 value = update_bus_time(ohci); 2106 spin_unlock_irqrestore(&ohci->lock, flags); 2107 return value; 2108 2109 case CSR_BUSY_TIMEOUT: 2110 value = reg_read(ohci, OHCI1394_ATRetries); 2111 return (value >> 4) & 0x0ffff00f; 2112 2113 case CSR_PRIORITY_BUDGET: 2114 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2115 (ohci->pri_req_max << 8); 2116 2117 default: 2118 WARN_ON(1); 2119 return 0; 2120 } 2121 } 2122 2123 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2124 { 2125 struct fw_ohci *ohci = fw_ohci(card); 2126 unsigned long flags; 2127 2128 switch (csr_offset) { 2129 case CSR_STATE_CLEAR: 2130 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2131 reg_write(ohci, OHCI1394_LinkControlClear, 2132 OHCI1394_LinkControl_cycleMaster); 2133 flush_writes(ohci); 2134 } 2135 if (value & CSR_STATE_BIT_ABDICATE) 2136 ohci->csr_state_setclear_abdicate = false; 2137 break; 2138 2139 case CSR_STATE_SET: 2140 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2141 reg_write(ohci, OHCI1394_LinkControlSet, 2142 OHCI1394_LinkControl_cycleMaster); 2143 flush_writes(ohci); 2144 } 2145 if (value & CSR_STATE_BIT_ABDICATE) 2146 ohci->csr_state_setclear_abdicate = true; 2147 break; 2148 2149 case CSR_NODE_IDS: 2150 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2151 flush_writes(ohci); 2152 break; 2153 2154 case CSR_CYCLE_TIME: 2155 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2156 reg_write(ohci, OHCI1394_IntEventSet, 2157 OHCI1394_cycleInconsistent); 2158 flush_writes(ohci); 2159 break; 2160 2161 case CSR_BUS_TIME: 2162 spin_lock_irqsave(&ohci->lock, flags); 2163 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); 2164 spin_unlock_irqrestore(&ohci->lock, flags); 2165 break; 2166 2167 case CSR_BUSY_TIMEOUT: 2168 value = (value & 0xf) | ((value & 0xf) << 4) | 2169 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2170 reg_write(ohci, OHCI1394_ATRetries, value); 2171 flush_writes(ohci); 2172 break; 2173 2174 case CSR_PRIORITY_BUDGET: 2175 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2176 flush_writes(ohci); 2177 break; 2178 2179 default: 2180 WARN_ON(1); 2181 break; 2182 } 2183 } 2184 2185 static void copy_iso_headers(struct iso_context *ctx, void *p) 2186 { 2187 int i = ctx->header_length; 2188 2189 if (i + ctx->base.header_size > PAGE_SIZE) 2190 return; 2191 2192 /* 2193 * The iso header is byteswapped to little endian by 2194 * the controller, but the remaining header quadlets 2195 * are big endian. We want to present all the headers 2196 * as big endian, so we have to swap the first quadlet. 2197 */ 2198 if (ctx->base.header_size > 0) 2199 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); 2200 if (ctx->base.header_size > 4) 2201 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); 2202 if (ctx->base.header_size > 8) 2203 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); 2204 ctx->header_length += ctx->base.header_size; 2205 } 2206 2207 static int handle_ir_packet_per_buffer(struct context *context, 2208 struct descriptor *d, 2209 struct descriptor *last) 2210 { 2211 struct iso_context *ctx = 2212 container_of(context, struct iso_context, context); 2213 struct descriptor *pd; 2214 __le32 *ir_header; 2215 void *p; 2216 2217 for (pd = d; pd <= last; pd++) 2218 if (pd->transfer_status) 2219 break; 2220 if (pd > last) 2221 /* Descriptor(s) not done yet, stop iteration */ 2222 return 0; 2223 2224 p = last + 1; 2225 copy_iso_headers(ctx, p); 2226 2227 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2228 ir_header = (__le32 *) p; 2229 ctx->base.callback.sc(&ctx->base, 2230 le32_to_cpu(ir_header[0]) & 0xffff, 2231 ctx->header_length, ctx->header, 2232 ctx->base.callback_data); 2233 ctx->header_length = 0; 2234 } 2235 2236 return 1; 2237 } 2238 2239 /* d == last because each descriptor block is only a single descriptor. */ 2240 static int handle_ir_buffer_fill(struct context *context, 2241 struct descriptor *d, 2242 struct descriptor *last) 2243 { 2244 struct iso_context *ctx = 2245 container_of(context, struct iso_context, context); 2246 2247 if (!last->transfer_status) 2248 /* Descriptor(s) not done yet, stop iteration */ 2249 return 0; 2250 2251 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) 2252 ctx->base.callback.mc(&ctx->base, 2253 le32_to_cpu(last->data_address) + 2254 le16_to_cpu(last->req_count) - 2255 le16_to_cpu(last->res_count), 2256 ctx->base.callback_data); 2257 2258 return 1; 2259 } 2260 2261 static int handle_it_packet(struct context *context, 2262 struct descriptor *d, 2263 struct descriptor *last) 2264 { 2265 struct iso_context *ctx = 2266 container_of(context, struct iso_context, context); 2267 int i; 2268 struct descriptor *pd; 2269 2270 for (pd = d; pd <= last; pd++) 2271 if (pd->transfer_status) 2272 break; 2273 if (pd > last) 2274 /* Descriptor(s) not done yet, stop iteration */ 2275 return 0; 2276 2277 i = ctx->header_length; 2278 if (i + 4 < PAGE_SIZE) { 2279 /* Present this value as big-endian to match the receive code */ 2280 *(__be32 *)(ctx->header + i) = cpu_to_be32( 2281 ((u32)le16_to_cpu(pd->transfer_status) << 16) | 2282 le16_to_cpu(pd->res_count)); 2283 ctx->header_length += 4; 2284 } 2285 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2286 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), 2287 ctx->header_length, ctx->header, 2288 ctx->base.callback_data); 2289 ctx->header_length = 0; 2290 } 2291 return 1; 2292 } 2293 2294 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2295 { 2296 u32 hi = channels >> 32, lo = channels; 2297 2298 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2299 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2300 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2301 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2302 mmiowb(); 2303 ohci->mc_channels = channels; 2304 } 2305 2306 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2307 int type, int channel, size_t header_size) 2308 { 2309 struct fw_ohci *ohci = fw_ohci(card); 2310 struct iso_context *uninitialized_var(ctx); 2311 descriptor_callback_t uninitialized_var(callback); 2312 u64 *uninitialized_var(channels); 2313 u32 *uninitialized_var(mask), uninitialized_var(regs); 2314 unsigned long flags; 2315 int index, ret = -EBUSY; 2316 2317 spin_lock_irqsave(&ohci->lock, flags); 2318 2319 switch (type) { 2320 case FW_ISO_CONTEXT_TRANSMIT: 2321 mask = &ohci->it_context_mask; 2322 callback = handle_it_packet; 2323 index = ffs(*mask) - 1; 2324 if (index >= 0) { 2325 *mask &= ~(1 << index); 2326 regs = OHCI1394_IsoXmitContextBase(index); 2327 ctx = &ohci->it_context_list[index]; 2328 } 2329 break; 2330 2331 case FW_ISO_CONTEXT_RECEIVE: 2332 channels = &ohci->ir_context_channels; 2333 mask = &ohci->ir_context_mask; 2334 callback = handle_ir_packet_per_buffer; 2335 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2336 if (index >= 0) { 2337 *channels &= ~(1ULL << channel); 2338 *mask &= ~(1 << index); 2339 regs = OHCI1394_IsoRcvContextBase(index); 2340 ctx = &ohci->ir_context_list[index]; 2341 } 2342 break; 2343 2344 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2345 mask = &ohci->ir_context_mask; 2346 callback = handle_ir_buffer_fill; 2347 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2348 if (index >= 0) { 2349 ohci->mc_allocated = true; 2350 *mask &= ~(1 << index); 2351 regs = OHCI1394_IsoRcvContextBase(index); 2352 ctx = &ohci->ir_context_list[index]; 2353 } 2354 break; 2355 2356 default: 2357 index = -1; 2358 ret = -ENOSYS; 2359 } 2360 2361 spin_unlock_irqrestore(&ohci->lock, flags); 2362 2363 if (index < 0) 2364 return ERR_PTR(ret); 2365 2366 memset(ctx, 0, sizeof(*ctx)); 2367 ctx->header_length = 0; 2368 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2369 if (ctx->header == NULL) { 2370 ret = -ENOMEM; 2371 goto out; 2372 } 2373 ret = context_init(&ctx->context, ohci, regs, callback); 2374 if (ret < 0) 2375 goto out_with_header; 2376 2377 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) 2378 set_multichannel_mask(ohci, 0); 2379 2380 return &ctx->base; 2381 2382 out_with_header: 2383 free_page((unsigned long)ctx->header); 2384 out: 2385 spin_lock_irqsave(&ohci->lock, flags); 2386 2387 switch (type) { 2388 case FW_ISO_CONTEXT_RECEIVE: 2389 *channels |= 1ULL << channel; 2390 break; 2391 2392 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2393 ohci->mc_allocated = false; 2394 break; 2395 } 2396 *mask |= 1 << index; 2397 2398 spin_unlock_irqrestore(&ohci->lock, flags); 2399 2400 return ERR_PTR(ret); 2401 } 2402 2403 static int ohci_start_iso(struct fw_iso_context *base, 2404 s32 cycle, u32 sync, u32 tags) 2405 { 2406 struct iso_context *ctx = container_of(base, struct iso_context, base); 2407 struct fw_ohci *ohci = ctx->context.ohci; 2408 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 2409 int index; 2410 2411 switch (ctx->base.type) { 2412 case FW_ISO_CONTEXT_TRANSMIT: 2413 index = ctx - ohci->it_context_list; 2414 match = 0; 2415 if (cycle >= 0) 2416 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 2417 (cycle & 0x7fff) << 16; 2418 2419 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 2420 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 2421 context_run(&ctx->context, match); 2422 break; 2423 2424 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2425 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 2426 /* fall through */ 2427 case FW_ISO_CONTEXT_RECEIVE: 2428 index = ctx - ohci->ir_context_list; 2429 match = (tags << 28) | (sync << 8) | ctx->base.channel; 2430 if (cycle >= 0) { 2431 match |= (cycle & 0x07fff) << 12; 2432 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 2433 } 2434 2435 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 2436 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 2437 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 2438 context_run(&ctx->context, control); 2439 break; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int ohci_stop_iso(struct fw_iso_context *base) 2446 { 2447 struct fw_ohci *ohci = fw_ohci(base->card); 2448 struct iso_context *ctx = container_of(base, struct iso_context, base); 2449 int index; 2450 2451 switch (ctx->base.type) { 2452 case FW_ISO_CONTEXT_TRANSMIT: 2453 index = ctx - ohci->it_context_list; 2454 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 2455 break; 2456 2457 case FW_ISO_CONTEXT_RECEIVE: 2458 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2459 index = ctx - ohci->ir_context_list; 2460 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 2461 break; 2462 } 2463 flush_writes(ohci); 2464 context_stop(&ctx->context); 2465 2466 return 0; 2467 } 2468 2469 static void ohci_free_iso_context(struct fw_iso_context *base) 2470 { 2471 struct fw_ohci *ohci = fw_ohci(base->card); 2472 struct iso_context *ctx = container_of(base, struct iso_context, base); 2473 unsigned long flags; 2474 int index; 2475 2476 ohci_stop_iso(base); 2477 context_release(&ctx->context); 2478 free_page((unsigned long)ctx->header); 2479 2480 spin_lock_irqsave(&ohci->lock, flags); 2481 2482 switch (base->type) { 2483 case FW_ISO_CONTEXT_TRANSMIT: 2484 index = ctx - ohci->it_context_list; 2485 ohci->it_context_mask |= 1 << index; 2486 break; 2487 2488 case FW_ISO_CONTEXT_RECEIVE: 2489 index = ctx - ohci->ir_context_list; 2490 ohci->ir_context_mask |= 1 << index; 2491 ohci->ir_context_channels |= 1ULL << base->channel; 2492 break; 2493 2494 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2495 index = ctx - ohci->ir_context_list; 2496 ohci->ir_context_mask |= 1 << index; 2497 ohci->ir_context_channels |= ohci->mc_channels; 2498 ohci->mc_channels = 0; 2499 ohci->mc_allocated = false; 2500 break; 2501 } 2502 2503 spin_unlock_irqrestore(&ohci->lock, flags); 2504 } 2505 2506 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 2507 { 2508 struct fw_ohci *ohci = fw_ohci(base->card); 2509 unsigned long flags; 2510 int ret; 2511 2512 switch (base->type) { 2513 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2514 2515 spin_lock_irqsave(&ohci->lock, flags); 2516 2517 /* Don't allow multichannel to grab other contexts' channels. */ 2518 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 2519 *channels = ohci->ir_context_channels; 2520 ret = -EBUSY; 2521 } else { 2522 set_multichannel_mask(ohci, *channels); 2523 ret = 0; 2524 } 2525 2526 spin_unlock_irqrestore(&ohci->lock, flags); 2527 2528 break; 2529 default: 2530 ret = -EINVAL; 2531 } 2532 2533 return ret; 2534 } 2535 2536 static int queue_iso_transmit(struct iso_context *ctx, 2537 struct fw_iso_packet *packet, 2538 struct fw_iso_buffer *buffer, 2539 unsigned long payload) 2540 { 2541 struct descriptor *d, *last, *pd; 2542 struct fw_iso_packet *p; 2543 __le32 *header; 2544 dma_addr_t d_bus, page_bus; 2545 u32 z, header_z, payload_z, irq; 2546 u32 payload_index, payload_end_index, next_page_index; 2547 int page, end_page, i, length, offset; 2548 2549 p = packet; 2550 payload_index = payload; 2551 2552 if (p->skip) 2553 z = 1; 2554 else 2555 z = 2; 2556 if (p->header_length > 0) 2557 z++; 2558 2559 /* Determine the first page the payload isn't contained in. */ 2560 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 2561 if (p->payload_length > 0) 2562 payload_z = end_page - (payload_index >> PAGE_SHIFT); 2563 else 2564 payload_z = 0; 2565 2566 z += payload_z; 2567 2568 /* Get header size in number of descriptors. */ 2569 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 2570 2571 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 2572 if (d == NULL) 2573 return -ENOMEM; 2574 2575 if (!p->skip) { 2576 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 2577 d[0].req_count = cpu_to_le16(8); 2578 /* 2579 * Link the skip address to this descriptor itself. This causes 2580 * a context to skip a cycle whenever lost cycles or FIFO 2581 * overruns occur, without dropping the data. The application 2582 * should then decide whether this is an error condition or not. 2583 * FIXME: Make the context's cycle-lost behaviour configurable? 2584 */ 2585 d[0].branch_address = cpu_to_le32(d_bus | z); 2586 2587 header = (__le32 *) &d[1]; 2588 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 2589 IT_HEADER_TAG(p->tag) | 2590 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 2591 IT_HEADER_CHANNEL(ctx->base.channel) | 2592 IT_HEADER_SPEED(ctx->base.speed)); 2593 header[1] = 2594 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 2595 p->payload_length)); 2596 } 2597 2598 if (p->header_length > 0) { 2599 d[2].req_count = cpu_to_le16(p->header_length); 2600 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 2601 memcpy(&d[z], p->header, p->header_length); 2602 } 2603 2604 pd = d + z - payload_z; 2605 payload_end_index = payload_index + p->payload_length; 2606 for (i = 0; i < payload_z; i++) { 2607 page = payload_index >> PAGE_SHIFT; 2608 offset = payload_index & ~PAGE_MASK; 2609 next_page_index = (page + 1) << PAGE_SHIFT; 2610 length = 2611 min(next_page_index, payload_end_index) - payload_index; 2612 pd[i].req_count = cpu_to_le16(length); 2613 2614 page_bus = page_private(buffer->pages[page]); 2615 pd[i].data_address = cpu_to_le32(page_bus + offset); 2616 2617 payload_index += length; 2618 } 2619 2620 if (p->interrupt) 2621 irq = DESCRIPTOR_IRQ_ALWAYS; 2622 else 2623 irq = DESCRIPTOR_NO_IRQ; 2624 2625 last = z == 2 ? d : d + z - 1; 2626 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 2627 DESCRIPTOR_STATUS | 2628 DESCRIPTOR_BRANCH_ALWAYS | 2629 irq); 2630 2631 context_append(&ctx->context, d, z, header_z); 2632 2633 return 0; 2634 } 2635 2636 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 2637 struct fw_iso_packet *packet, 2638 struct fw_iso_buffer *buffer, 2639 unsigned long payload) 2640 { 2641 struct descriptor *d, *pd; 2642 dma_addr_t d_bus, page_bus; 2643 u32 z, header_z, rest; 2644 int i, j, length; 2645 int page, offset, packet_count, header_size, payload_per_buffer; 2646 2647 /* 2648 * The OHCI controller puts the isochronous header and trailer in the 2649 * buffer, so we need at least 8 bytes. 2650 */ 2651 packet_count = packet->header_length / ctx->base.header_size; 2652 header_size = max(ctx->base.header_size, (size_t)8); 2653 2654 /* Get header size in number of descriptors. */ 2655 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 2656 page = payload >> PAGE_SHIFT; 2657 offset = payload & ~PAGE_MASK; 2658 payload_per_buffer = packet->payload_length / packet_count; 2659 2660 for (i = 0; i < packet_count; i++) { 2661 /* d points to the header descriptor */ 2662 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 2663 d = context_get_descriptors(&ctx->context, 2664 z + header_z, &d_bus); 2665 if (d == NULL) 2666 return -ENOMEM; 2667 2668 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 2669 DESCRIPTOR_INPUT_MORE); 2670 if (packet->skip && i == 0) 2671 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 2672 d->req_count = cpu_to_le16(header_size); 2673 d->res_count = d->req_count; 2674 d->transfer_status = 0; 2675 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 2676 2677 rest = payload_per_buffer; 2678 pd = d; 2679 for (j = 1; j < z; j++) { 2680 pd++; 2681 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 2682 DESCRIPTOR_INPUT_MORE); 2683 2684 if (offset + rest < PAGE_SIZE) 2685 length = rest; 2686 else 2687 length = PAGE_SIZE - offset; 2688 pd->req_count = cpu_to_le16(length); 2689 pd->res_count = pd->req_count; 2690 pd->transfer_status = 0; 2691 2692 page_bus = page_private(buffer->pages[page]); 2693 pd->data_address = cpu_to_le32(page_bus + offset); 2694 2695 offset = (offset + length) & ~PAGE_MASK; 2696 rest -= length; 2697 if (offset == 0) 2698 page++; 2699 } 2700 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 2701 DESCRIPTOR_INPUT_LAST | 2702 DESCRIPTOR_BRANCH_ALWAYS); 2703 if (packet->interrupt && i == packet_count - 1) 2704 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 2705 2706 context_append(&ctx->context, d, z, header_z); 2707 } 2708 2709 return 0; 2710 } 2711 2712 static int queue_iso_buffer_fill(struct iso_context *ctx, 2713 struct fw_iso_packet *packet, 2714 struct fw_iso_buffer *buffer, 2715 unsigned long payload) 2716 { 2717 struct descriptor *d; 2718 dma_addr_t d_bus, page_bus; 2719 int page, offset, rest, z, i, length; 2720 2721 page = payload >> PAGE_SHIFT; 2722 offset = payload & ~PAGE_MASK; 2723 rest = packet->payload_length; 2724 2725 /* We need one descriptor for each page in the buffer. */ 2726 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 2727 2728 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 2729 return -EFAULT; 2730 2731 for (i = 0; i < z; i++) { 2732 d = context_get_descriptors(&ctx->context, 1, &d_bus); 2733 if (d == NULL) 2734 return -ENOMEM; 2735 2736 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 2737 DESCRIPTOR_BRANCH_ALWAYS); 2738 if (packet->skip && i == 0) 2739 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 2740 if (packet->interrupt && i == z - 1) 2741 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 2742 2743 if (offset + rest < PAGE_SIZE) 2744 length = rest; 2745 else 2746 length = PAGE_SIZE - offset; 2747 d->req_count = cpu_to_le16(length); 2748 d->res_count = d->req_count; 2749 d->transfer_status = 0; 2750 2751 page_bus = page_private(buffer->pages[page]); 2752 d->data_address = cpu_to_le32(page_bus + offset); 2753 2754 rest -= length; 2755 offset = 0; 2756 page++; 2757 2758 context_append(&ctx->context, d, 1, 0); 2759 } 2760 2761 return 0; 2762 } 2763 2764 static int ohci_queue_iso(struct fw_iso_context *base, 2765 struct fw_iso_packet *packet, 2766 struct fw_iso_buffer *buffer, 2767 unsigned long payload) 2768 { 2769 struct iso_context *ctx = container_of(base, struct iso_context, base); 2770 unsigned long flags; 2771 int ret = -ENOSYS; 2772 2773 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 2774 switch (base->type) { 2775 case FW_ISO_CONTEXT_TRANSMIT: 2776 ret = queue_iso_transmit(ctx, packet, buffer, payload); 2777 break; 2778 case FW_ISO_CONTEXT_RECEIVE: 2779 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 2780 break; 2781 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2782 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 2783 break; 2784 } 2785 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 2786 2787 return ret; 2788 } 2789 2790 static const struct fw_card_driver ohci_driver = { 2791 .enable = ohci_enable, 2792 .read_phy_reg = ohci_read_phy_reg, 2793 .update_phy_reg = ohci_update_phy_reg, 2794 .set_config_rom = ohci_set_config_rom, 2795 .send_request = ohci_send_request, 2796 .send_response = ohci_send_response, 2797 .cancel_packet = ohci_cancel_packet, 2798 .enable_phys_dma = ohci_enable_phys_dma, 2799 .read_csr = ohci_read_csr, 2800 .write_csr = ohci_write_csr, 2801 2802 .allocate_iso_context = ohci_allocate_iso_context, 2803 .free_iso_context = ohci_free_iso_context, 2804 .set_iso_channels = ohci_set_iso_channels, 2805 .queue_iso = ohci_queue_iso, 2806 .start_iso = ohci_start_iso, 2807 .stop_iso = ohci_stop_iso, 2808 }; 2809 2810 #ifdef CONFIG_PPC_PMAC 2811 static void pmac_ohci_on(struct pci_dev *dev) 2812 { 2813 if (machine_is(powermac)) { 2814 struct device_node *ofn = pci_device_to_OF_node(dev); 2815 2816 if (ofn) { 2817 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 2818 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 2819 } 2820 } 2821 } 2822 2823 static void pmac_ohci_off(struct pci_dev *dev) 2824 { 2825 if (machine_is(powermac)) { 2826 struct device_node *ofn = pci_device_to_OF_node(dev); 2827 2828 if (ofn) { 2829 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 2830 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 2831 } 2832 } 2833 } 2834 #else 2835 static inline void pmac_ohci_on(struct pci_dev *dev) {} 2836 static inline void pmac_ohci_off(struct pci_dev *dev) {} 2837 #endif /* CONFIG_PPC_PMAC */ 2838 2839 static int __devinit pci_probe(struct pci_dev *dev, 2840 const struct pci_device_id *ent) 2841 { 2842 struct fw_ohci *ohci; 2843 u32 bus_options, max_receive, link_speed, version; 2844 u64 guid; 2845 int i, err, n_ir, n_it; 2846 size_t size; 2847 2848 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 2849 if (ohci == NULL) { 2850 err = -ENOMEM; 2851 goto fail; 2852 } 2853 2854 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 2855 2856 pmac_ohci_on(dev); 2857 2858 err = pci_enable_device(dev); 2859 if (err) { 2860 fw_error("Failed to enable OHCI hardware\n"); 2861 goto fail_free; 2862 } 2863 2864 pci_set_master(dev); 2865 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 2866 pci_set_drvdata(dev, ohci); 2867 2868 spin_lock_init(&ohci->lock); 2869 mutex_init(&ohci->phy_reg_mutex); 2870 2871 tasklet_init(&ohci->bus_reset_tasklet, 2872 bus_reset_tasklet, (unsigned long)ohci); 2873 2874 err = pci_request_region(dev, 0, ohci_driver_name); 2875 if (err) { 2876 fw_error("MMIO resource unavailable\n"); 2877 goto fail_disable; 2878 } 2879 2880 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 2881 if (ohci->registers == NULL) { 2882 fw_error("Failed to remap registers\n"); 2883 err = -ENXIO; 2884 goto fail_iomem; 2885 } 2886 2887 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 2888 if (ohci_quirks[i].vendor == dev->vendor && 2889 (ohci_quirks[i].device == dev->device || 2890 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) { 2891 ohci->quirks = ohci_quirks[i].flags; 2892 break; 2893 } 2894 if (param_quirks) 2895 ohci->quirks = param_quirks; 2896 2897 ar_context_init(&ohci->ar_request_ctx, ohci, 2898 OHCI1394_AsReqRcvContextControlSet); 2899 2900 ar_context_init(&ohci->ar_response_ctx, ohci, 2901 OHCI1394_AsRspRcvContextControlSet); 2902 2903 context_init(&ohci->at_request_ctx, ohci, 2904 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 2905 2906 context_init(&ohci->at_response_ctx, ohci, 2907 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 2908 2909 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 2910 ohci->ir_context_channels = ~0ULL; 2911 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 2912 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 2913 n_ir = hweight32(ohci->ir_context_mask); 2914 size = sizeof(struct iso_context) * n_ir; 2915 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 2916 2917 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 2918 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 2919 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 2920 n_it = hweight32(ohci->it_context_mask); 2921 size = sizeof(struct iso_context) * n_it; 2922 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 2923 2924 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 2925 err = -ENOMEM; 2926 goto fail_contexts; 2927 } 2928 2929 /* self-id dma buffer allocation */ 2930 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, 2931 SELF_ID_BUF_SIZE, 2932 &ohci->self_id_bus, 2933 GFP_KERNEL); 2934 if (ohci->self_id_cpu == NULL) { 2935 err = -ENOMEM; 2936 goto fail_contexts; 2937 } 2938 2939 bus_options = reg_read(ohci, OHCI1394_BusOptions); 2940 max_receive = (bus_options >> 12) & 0xf; 2941 link_speed = bus_options & 0x7; 2942 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 2943 reg_read(ohci, OHCI1394_GUIDLo); 2944 2945 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 2946 if (err) 2947 goto fail_self_id; 2948 2949 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2950 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " 2951 "%d IR + %d IT contexts, quirks 0x%x\n", 2952 dev_name(&dev->dev), version >> 16, version & 0xff, 2953 n_ir, n_it, ohci->quirks); 2954 2955 return 0; 2956 2957 fail_self_id: 2958 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, 2959 ohci->self_id_cpu, ohci->self_id_bus); 2960 fail_contexts: 2961 kfree(ohci->ir_context_list); 2962 kfree(ohci->it_context_list); 2963 context_release(&ohci->at_response_ctx); 2964 context_release(&ohci->at_request_ctx); 2965 ar_context_release(&ohci->ar_response_ctx); 2966 ar_context_release(&ohci->ar_request_ctx); 2967 pci_iounmap(dev, ohci->registers); 2968 fail_iomem: 2969 pci_release_region(dev, 0); 2970 fail_disable: 2971 pci_disable_device(dev); 2972 fail_free: 2973 kfree(&ohci->card); 2974 pmac_ohci_off(dev); 2975 fail: 2976 if (err == -ENOMEM) 2977 fw_error("Out of memory\n"); 2978 2979 return err; 2980 } 2981 2982 static void pci_remove(struct pci_dev *dev) 2983 { 2984 struct fw_ohci *ohci; 2985 2986 ohci = pci_get_drvdata(dev); 2987 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2988 flush_writes(ohci); 2989 fw_core_remove_card(&ohci->card); 2990 2991 /* 2992 * FIXME: Fail all pending packets here, now that the upper 2993 * layers can't queue any more. 2994 */ 2995 2996 software_reset(ohci); 2997 free_irq(dev->irq, ohci); 2998 2999 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3000 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3001 ohci->next_config_rom, ohci->next_config_rom_bus); 3002 if (ohci->config_rom) 3003 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3004 ohci->config_rom, ohci->config_rom_bus); 3005 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, 3006 ohci->self_id_cpu, ohci->self_id_bus); 3007 ar_context_release(&ohci->ar_request_ctx); 3008 ar_context_release(&ohci->ar_response_ctx); 3009 context_release(&ohci->at_request_ctx); 3010 context_release(&ohci->at_response_ctx); 3011 kfree(ohci->it_context_list); 3012 kfree(ohci->ir_context_list); 3013 pci_disable_msi(dev); 3014 pci_iounmap(dev, ohci->registers); 3015 pci_release_region(dev, 0); 3016 pci_disable_device(dev); 3017 kfree(&ohci->card); 3018 pmac_ohci_off(dev); 3019 3020 fw_notify("Removed fw-ohci device.\n"); 3021 } 3022 3023 #ifdef CONFIG_PM 3024 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3025 { 3026 struct fw_ohci *ohci = pci_get_drvdata(dev); 3027 int err; 3028 3029 software_reset(ohci); 3030 free_irq(dev->irq, ohci); 3031 pci_disable_msi(dev); 3032 err = pci_save_state(dev); 3033 if (err) { 3034 fw_error("pci_save_state failed\n"); 3035 return err; 3036 } 3037 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3038 if (err) 3039 fw_error("pci_set_power_state failed with %d\n", err); 3040 pmac_ohci_off(dev); 3041 3042 return 0; 3043 } 3044 3045 static int pci_resume(struct pci_dev *dev) 3046 { 3047 struct fw_ohci *ohci = pci_get_drvdata(dev); 3048 int err; 3049 3050 pmac_ohci_on(dev); 3051 pci_set_power_state(dev, PCI_D0); 3052 pci_restore_state(dev); 3053 err = pci_enable_device(dev); 3054 if (err) { 3055 fw_error("pci_enable_device failed\n"); 3056 return err; 3057 } 3058 3059 return ohci_enable(&ohci->card, NULL, 0); 3060 } 3061 #endif 3062 3063 static const struct pci_device_id pci_table[] = { 3064 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3065 { } 3066 }; 3067 3068 MODULE_DEVICE_TABLE(pci, pci_table); 3069 3070 static struct pci_driver fw_ohci_pci_driver = { 3071 .name = ohci_driver_name, 3072 .id_table = pci_table, 3073 .probe = pci_probe, 3074 .remove = pci_remove, 3075 #ifdef CONFIG_PM 3076 .resume = pci_resume, 3077 .suspend = pci_suspend, 3078 #endif 3079 }; 3080 3081 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3082 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3083 MODULE_LICENSE("GPL"); 3084 3085 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3086 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE 3087 MODULE_ALIAS("ohci1394"); 3088 #endif 3089 3090 static int __init fw_ohci_init(void) 3091 { 3092 return pci_register_driver(&fw_ohci_pci_driver); 3093 } 3094 3095 static void __exit fw_ohci_cleanup(void) 3096 { 3097 pci_unregister_driver(&fw_ohci_pci_driver); 3098 } 3099 3100 module_init(fw_ohci_init); 3101 module_exit(fw_ohci_cleanup); 3102