1 /* 2 * AMD64 class Memory Controller kernel module 3 * 4 * Copyright (c) 2009 SoftwareBitMaker. 5 * Copyright (c) 2009 Advanced Micro Devices, Inc. 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 * 10 * Originally Written by Thayne Harbaugh 11 * 12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 13 * - K8 CPU Revision D and greater support 14 * 15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: 16 * - Module largely rewritten, with new (and hopefully correct) 17 * code for dealing with node and chip select interleaving, 18 * various code cleanup, and bug fixes 19 * - Added support for memory hoisting using DRAM hole address 20 * register 21 * 22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 23 * -K8 Rev (1207) revision support added, required Revision 24 * specific mini-driver code to support Rev F as well as 25 * prior revisions 26 * 27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 28 * -Family 10h revision support added. New PCI Device IDs, 29 * indicating new changes. Actual registers modified 30 * were slight, less than the Rev E to Rev F transition 31 * but changing the PCI Device ID was the proper thing to 32 * do, as it provides for almost automactic family 33 * detection. The mods to Rev F required more family 34 * information detection. 35 * 36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>: 37 * - misc fixes and code cleanups 38 * 39 * This module is based on the following documents 40 * (available from http://www.amd.com/): 41 * 42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD 43 * Opteron Processors 44 * AMD publication #: 26094 45 *` Revision: 3.26 46 * 47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh 48 * Processors 49 * AMD publication #: 32559 50 * Revision: 3.00 51 * Issue Date: May 2006 52 * 53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h 54 * Processors 55 * AMD publication #: 31116 56 * Revision: 3.00 57 * Issue Date: September 07, 2007 58 * 59 * Sections in the first 2 documents are no longer in sync with each other. 60 * The Family 10h BKDG was totally re-written from scratch with a new 61 * presentation model. 62 * Therefore, comments that refer to a Document section might be off. 63 */ 64 65 #include <linux/module.h> 66 #include <linux/ctype.h> 67 #include <linux/init.h> 68 #include <linux/pci.h> 69 #include <linux/pci_ids.h> 70 #include <linux/slab.h> 71 #include <linux/mmzone.h> 72 #include <linux/edac.h> 73 #include <asm/msr.h> 74 #include "edac_core.h" 75 #include "mce_amd.h" 76 77 #define amd64_debug(fmt, arg...) \ 78 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) 79 80 #define amd64_info(fmt, arg...) \ 81 edac_printk(KERN_INFO, "amd64", fmt, ##arg) 82 83 #define amd64_notice(fmt, arg...) \ 84 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) 85 86 #define amd64_warn(fmt, arg...) \ 87 edac_printk(KERN_WARNING, "amd64", fmt, ##arg) 88 89 #define amd64_err(fmt, arg...) \ 90 edac_printk(KERN_ERR, "amd64", fmt, ##arg) 91 92 #define amd64_mc_warn(mci, fmt, arg...) \ 93 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) 94 95 #define amd64_mc_err(mci, fmt, arg...) \ 96 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) 97 98 /* 99 * Throughout the comments in this code, the following terms are used: 100 * 101 * SysAddr, DramAddr, and InputAddr 102 * 103 * These terms come directly from the amd64 documentation 104 * (AMD publication #26094). They are defined as follows: 105 * 106 * SysAddr: 107 * This is a physical address generated by a CPU core or a device 108 * doing DMA. If generated by a CPU core, a SysAddr is the result of 109 * a virtual to physical address translation by the CPU core's address 110 * translation mechanism (MMU). 111 * 112 * DramAddr: 113 * A DramAddr is derived from a SysAddr by subtracting an offset that 114 * depends on which node the SysAddr maps to and whether the SysAddr 115 * is within a range affected by memory hoisting. The DRAM Base 116 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 117 * determine which node a SysAddr maps to. 118 * 119 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 120 * is within the range of addresses specified by this register, then 121 * a value x from the DHAR is subtracted from the SysAddr to produce a 122 * DramAddr. Here, x represents the base address for the node that 123 * the SysAddr maps to plus an offset due to memory hoisting. See 124 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and 125 * sys_addr_to_dram_addr() below for more information. 126 * 127 * If the SysAddr is not affected by the DHAR then a value y is 128 * subtracted from the SysAddr to produce a DramAddr. Here, y is the 129 * base address for the node that the SysAddr maps to. See section 130 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more 131 * information. 132 * 133 * InputAddr: 134 * A DramAddr is translated to an InputAddr before being passed to the 135 * memory controller for the node that the DramAddr is associated 136 * with. The memory controller then maps the InputAddr to a csrow. 137 * If node interleaving is not in use, then the InputAddr has the same 138 * value as the DramAddr. Otherwise, the InputAddr is produced by 139 * discarding the bits used for node interleaving from the DramAddr. 140 * See section 3.4.4 for more information. 141 * 142 * The memory controller for a given node uses its DRAM CS Base and 143 * DRAM CS Mask registers to map an InputAddr to a csrow. See 144 * sections 3.5.4 and 3.5.5 for more information. 145 */ 146 147 #define EDAC_AMD64_VERSION "3.4.0" 148 #define EDAC_MOD_STR "amd64_edac" 149 150 /* Extended Model from CPUID, for CPU Revision numbers */ 151 #define K8_REV_D 1 152 #define K8_REV_E 2 153 #define K8_REV_F 4 154 155 /* Hardware limit on ChipSelect rows per MC and processors per system */ 156 #define NUM_CHIPSELECTS 8 157 #define DRAM_RANGES 8 158 159 #define ON true 160 #define OFF false 161 162 /* 163 * Create a contiguous bitmask starting at bit position @lo and ending at 164 * position @hi. For example 165 * 166 * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000. 167 */ 168 #define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) 169 170 /* 171 * PCI-defined configuration space registers 172 */ 173 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 174 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 175 176 177 /* 178 * Function 1 - Address Map 179 */ 180 #define DRAM_BASE_LO 0x40 181 #define DRAM_LIMIT_LO 0x44 182 183 #define dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7)) 184 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) 185 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) 186 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) 187 188 #define DHAR 0xf0 189 #define dhar_valid(pvt) ((pvt)->dhar & BIT(0)) 190 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) 191 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) 192 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) 193 194 /* NOTE: Extra mask bit vs K8 */ 195 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) 196 197 #define DCT_CFG_SEL 0x10C 198 199 #define DRAM_BASE_HI 0x140 200 #define DRAM_LIMIT_HI 0x144 201 202 203 /* 204 * Function 2 - DRAM controller 205 */ 206 #define DCSB0 0x40 207 #define DCSB1 0x140 208 #define DCSB_CS_ENABLE BIT(0) 209 210 #define DCSM0 0x60 211 #define DCSM1 0x160 212 213 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) 214 215 #define DBAM0 0x80 216 #define DBAM1 0x180 217 218 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ 219 #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) 220 221 #define DBAM_MAX_VALUE 11 222 223 #define DCLR0 0x90 224 #define DCLR1 0x190 225 #define REVE_WIDTH_128 BIT(16) 226 #define WIDTH_128 BIT(11) 227 228 #define DCHR0 0x94 229 #define DCHR1 0x194 230 #define DDR3_MODE BIT(8) 231 232 #define DCT_SEL_LO 0x110 233 #define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800) 234 #define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3) 235 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) 236 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) 237 238 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) 239 240 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) 241 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) 242 243 #define SWAP_INTLV_REG 0x10c 244 245 #define DCT_SEL_HI 0x114 246 247 /* 248 * Function 3 - Misc Control 249 */ 250 #define NBCTL 0x40 251 252 #define NBCFG 0x44 253 #define NBCFG_CHIPKILL BIT(23) 254 #define NBCFG_ECC_ENABLE BIT(22) 255 256 /* F3x48: NBSL */ 257 #define F10_NBSL_EXT_ERR_ECC 0x8 258 #define NBSL_PP_OBS 0x2 259 260 #define SCRCTRL 0x58 261 262 #define F10_ONLINE_SPARE 0xB0 263 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) 264 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) 265 266 #define F10_NB_ARRAY_ADDR 0xB8 267 #define F10_NB_ARRAY_DRAM_ECC BIT(31) 268 269 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 270 #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) 271 272 #define F10_NB_ARRAY_DATA 0xBC 273 #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ 274 (BIT(((word) & 0xF) + 20) | \ 275 BIT(17) | bits) 276 #define SET_NB_DRAM_INJECTION_READ(word, bits) \ 277 (BIT(((word) & 0xF) + 20) | \ 278 BIT(16) | bits) 279 280 #define NBCAP 0xE8 281 #define NBCAP_CHIPKILL BIT(4) 282 #define NBCAP_SECDED BIT(3) 283 #define NBCAP_DCT_DUAL BIT(0) 284 285 #define EXT_NB_MCA_CFG 0x180 286 287 /* MSRs */ 288 #define MSR_MCGCTL_NBE BIT(4) 289 290 /* AMD sets the first MC device at device ID 0x18. */ 291 static inline u8 get_node_id(struct pci_dev *pdev) 292 { 293 return PCI_SLOT(pdev->devfn) - 0x18; 294 } 295 296 enum amd_families { 297 K8_CPUS = 0, 298 F10_CPUS, 299 F15_CPUS, 300 NUM_FAMILIES, 301 }; 302 303 /* Error injection control structure */ 304 struct error_injection { 305 u32 section; 306 u32 word; 307 u32 bit_map; 308 }; 309 310 /* low and high part of PCI config space regs */ 311 struct reg_pair { 312 u32 lo, hi; 313 }; 314 315 /* 316 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers 317 */ 318 struct dram_range { 319 struct reg_pair base; 320 struct reg_pair lim; 321 }; 322 323 /* A DCT chip selects collection */ 324 struct chip_select { 325 u32 csbases[NUM_CHIPSELECTS]; 326 u8 b_cnt; 327 328 u32 csmasks[NUM_CHIPSELECTS]; 329 u8 m_cnt; 330 }; 331 332 struct amd64_pvt { 333 struct low_ops *ops; 334 335 /* pci_device handles which we utilize */ 336 struct pci_dev *F1, *F2, *F3; 337 338 unsigned mc_node_id; /* MC index of this MC node */ 339 int ext_model; /* extended model value of this node */ 340 int channel_count; 341 342 /* Raw registers */ 343 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ 344 u32 dclr1; /* DRAM Configuration Low DCT1 reg */ 345 u32 dchr0; /* DRAM Configuration High DCT0 reg */ 346 u32 dchr1; /* DRAM Configuration High DCT1 reg */ 347 u32 nbcap; /* North Bridge Capabilities */ 348 u32 nbcfg; /* F10 North Bridge Configuration */ 349 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ 350 u32 dhar; /* DRAM Hoist reg */ 351 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ 352 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 353 354 /* one for each DCT */ 355 struct chip_select csels[2]; 356 357 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 358 struct dram_range ranges[DRAM_RANGES]; 359 360 u64 top_mem; /* top of memory below 4GB */ 361 u64 top_mem2; /* top of memory above 4GB */ 362 363 u32 dct_sel_lo; /* DRAM Controller Select Low */ 364 u32 dct_sel_hi; /* DRAM Controller Select High */ 365 u32 online_spare; /* On-Line spare Reg */ 366 367 /* x4 or x8 syndromes in use */ 368 u8 ecc_sym_sz; 369 370 /* place to store error injection parameters prior to issue */ 371 struct error_injection injection; 372 }; 373 374 static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i) 375 { 376 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; 377 378 if (boot_cpu_data.x86 == 0xf) 379 return addr; 380 381 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; 382 } 383 384 static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i) 385 { 386 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; 387 388 if (boot_cpu_data.x86 == 0xf) 389 return lim; 390 391 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; 392 } 393 394 static inline u16 extract_syndrome(u64 status) 395 { 396 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); 397 } 398 399 /* 400 * per-node ECC settings descriptor 401 */ 402 struct ecc_settings { 403 u32 old_nbctl; 404 bool nbctl_valid; 405 406 struct flags { 407 unsigned long nb_mce_enable:1; 408 unsigned long nb_ecc_prev:1; 409 } flags; 410 }; 411 412 #ifdef CONFIG_EDAC_DEBUG 413 #define NUM_DBG_ATTRS 5 414 #else 415 #define NUM_DBG_ATTRS 0 416 #endif 417 418 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION 419 #define NUM_INJ_ATTRS 5 420 #else 421 #define NUM_INJ_ATTRS 0 422 #endif 423 424 extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS], 425 amd64_inj_attrs[NUM_INJ_ATTRS]; 426 427 /* 428 * Each of the PCI Device IDs types have their own set of hardware accessor 429 * functions and per device encoding/decoding logic. 430 */ 431 struct low_ops { 432 int (*early_channel_count) (struct amd64_pvt *pvt); 433 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, 434 u16 syndrome); 435 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode); 436 int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset, 437 u32 *val, const char *func); 438 }; 439 440 struct amd64_family_type { 441 const char *ctl_name; 442 u16 f1_id, f3_id; 443 struct low_ops ops; 444 }; 445 446 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, 447 u32 val, const char *func); 448 449 #define amd64_read_pci_cfg(pdev, offset, val) \ 450 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) 451 452 #define amd64_write_pci_cfg(pdev, offset, val) \ 453 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) 454 455 #define amd64_read_dct_pci_cfg(pvt, offset, val) \ 456 pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__) 457 458 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 459 u64 *hole_offset, u64 *hole_size); 460