1 /* 2 * AMD64 class Memory Controller kernel module 3 * 4 * Copyright (c) 2009 SoftwareBitMaker. 5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc. 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/ctype.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/slab.h> 17 #include <linux/mmzone.h> 18 #include <linux/edac.h> 19 #include <asm/msr.h> 20 #include "edac_module.h" 21 #include "mce_amd.h" 22 23 #define amd64_debug(fmt, arg...) \ 24 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) 25 26 #define amd64_info(fmt, arg...) \ 27 edac_printk(KERN_INFO, "amd64", fmt, ##arg) 28 29 #define amd64_notice(fmt, arg...) \ 30 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) 31 32 #define amd64_warn(fmt, arg...) \ 33 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg) 34 35 #define amd64_err(fmt, arg...) \ 36 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg) 37 38 #define amd64_mc_warn(mci, fmt, arg...) \ 39 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) 40 41 #define amd64_mc_err(mci, fmt, arg...) \ 42 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) 43 44 /* 45 * Throughout the comments in this code, the following terms are used: 46 * 47 * SysAddr, DramAddr, and InputAddr 48 * 49 * These terms come directly from the amd64 documentation 50 * (AMD publication #26094). They are defined as follows: 51 * 52 * SysAddr: 53 * This is a physical address generated by a CPU core or a device 54 * doing DMA. If generated by a CPU core, a SysAddr is the result of 55 * a virtual to physical address translation by the CPU core's address 56 * translation mechanism (MMU). 57 * 58 * DramAddr: 59 * A DramAddr is derived from a SysAddr by subtracting an offset that 60 * depends on which node the SysAddr maps to and whether the SysAddr 61 * is within a range affected by memory hoisting. The DRAM Base 62 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 63 * determine which node a SysAddr maps to. 64 * 65 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 66 * is within the range of addresses specified by this register, then 67 * a value x from the DHAR is subtracted from the SysAddr to produce a 68 * DramAddr. Here, x represents the base address for the node that 69 * the SysAddr maps to plus an offset due to memory hoisting. See 70 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and 71 * sys_addr_to_dram_addr() below for more information. 72 * 73 * If the SysAddr is not affected by the DHAR then a value y is 74 * subtracted from the SysAddr to produce a DramAddr. Here, y is the 75 * base address for the node that the SysAddr maps to. See section 76 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more 77 * information. 78 * 79 * InputAddr: 80 * A DramAddr is translated to an InputAddr before being passed to the 81 * memory controller for the node that the DramAddr is associated 82 * with. The memory controller then maps the InputAddr to a csrow. 83 * If node interleaving is not in use, then the InputAddr has the same 84 * value as the DramAddr. Otherwise, the InputAddr is produced by 85 * discarding the bits used for node interleaving from the DramAddr. 86 * See section 3.4.4 for more information. 87 * 88 * The memory controller for a given node uses its DRAM CS Base and 89 * DRAM CS Mask registers to map an InputAddr to a csrow. See 90 * sections 3.5.4 and 3.5.5 for more information. 91 */ 92 93 #define EDAC_AMD64_VERSION "3.4.0" 94 #define EDAC_MOD_STR "amd64_edac" 95 96 /* Extended Model from CPUID, for CPU Revision numbers */ 97 #define K8_REV_D 1 98 #define K8_REV_E 2 99 #define K8_REV_F 4 100 101 /* Hardware limit on ChipSelect rows per MC and processors per system */ 102 #define NUM_CHIPSELECTS 8 103 #define DRAM_RANGES 8 104 105 #define ON true 106 #define OFF false 107 108 /* 109 * PCI-defined configuration space registers 110 */ 111 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 112 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 113 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b 114 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c 115 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 116 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 117 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 118 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 119 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 120 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 121 #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 122 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 123 124 /* 125 * Function 1 - Address Map 126 */ 127 #define DRAM_BASE_LO 0x40 128 #define DRAM_LIMIT_LO 0x44 129 130 /* 131 * F15 M30h D18F1x2[1C:00] 132 */ 133 #define DRAM_CONT_BASE 0x200 134 #define DRAM_CONT_LIMIT 0x204 135 136 /* 137 * F15 M30h D18F1x2[4C:40] 138 */ 139 #define DRAM_CONT_HIGH_OFF 0x240 140 141 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) 142 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) 143 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) 144 145 #define DHAR 0xf0 146 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) 147 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) 148 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) 149 150 /* NOTE: Extra mask bit vs K8 */ 151 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) 152 153 #define DCT_CFG_SEL 0x10C 154 155 #define DRAM_LOCAL_NODE_BASE 0x120 156 #define DRAM_LOCAL_NODE_LIM 0x124 157 158 #define DRAM_BASE_HI 0x140 159 #define DRAM_LIMIT_HI 0x144 160 161 162 /* 163 * Function 2 - DRAM controller 164 */ 165 #define DCSB0 0x40 166 #define DCSB1 0x140 167 #define DCSB_CS_ENABLE BIT(0) 168 169 #define DCSM0 0x60 170 #define DCSM1 0x160 171 172 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) 173 174 #define DRAM_CONTROL 0x78 175 176 #define DBAM0 0x80 177 #define DBAM1 0x180 178 179 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ 180 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) 181 182 #define DBAM_MAX_VALUE 11 183 184 #define DCLR0 0x90 185 #define DCLR1 0x190 186 #define REVE_WIDTH_128 BIT(16) 187 #define WIDTH_128 BIT(11) 188 189 #define DCHR0 0x94 190 #define DCHR1 0x194 191 #define DDR3_MODE BIT(8) 192 193 #define DCT_SEL_LO 0x110 194 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) 195 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) 196 197 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) 198 199 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) 200 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) 201 202 #define SWAP_INTLV_REG 0x10c 203 204 #define DCT_SEL_HI 0x114 205 206 #define F15H_M60H_SCRCTRL 0x1C8 207 #define F17H_SCR_BASE_ADDR 0x48 208 #define F17H_SCR_LIMIT_ADDR 0x4C 209 210 /* 211 * Function 3 - Misc Control 212 */ 213 #define NBCTL 0x40 214 215 #define NBCFG 0x44 216 #define NBCFG_CHIPKILL BIT(23) 217 #define NBCFG_ECC_ENABLE BIT(22) 218 219 /* F3x48: NBSL */ 220 #define F10_NBSL_EXT_ERR_ECC 0x8 221 #define NBSL_PP_OBS 0x2 222 223 #define SCRCTRL 0x58 224 225 #define F10_ONLINE_SPARE 0xB0 226 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) 227 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) 228 229 #define F10_NB_ARRAY_ADDR 0xB8 230 #define F10_NB_ARRAY_DRAM BIT(31) 231 232 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 233 #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) 234 235 #define F10_NB_ARRAY_DATA 0xBC 236 #define F10_NB_ARR_ECC_WR_REQ BIT(17) 237 #define SET_NB_DRAM_INJECTION_WRITE(inj) \ 238 (BIT(((inj.word) & 0xF) + 20) | \ 239 F10_NB_ARR_ECC_WR_REQ | inj.bit_map) 240 #define SET_NB_DRAM_INJECTION_READ(inj) \ 241 (BIT(((inj.word) & 0xF) + 20) | \ 242 BIT(16) | inj.bit_map) 243 244 245 #define NBCAP 0xE8 246 #define NBCAP_CHIPKILL BIT(4) 247 #define NBCAP_SECDED BIT(3) 248 #define NBCAP_DCT_DUAL BIT(0) 249 250 #define EXT_NB_MCA_CFG 0x180 251 252 /* MSRs */ 253 #define MSR_MCGCTL_NBE BIT(4) 254 255 /* F17h */ 256 257 /* F0: */ 258 #define DF_DHAR 0x104 259 260 /* UMC CH register offsets */ 261 #define UMCCH_BASE_ADDR 0x0 262 #define UMCCH_ADDR_MASK 0x20 263 #define UMCCH_ADDR_CFG 0x30 264 #define UMCCH_DIMM_CFG 0x80 265 #define UMCCH_UMC_CFG 0x100 266 #define UMCCH_SDP_CTRL 0x104 267 #define UMCCH_ECC_CTRL 0x14C 268 #define UMCCH_ECC_BAD_SYMBOL 0xD90 269 #define UMCCH_UMC_CAP 0xDF0 270 #define UMCCH_UMC_CAP_HI 0xDF4 271 272 /* UMC CH bitfields */ 273 #define UMC_ECC_CHIPKILL_CAP BIT(31) 274 #define UMC_ECC_ENABLED BIT(30) 275 276 #define UMC_SDP_INIT BIT(31) 277 278 #define NUM_UMCS 2 279 280 enum amd_families { 281 K8_CPUS = 0, 282 F10_CPUS, 283 F15_CPUS, 284 F15_M30H_CPUS, 285 F15_M60H_CPUS, 286 F16_CPUS, 287 F16_M30H_CPUS, 288 F17_CPUS, 289 NUM_FAMILIES, 290 }; 291 292 /* Error injection control structure */ 293 struct error_injection { 294 u32 section; 295 u32 word; 296 u32 bit_map; 297 }; 298 299 /* low and high part of PCI config space regs */ 300 struct reg_pair { 301 u32 lo, hi; 302 }; 303 304 /* 305 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers 306 */ 307 struct dram_range { 308 struct reg_pair base; 309 struct reg_pair lim; 310 }; 311 312 /* A DCT chip selects collection */ 313 struct chip_select { 314 u32 csbases[NUM_CHIPSELECTS]; 315 u8 b_cnt; 316 317 u32 csmasks[NUM_CHIPSELECTS]; 318 u8 m_cnt; 319 }; 320 321 struct amd64_umc { 322 u32 dimm_cfg; /* DIMM Configuration reg */ 323 u32 umc_cfg; /* Configuration reg */ 324 u32 sdp_ctrl; /* SDP Control reg */ 325 u32 ecc_ctrl; /* DRAM ECC Control reg */ 326 u32 umc_cap_hi; /* Capabilities High reg */ 327 }; 328 329 struct amd64_pvt { 330 struct low_ops *ops; 331 332 /* pci_device handles which we utilize */ 333 struct pci_dev *F0, *F1, *F2, *F3, *F6; 334 335 u16 mc_node_id; /* MC index of this MC node */ 336 u8 fam; /* CPU family */ 337 u8 model; /* ... model */ 338 u8 stepping; /* ... stepping */ 339 340 int ext_model; /* extended model value of this node */ 341 int channel_count; 342 343 /* Raw registers */ 344 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ 345 u32 dclr1; /* DRAM Configuration Low DCT1 reg */ 346 u32 dchr0; /* DRAM Configuration High DCT0 reg */ 347 u32 dchr1; /* DRAM Configuration High DCT1 reg */ 348 u32 nbcap; /* North Bridge Capabilities */ 349 u32 nbcfg; /* F10 North Bridge Configuration */ 350 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ 351 u32 dhar; /* DRAM Hoist reg */ 352 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ 353 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 354 355 /* one for each DCT */ 356 struct chip_select csels[2]; 357 358 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 359 struct dram_range ranges[DRAM_RANGES]; 360 361 u64 top_mem; /* top of memory below 4GB */ 362 u64 top_mem2; /* top of memory above 4GB */ 363 364 u32 dct_sel_lo; /* DRAM Controller Select Low */ 365 u32 dct_sel_hi; /* DRAM Controller Select High */ 366 u32 online_spare; /* On-Line spare Reg */ 367 368 /* x4 or x8 syndromes in use */ 369 u8 ecc_sym_sz; 370 371 /* place to store error injection parameters prior to issue */ 372 struct error_injection injection; 373 374 /* cache the dram_type */ 375 enum mem_type dram_type; 376 377 struct amd64_umc *umc; /* UMC registers */ 378 }; 379 380 enum err_codes { 381 DECODE_OK = 0, 382 ERR_NODE = -1, 383 ERR_CSROW = -2, 384 ERR_CHANNEL = -3, 385 ERR_SYND = -4, 386 ERR_NORM_ADDR = -5, 387 }; 388 389 struct err_info { 390 int err_code; 391 struct mem_ctl_info *src_mci; 392 int csrow; 393 int channel; 394 u16 syndrome; 395 u32 page; 396 u32 offset; 397 }; 398 399 static inline u32 get_umc_base(u8 channel) 400 { 401 /* ch0: 0x50000, ch1: 0x150000 */ 402 return 0x50000 + (!!channel << 20); 403 } 404 405 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) 406 { 407 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; 408 409 if (boot_cpu_data.x86 == 0xf) 410 return addr; 411 412 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; 413 } 414 415 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) 416 { 417 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; 418 419 if (boot_cpu_data.x86 == 0xf) 420 return lim; 421 422 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; 423 } 424 425 static inline u16 extract_syndrome(u64 status) 426 { 427 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); 428 } 429 430 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) 431 { 432 if (pvt->fam == 0x15 && pvt->model >= 0x30) 433 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | 434 ((pvt->dct_sel_lo >> 6) & 0x3); 435 436 return ((pvt)->dct_sel_lo >> 6) & 0x3; 437 } 438 /* 439 * per-node ECC settings descriptor 440 */ 441 struct ecc_settings { 442 u32 old_nbctl; 443 bool nbctl_valid; 444 445 struct flags { 446 unsigned long nb_mce_enable:1; 447 unsigned long nb_ecc_prev:1; 448 } flags; 449 }; 450 451 #ifdef CONFIG_EDAC_DEBUG 452 extern const struct attribute_group amd64_edac_dbg_group; 453 #endif 454 455 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION 456 extern const struct attribute_group amd64_edac_inj_group; 457 #endif 458 459 /* 460 * Each of the PCI Device IDs types have their own set of hardware accessor 461 * functions and per device encoding/decoding logic. 462 */ 463 struct low_ops { 464 int (*early_channel_count) (struct amd64_pvt *pvt); 465 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, 466 struct err_info *); 467 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, 468 unsigned cs_mode, int cs_mask_nr); 469 }; 470 471 struct amd64_family_type { 472 const char *ctl_name; 473 u16 f0_id, f1_id, f2_id, f6_id; 474 struct low_ops ops; 475 }; 476 477 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, 478 u32 *val, const char *func); 479 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, 480 u32 val, const char *func); 481 482 #define amd64_read_pci_cfg(pdev, offset, val) \ 483 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) 484 485 #define amd64_write_pci_cfg(pdev, offset, val) \ 486 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) 487 488 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 489 u64 *hole_offset, u64 *hole_size); 490 491 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 492 493 /* Injection helpers */ 494 static inline void disable_caches(void *dummy) 495 { 496 write_cr0(read_cr0() | X86_CR0_CD); 497 wbinvd(); 498 } 499 500 static inline void enable_caches(void *dummy) 501 { 502 write_cr0(read_cr0() & ~X86_CR0_CD); 503 } 504 505 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) 506 { 507 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 508 u32 tmp; 509 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); 510 return (u8) tmp & 0xF; 511 } 512 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; 513 } 514 515 static inline u8 dhar_valid(struct amd64_pvt *pvt) 516 { 517 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 518 u32 tmp; 519 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 520 return (tmp >> 1) & BIT(0); 521 } 522 return (pvt)->dhar & BIT(0); 523 } 524 525 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) 526 { 527 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 528 u32 tmp; 529 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 530 return (tmp >> 11) & 0x1FFF; 531 } 532 return (pvt)->dct_sel_lo & 0xFFFFF800; 533 } 534