1 /* 2 * AMD64 class Memory Controller kernel module 3 * 4 * Copyright (c) 2009 SoftwareBitMaker. 5 * Copyright (c) 2009 Advanced Micro Devices, Inc. 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 * 10 * Originally Written by Thayne Harbaugh 11 * 12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 13 * - K8 CPU Revision D and greater support 14 * 15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: 16 * - Module largely rewritten, with new (and hopefully correct) 17 * code for dealing with node and chip select interleaving, 18 * various code cleanup, and bug fixes 19 * - Added support for memory hoisting using DRAM hole address 20 * register 21 * 22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 23 * -K8 Rev (1207) revision support added, required Revision 24 * specific mini-driver code to support Rev F as well as 25 * prior revisions 26 * 27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: 28 * -Family 10h revision support added. New PCI Device IDs, 29 * indicating new changes. Actual registers modified 30 * were slight, less than the Rev E to Rev F transition 31 * but changing the PCI Device ID was the proper thing to 32 * do, as it provides for almost automactic family 33 * detection. The mods to Rev F required more family 34 * information detection. 35 * 36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>: 37 * - misc fixes and code cleanups 38 * 39 * This module is based on the following documents 40 * (available from http://www.amd.com/): 41 * 42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD 43 * Opteron Processors 44 * AMD publication #: 26094 45 *` Revision: 3.26 46 * 47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh 48 * Processors 49 * AMD publication #: 32559 50 * Revision: 3.00 51 * Issue Date: May 2006 52 * 53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h 54 * Processors 55 * AMD publication #: 31116 56 * Revision: 3.00 57 * Issue Date: September 07, 2007 58 * 59 * Sections in the first 2 documents are no longer in sync with each other. 60 * The Family 10h BKDG was totally re-written from scratch with a new 61 * presentation model. 62 * Therefore, comments that refer to a Document section might be off. 63 */ 64 65 #include <linux/module.h> 66 #include <linux/ctype.h> 67 #include <linux/init.h> 68 #include <linux/pci.h> 69 #include <linux/pci_ids.h> 70 #include <linux/slab.h> 71 #include <linux/mmzone.h> 72 #include <linux/edac.h> 73 #include <asm/msr.h> 74 #include "edac_core.h" 75 76 #define amd64_printk(level, fmt, arg...) \ 77 edac_printk(level, "amd64", fmt, ##arg) 78 79 #define amd64_mc_printk(mci, level, fmt, arg...) \ 80 edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg) 81 82 /* 83 * Throughout the comments in this code, the following terms are used: 84 * 85 * SysAddr, DramAddr, and InputAddr 86 * 87 * These terms come directly from the amd64 documentation 88 * (AMD publication #26094). They are defined as follows: 89 * 90 * SysAddr: 91 * This is a physical address generated by a CPU core or a device 92 * doing DMA. If generated by a CPU core, a SysAddr is the result of 93 * a virtual to physical address translation by the CPU core's address 94 * translation mechanism (MMU). 95 * 96 * DramAddr: 97 * A DramAddr is derived from a SysAddr by subtracting an offset that 98 * depends on which node the SysAddr maps to and whether the SysAddr 99 * is within a range affected by memory hoisting. The DRAM Base 100 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 101 * determine which node a SysAddr maps to. 102 * 103 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 104 * is within the range of addresses specified by this register, then 105 * a value x from the DHAR is subtracted from the SysAddr to produce a 106 * DramAddr. Here, x represents the base address for the node that 107 * the SysAddr maps to plus an offset due to memory hoisting. See 108 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and 109 * sys_addr_to_dram_addr() below for more information. 110 * 111 * If the SysAddr is not affected by the DHAR then a value y is 112 * subtracted from the SysAddr to produce a DramAddr. Here, y is the 113 * base address for the node that the SysAddr maps to. See section 114 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more 115 * information. 116 * 117 * InputAddr: 118 * A DramAddr is translated to an InputAddr before being passed to the 119 * memory controller for the node that the DramAddr is associated 120 * with. The memory controller then maps the InputAddr to a csrow. 121 * If node interleaving is not in use, then the InputAddr has the same 122 * value as the DramAddr. Otherwise, the InputAddr is produced by 123 * discarding the bits used for node interleaving from the DramAddr. 124 * See section 3.4.4 for more information. 125 * 126 * The memory controller for a given node uses its DRAM CS Base and 127 * DRAM CS Mask registers to map an InputAddr to a csrow. See 128 * sections 3.5.4 and 3.5.5 for more information. 129 */ 130 131 #define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__ 132 #define EDAC_MOD_STR "amd64_edac" 133 134 /* Extended Model from CPUID, for CPU Revision numbers */ 135 #define OPTERON_CPU_LE_REV_C 0 136 #define OPTERON_CPU_REV_D 1 137 #define OPTERON_CPU_REV_E 2 138 139 /* NPT processors have the following Extended Models */ 140 #define OPTERON_CPU_REV_F 4 141 #define OPTERON_CPU_REV_FA 5 142 143 /* Hardware limit on ChipSelect rows per MC and processors per system */ 144 #define CHIPSELECT_COUNT 8 145 #define DRAM_REG_COUNT 8 146 147 148 /* 149 * PCI-defined configuration space registers 150 */ 151 152 153 /* 154 * Function 1 - Address Map 155 */ 156 #define K8_DRAM_BASE_LOW 0x40 157 #define K8_DRAM_LIMIT_LOW 0x44 158 #define K8_DHAR 0xf0 159 160 #define DHAR_VALID BIT(0) 161 #define F10_DRAM_MEM_HOIST_VALID BIT(1) 162 163 #define DHAR_BASE_MASK 0xff000000 164 #define dhar_base(dhar) (dhar & DHAR_BASE_MASK) 165 166 #define K8_DHAR_OFFSET_MASK 0x0000ff00 167 #define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16) 168 169 #define F10_DHAR_OFFSET_MASK 0x0000ff80 170 /* NOTE: Extra mask bit vs K8 */ 171 #define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16) 172 173 174 /* F10 High BASE/LIMIT registers */ 175 #define F10_DRAM_BASE_HIGH 0x140 176 #define F10_DRAM_LIMIT_HIGH 0x144 177 178 179 /* 180 * Function 2 - DRAM controller 181 */ 182 #define K8_DCSB0 0x40 183 #define F10_DCSB1 0x140 184 185 #define K8_DCSB_CS_ENABLE BIT(0) 186 #define K8_DCSB_NPT_SPARE BIT(1) 187 #define K8_DCSB_NPT_TESTFAIL BIT(2) 188 189 /* 190 * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form 191 * the address 192 */ 193 #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL) 194 #define REV_E_DCS_SHIFT 4 195 #define REV_E_DCSM_COUNT 8 196 197 #define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL) 198 #define REV_F_F1Xh_DCS_SHIFT 8 199 200 /* 201 * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount 202 * to form the address 203 */ 204 #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL) 205 #define REV_F_DCS_SHIFT 8 206 #define REV_F_DCSM_COUNT 4 207 #define F10_DCSM_COUNT 4 208 #define F11_DCSM_COUNT 2 209 210 /* DRAM CS Mask Registers */ 211 #define K8_DCSM0 0x60 212 #define F10_DCSM1 0x160 213 214 /* REV E: select [29:21] and [15:9] from DCSM */ 215 #define REV_E_DCSM_MASK_BITS 0x3FE0FE00 216 217 /* unused bits [24:20] and [12:0] */ 218 #define REV_E_DCS_NOTUSED_BITS 0x01F01FFF 219 220 /* REV F and later: select [28:19] and [13:5] from DCSM */ 221 #define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0 222 223 /* unused bits [26:22] and [12:0] */ 224 #define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF 225 226 #define DBAM0 0x80 227 #define DBAM1 0x180 228 229 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ 230 #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) 231 232 #define DBAM_MAX_VALUE 11 233 234 235 #define F10_DCLR_0 0x90 236 #define F10_DCLR_1 0x190 237 #define REVE_WIDTH_128 BIT(16) 238 #define F10_WIDTH_128 BIT(11) 239 240 241 #define F10_DCHR_0 0x94 242 #define F10_DCHR_1 0x194 243 244 #define F10_DCHR_FOUR_RANK_DIMM BIT(18) 245 #define F10_DCHR_Ddr3Mode BIT(8) 246 #define F10_DCHR_MblMode BIT(6) 247 248 249 #define F10_DCTL_SEL_LOW 0x110 250 251 #define dct_sel_baseaddr(pvt) \ 252 ((pvt->dram_ctl_select_low) & 0xFFFFF800) 253 254 #define dct_sel_interleave_addr(pvt) \ 255 (((pvt->dram_ctl_select_low) >> 6) & 0x3) 256 257 enum { 258 F10_DCTL_SEL_LOW_DctSelHiRngEn = BIT(0), 259 F10_DCTL_SEL_LOW_DctSelIntLvEn = BIT(2), 260 F10_DCTL_SEL_LOW_DctGangEn = BIT(4), 261 F10_DCTL_SEL_LOW_DctDatIntLv = BIT(5), 262 F10_DCTL_SEL_LOW_DramEnable = BIT(8), 263 F10_DCTL_SEL_LOW_MemCleared = BIT(10), 264 }; 265 266 #define dct_high_range_enabled(pvt) \ 267 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn) 268 269 #define dct_interleave_enabled(pvt) \ 270 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn) 271 272 #define dct_ganging_enabled(pvt) \ 273 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn) 274 275 #define dct_data_intlv_enabled(pvt) \ 276 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv) 277 278 #define dct_dram_enabled(pvt) \ 279 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable) 280 281 #define dct_memory_cleared(pvt) \ 282 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared) 283 284 285 #define F10_DCTL_SEL_HIGH 0x114 286 287 288 /* 289 * Function 3 - Misc Control 290 */ 291 #define K8_NBCTL 0x40 292 293 /* Correctable ECC error reporting enable */ 294 #define K8_NBCTL_CECCEn BIT(0) 295 296 /* UnCorrectable ECC error reporting enable */ 297 #define K8_NBCTL_UECCEn BIT(1) 298 299 #define K8_NBCFG 0x44 300 #define K8_NBCFG_CHIPKILL BIT(23) 301 #define K8_NBCFG_ECC_ENABLE BIT(22) 302 303 #define K8_NBSL 0x48 304 305 306 #define EXTRACT_HIGH_SYNDROME(x) (((x) >> 24) & 0xff) 307 #define EXTRACT_EXT_ERROR_CODE(x) (((x) >> 16) & 0x1f) 308 309 /* Family F10h: Normalized Extended Error Codes */ 310 #define F10_NBSL_EXT_ERR_RES 0x0 311 #define F10_NBSL_EXT_ERR_CRC 0x1 312 #define F10_NBSL_EXT_ERR_SYNC 0x2 313 #define F10_NBSL_EXT_ERR_MST 0x3 314 #define F10_NBSL_EXT_ERR_TGT 0x4 315 #define F10_NBSL_EXT_ERR_GART 0x5 316 #define F10_NBSL_EXT_ERR_RMW 0x6 317 #define F10_NBSL_EXT_ERR_WDT 0x7 318 #define F10_NBSL_EXT_ERR_ECC 0x8 319 #define F10_NBSL_EXT_ERR_DEV 0x9 320 #define F10_NBSL_EXT_ERR_LINK_DATA 0xA 321 322 /* Next two are overloaded values */ 323 #define F10_NBSL_EXT_ERR_LINK_PROTO 0xB 324 #define F10_NBSL_EXT_ERR_L3_PROTO 0xB 325 326 #define F10_NBSL_EXT_ERR_NB_ARRAY 0xC 327 #define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD 328 #define F10_NBSL_EXT_ERR_LINK_RETRY 0xE 329 330 /* Next two are overloaded values */ 331 #define F10_NBSL_EXT_ERR_GART_WALK 0xF 332 #define F10_NBSL_EXT_ERR_DEV_WALK 0xF 333 334 /* 0x10 to 0x1B: Reserved */ 335 #define F10_NBSL_EXT_ERR_L3_DATA 0x1C 336 #define F10_NBSL_EXT_ERR_L3_TAG 0x1D 337 #define F10_NBSL_EXT_ERR_L3_LRU 0x1E 338 339 /* K8: Normalized Extended Error Codes */ 340 #define K8_NBSL_EXT_ERR_ECC 0x0 341 #define K8_NBSL_EXT_ERR_CRC 0x1 342 #define K8_NBSL_EXT_ERR_SYNC 0x2 343 #define K8_NBSL_EXT_ERR_MST 0x3 344 #define K8_NBSL_EXT_ERR_TGT 0x4 345 #define K8_NBSL_EXT_ERR_GART 0x5 346 #define K8_NBSL_EXT_ERR_RMW 0x6 347 #define K8_NBSL_EXT_ERR_WDT 0x7 348 #define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8 349 #define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD 350 351 #define EXTRACT_ERROR_CODE(x) ((x) & 0xffff) 352 #define TEST_TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) 353 #define TEST_MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) 354 #define TEST_BUS_ERROR(x) (((x) & 0xF800) == 0x0800) 355 #define EXTRACT_TT_CODE(x) (((x) >> 2) & 0x3) 356 #define EXTRACT_II_CODE(x) (((x) >> 2) & 0x3) 357 #define EXTRACT_LL_CODE(x) (((x) >> 0) & 0x3) 358 #define EXTRACT_RRRR_CODE(x) (((x) >> 4) & 0xf) 359 #define EXTRACT_TO_CODE(x) (((x) >> 8) & 0x1) 360 #define EXTRACT_PP_CODE(x) (((x) >> 9) & 0x3) 361 362 /* 363 * The following are for BUS type errors AFTER values have been normalized by 364 * shifting right 365 */ 366 #define K8_NBSL_PP_SRC 0x0 367 #define K8_NBSL_PP_RES 0x1 368 #define K8_NBSL_PP_OBS 0x2 369 #define K8_NBSL_PP_GENERIC 0x3 370 371 372 #define K8_NBSH 0x4C 373 374 #define K8_NBSH_VALID_BIT BIT(31) 375 #define K8_NBSH_OVERFLOW BIT(30) 376 #define K8_NBSH_UNCORRECTED_ERR BIT(29) 377 #define K8_NBSH_ERR_ENABLE BIT(28) 378 #define K8_NBSH_MISC_ERR_VALID BIT(27) 379 #define K8_NBSH_VALID_ERROR_ADDR BIT(26) 380 #define K8_NBSH_PCC BIT(25) 381 #define K8_NBSH_CECC BIT(14) 382 #define K8_NBSH_UECC BIT(13) 383 #define K8_NBSH_ERR_SCRUBER BIT(8) 384 #define K8_NBSH_CORE3 BIT(3) 385 #define K8_NBSH_CORE2 BIT(2) 386 #define K8_NBSH_CORE1 BIT(1) 387 #define K8_NBSH_CORE0 BIT(0) 388 389 #define EXTRACT_LDT_LINK(x) (((x) >> 4) & 0x7) 390 #define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF) 391 #define EXTRACT_LOW_SYNDROME(x) (((x) >> 15) & 0xff) 392 393 394 #define K8_NBEAL 0x50 395 #define K8_NBEAH 0x54 396 #define K8_SCRCTRL 0x58 397 398 #define F10_NB_CFG_LOW 0x88 399 #define F10_NB_CFG_LOW_ENABLE_EXT_CFG BIT(14) 400 401 #define F10_NB_CFG_HIGH 0x8C 402 403 #define F10_ONLINE_SPARE 0xB0 404 #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) 405 #define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3)) 406 #define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007) 407 #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) 408 409 #define F10_NB_ARRAY_ADDR 0xB8 410 411 #define F10_NB_ARRAY_DRAM_ECC 0x80000000 412 413 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 414 #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) 415 416 #define F10_NB_ARRAY_DATA 0xBC 417 418 #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ 419 (BIT(((word) & 0xF) + 20) | \ 420 BIT(17) | \ 421 ((bits) & 0xF)) 422 423 #define SET_NB_DRAM_INJECTION_READ(word, bits) \ 424 (BIT(((word) & 0xF) + 20) | \ 425 BIT(16) | \ 426 ((bits) & 0xF)) 427 428 #define K8_NBCAP 0xE8 429 #define K8_NBCAP_CORES (BIT(12)|BIT(13)) 430 #define K8_NBCAP_CHIPKILL BIT(4) 431 #define K8_NBCAP_SECDED BIT(3) 432 #define K8_NBCAP_8_NODE BIT(2) 433 #define K8_NBCAP_DUAL_NODE BIT(1) 434 #define K8_NBCAP_DCT_DUAL BIT(0) 435 436 /* 437 * MSR Regs 438 */ 439 #define K8_MSR_MCGCTL 0x017b 440 #define K8_MSR_MCGCTL_NBE BIT(4) 441 442 #define K8_MSR_MC4CTL 0x0410 443 #define K8_MSR_MC4STAT 0x0411 444 #define K8_MSR_MC4ADDR 0x0412 445 446 /* AMD sets the first MC device at device ID 0x18. */ 447 static inline int get_node_id(struct pci_dev *pdev) 448 { 449 return PCI_SLOT(pdev->devfn) - 0x18; 450 } 451 452 enum amd64_chipset_families { 453 K8_CPUS = 0, 454 F10_CPUS, 455 F11_CPUS, 456 }; 457 458 /* 459 * Structure to hold: 460 * 461 * 1) dynamically read status and error address HW registers 462 * 2) sysfs entered values 463 * 3) MCE values 464 * 465 * Depends on entry into the modules 466 */ 467 struct amd64_error_info_regs { 468 u32 nbcfg; 469 u32 nbsh; 470 u32 nbsl; 471 u32 nbeah; 472 u32 nbeal; 473 }; 474 475 /* Error injection control structure */ 476 struct error_injection { 477 u32 section; 478 u32 word; 479 u32 bit_map; 480 }; 481 482 struct amd64_pvt { 483 /* pci_device handles which we utilize */ 484 struct pci_dev *addr_f1_ctl; 485 struct pci_dev *dram_f2_ctl; 486 struct pci_dev *misc_f3_ctl; 487 488 int mc_node_id; /* MC index of this MC node */ 489 int ext_model; /* extended model value of this node */ 490 491 struct low_ops *ops; /* pointer to per PCI Device ID func table */ 492 493 int channel_count; 494 495 /* Raw registers */ 496 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ 497 u32 dclr1; /* DRAM Configuration Low DCT1 reg */ 498 u32 dchr0; /* DRAM Configuration High DCT0 reg */ 499 u32 dchr1; /* DRAM Configuration High DCT1 reg */ 500 u32 nbcap; /* North Bridge Capabilities */ 501 u32 nbcfg; /* F10 North Bridge Configuration */ 502 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ 503 u32 dhar; /* DRAM Hoist reg */ 504 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ 505 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 506 507 /* DRAM CS Base Address Registers F2x[1,0][5C:40] */ 508 u32 dcsb0[CHIPSELECT_COUNT]; 509 u32 dcsb1[CHIPSELECT_COUNT]; 510 511 /* DRAM CS Mask Registers F2x[1,0][6C:60] */ 512 u32 dcsm0[CHIPSELECT_COUNT]; 513 u32 dcsm1[CHIPSELECT_COUNT]; 514 515 /* 516 * Decoded parts of DRAM BASE and LIMIT Registers 517 * F1x[78,70,68,60,58,50,48,40] 518 */ 519 u64 dram_base[DRAM_REG_COUNT]; 520 u64 dram_limit[DRAM_REG_COUNT]; 521 u8 dram_IntlvSel[DRAM_REG_COUNT]; 522 u8 dram_IntlvEn[DRAM_REG_COUNT]; 523 u8 dram_DstNode[DRAM_REG_COUNT]; 524 u8 dram_rw_en[DRAM_REG_COUNT]; 525 526 /* 527 * The following fields are set at (load) run time, after CPU revision 528 * has been determined, since the dct_base and dct_mask registers vary 529 * based on revision 530 */ 531 u32 dcsb_base; /* DCSB base bits */ 532 u32 dcsm_mask; /* DCSM mask bits */ 533 u32 num_dcsm; /* Number of DCSM registers */ 534 u32 dcs_mask_notused; /* DCSM notused mask bits */ 535 u32 dcs_shift; /* DCSB and DCSM shift value */ 536 537 u64 top_mem; /* top of memory below 4GB */ 538 u64 top_mem2; /* top of memory above 4GB */ 539 540 u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */ 541 u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */ 542 u32 online_spare; /* On-Line spare Reg */ 543 544 /* temp storage for when input is received from sysfs */ 545 struct amd64_error_info_regs ctl_error_info; 546 547 /* place to store error injection parameters prior to issue */ 548 struct error_injection injection; 549 550 /* Save old hw registers' values before we modified them */ 551 u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */ 552 u32 old_nbctl; 553 unsigned long old_mcgctl; /* per core on this node */ 554 555 /* MC Type Index value: socket F vs Family 10h */ 556 u32 mc_type_index; 557 558 /* misc settings */ 559 struct flags { 560 unsigned long cf8_extcfg:1; 561 } flags; 562 }; 563 564 struct scrubrate { 565 u32 scrubval; /* bit pattern for scrub rate */ 566 u32 bandwidth; /* bandwidth consumed (bytes/sec) */ 567 }; 568 569 extern struct scrubrate scrubrates[23]; 570 extern u32 revf_quad_ddr2_shift[16]; 571 extern const char *tt_msgs[4]; 572 extern const char *ll_msgs[4]; 573 extern const char *rrrr_msgs[16]; 574 extern const char *to_msgs[2]; 575 extern const char *pp_msgs[4]; 576 extern const char *ii_msgs[4]; 577 extern const char *ext_msgs[32]; 578 extern const char *htlink_msgs[8]; 579 580 #ifdef CONFIG_EDAC_DEBUG 581 #define NUM_DBG_ATTRS 9 582 #else 583 #define NUM_DBG_ATTRS 0 584 #endif 585 586 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION 587 #define NUM_INJ_ATTRS 5 588 #else 589 #define NUM_INJ_ATTRS 0 590 #endif 591 592 extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS], 593 amd64_inj_attrs[NUM_INJ_ATTRS]; 594 595 /* 596 * Each of the PCI Device IDs types have their own set of hardware accessor 597 * functions and per device encoding/decoding logic. 598 */ 599 struct low_ops { 600 int (*probe_valid_hardware)(struct amd64_pvt *pvt); 601 int (*early_channel_count)(struct amd64_pvt *pvt); 602 603 u64 (*get_error_address)(struct mem_ctl_info *mci, 604 struct amd64_error_info_regs *info); 605 void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram); 606 void (*read_dram_ctl_register)(struct amd64_pvt *pvt); 607 void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, 608 struct amd64_error_info_regs *info, 609 u64 SystemAddr); 610 int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map); 611 }; 612 613 struct amd64_family_type { 614 const char *ctl_name; 615 u16 addr_f1_ctl; 616 u16 misc_f3_ctl; 617 struct low_ops ops; 618 }; 619 620 static struct amd64_family_type amd64_family_types[]; 621 622 static inline const char *get_amd_family_name(int index) 623 { 624 return amd64_family_types[index].ctl_name; 625 } 626 627 static inline struct low_ops *family_ops(int index) 628 { 629 return &amd64_family_types[index].ops; 630 } 631 632 /* 633 * For future CPU versions, verify the following as new 'slow' rates appear and 634 * modify the necessary skip values for the supported CPU. 635 */ 636 #define K8_MIN_SCRUB_RATE_BITS 0x0 637 #define F10_MIN_SCRUB_RATE_BITS 0x5 638 #define F11_MIN_SCRUB_RATE_BITS 0x6 639 640 int amd64_process_error_info(struct mem_ctl_info *mci, 641 struct amd64_error_info_regs *info, 642 int handle_errors); 643 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 644 u64 *hole_offset, u64 *hole_size); 645