1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 help 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES 58 select UEFI_CPER 59 help 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 62 APEI/GHES driver. By enabling this option, the error reports provided 63 by GHES are sent to userspace via the EDAC API. 64 65 When this option is enabled, it will disable the hardware-driven 66 mechanisms, if a GHES BIOS is detected, entering into the 67 "Firmware First" mode. 68 69 It should be noticed that keeping both GHES and a hardware-driven 70 error mechanism won't work well, as BIOS will race with OS, while 71 reading the error registers. So, if you want to not use "Firmware 72 first" GHES error mechanism, you should disable GHES either at 73 compilation time or by passing "ghes.disable=1" Kernel parameter 74 at boot time. 75 76 In doubt, say 'Y'. 77 78config EDAC_SCRUB 79 bool "EDAC scrub feature" 80 help 81 The EDAC scrub feature is optional and is designed to control the 82 memory scrubbers in the system. The common sysfs scrub interface 83 abstracts the control of various arbitrary scrubbing functionalities 84 into a unified set of functions. 85 Say 'y/n' to enable/disable EDAC scrub feature. 86 87config EDAC_AMD64 88 tristate "AMD64 (Opteron, Athlon64)" 89 depends on AMD_NB && EDAC_DECODE_MCE 90 depends on AMD_NODE 91 imply AMD_ATL 92 help 93 Support for error detection and correction of DRAM ECC errors on 94 the AMD64 families (>= K8) of memory controllers. 95 96 When EDAC_DEBUG is enabled, hardware error injection facilities 97 through sysfs are available: 98 99 AMD CPUs up to and excluding family 0x17 provide for Memory 100 Error Injection into the ECC detection circuits. The amd64_edac 101 module allows the operator/user to inject Uncorrectable and 102 Correctable errors into DRAM. 103 104 When enabled, in each of the respective memory controller directories 105 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 106 107 - inject_section (0..3, 16-byte section of 64-byte cacheline), 108 - inject_word (0..8, 16-bit word of 16-byte section), 109 - inject_ecc_vector (hex ecc vector: select bits of inject word) 110 111 In addition, there are two control files, inject_read and inject_write, 112 which trigger the DRAM ECC Read and Write respectively. 113 114config EDAC_AL_MC 115 tristate "Amazon's Annapurna Lab Memory Controller" 116 depends on (ARCH_ALPINE || COMPILE_TEST) 117 help 118 Support for error detection and correction for Amazon's Annapurna 119 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 120 121config EDAC_AMD76X 122 tristate "AMD 76x (760, 762, 768)" 123 depends on PCI && X86_32 124 help 125 Support for error detection and correction on the AMD 76x 126 series of chipsets used with the Athlon processor. 127 128config EDAC_E7XXX 129 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 130 depends on PCI && X86_32 131 help 132 Support for error detection and correction on the Intel 133 E7205, E7500, E7501 and E7505 server chipsets. 134 135config EDAC_E752X 136 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 137 depends on PCI && X86 138 help 139 Support for error detection and correction on the Intel 140 E7520, E7525, E7320 server chipsets. 141 142config EDAC_I82443BXGX 143 tristate "Intel 82443BX/GX (440BX/GX)" 144 depends on PCI && X86_32 145 depends on BROKEN 146 help 147 Support for error detection and correction on the Intel 148 82443BX/GX memory controllers (440BX/GX chipsets). 149 150config EDAC_I82875P 151 tristate "Intel 82875p (D82875P, E7210)" 152 depends on PCI && X86_32 153 help 154 Support for error detection and correction on the Intel 155 DP82785P and E7210 server chipsets. 156 157config EDAC_I82975X 158 tristate "Intel 82975x (D82975x)" 159 depends on PCI && X86 160 help 161 Support for error detection and correction on the Intel 162 DP82975x server chipsets. 163 164config EDAC_I3000 165 tristate "Intel 3000/3010" 166 depends on PCI && X86 167 help 168 Support for error detection and correction on the Intel 169 3000 and 3010 server chipsets. 170 171config EDAC_I3200 172 tristate "Intel 3200" 173 depends on PCI && X86 174 help 175 Support for error detection and correction on the Intel 176 3200 and 3210 server chipsets. 177 178config EDAC_IE31200 179 tristate "Intel e312xx" 180 depends on PCI && X86 181 help 182 Support for error detection and correction on the Intel 183 E3-1200 based DRAM controllers. 184 185config EDAC_X38 186 tristate "Intel X38" 187 depends on PCI && X86 188 help 189 Support for error detection and correction on the Intel 190 X38 server chipsets. 191 192config EDAC_I5400 193 tristate "Intel 5400 (Seaburg) chipsets" 194 depends on PCI && X86 195 help 196 Support for error detection and correction the Intel 197 i5400 MCH chipset (Seaburg). 198 199config EDAC_I7CORE 200 tristate "Intel i7 Core (Nehalem) processors" 201 depends on PCI && X86 && X86_MCE_INTEL 202 help 203 Support for error detection and correction the Intel 204 i7 Core (Nehalem) Integrated Memory Controller that exists on 205 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 206 and Xeon 55xx processors. 207 208config EDAC_I82860 209 tristate "Intel 82860" 210 depends on PCI && X86_32 211 help 212 Support for error detection and correction on the Intel 213 82860 chipset. 214 215config EDAC_R82600 216 tristate "Radisys 82600 embedded chipset" 217 depends on PCI && X86_32 218 help 219 Support for error detection and correction on the Radisys 220 82600 embedded chipset. 221 222config EDAC_I5000 223 tristate "Intel Greencreek/Blackford chipset" 224 depends on X86 && PCI 225 depends on BROKEN 226 help 227 Support for error detection and correction the Intel 228 Greekcreek/Blackford chipsets. 229 230config EDAC_I5100 231 tristate "Intel San Clemente MCH" 232 depends on X86 && PCI 233 help 234 Support for error detection and correction the Intel 235 San Clemente MCH. 236 237config EDAC_I7300 238 tristate "Intel Clarksboro MCH" 239 depends on X86 && PCI 240 help 241 Support for error detection and correction the Intel 242 Clarksboro MCH (Intel 7300 chipset). 243 244config EDAC_SBRIDGE 245 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 246 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 247 help 248 Support for error detection and correction the Intel 249 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 250 251config EDAC_SKX 252 tristate "Intel Skylake server Integrated MC" 253 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 254 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 255 select DMI 256 select ACPI_ADXL 257 help 258 Support for error detection and correction the Intel 259 Skylake server Integrated Memory Controllers. If your 260 system has non-volatile DIMMs you should also manually 261 select CONFIG_ACPI_NFIT. 262 263config EDAC_I10NM 264 tristate "Intel 10nm server Integrated MC" 265 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 266 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 267 select DMI 268 select ACPI_ADXL 269 help 270 Support for error detection and correction the Intel 271 10nm server Integrated Memory Controllers. If your 272 system has non-volatile DIMMs you should also manually 273 select CONFIG_ACPI_NFIT. 274 275config EDAC_PND2 276 tristate "Intel Pondicherry2" 277 depends on PCI && X86_64 && X86_MCE_INTEL 278 select P2SB if X86 279 help 280 Support for error detection and correction on the Intel 281 Pondicherry2 Integrated Memory Controller. This SoC IP is 282 first used on the Apollo Lake platform and Denverton 283 micro-server but may appear on others in the future. 284 285config EDAC_IGEN6 286 tristate "Intel client SoC Integrated MC" 287 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 288 depends on X86_64 && X86_MCE_INTEL 289 help 290 Support for error detection and correction on the Intel 291 client SoC Integrated Memory Controller using In-Band ECC IP. 292 This In-Band ECC is first used on the Elkhart Lake SoC but 293 may appear on others in the future. 294 295config EDAC_MPC85XX 296 bool "Freescale MPC83xx / MPC85xx" 297 depends on FSL_SOC && EDAC=y 298 help 299 Support for error detection and correction on the Freescale 300 MPC8349, MPC8560, MPC8540, MPC8548, T4240 301 302config EDAC_LAYERSCAPE 303 tristate "Freescale Layerscape DDR" 304 depends on ARCH_LAYERSCAPE || SOC_LS1021A 305 help 306 Support for error detection and correction on Freescale memory 307 controllers on Layerscape SoCs. 308 309config EDAC_PASEMI 310 tristate "PA Semi PWRficient" 311 depends on PPC_PASEMI && PCI 312 help 313 Support for error detection and correction on PA Semi 314 PWRficient. 315 316config EDAC_CPC925 317 tristate "IBM CPC925 Memory Controller (PPC970FX)" 318 depends on PPC64 319 help 320 Support for error detection and correction on the 321 IBM CPC925 Bridge and Memory Controller, which is 322 a companion chip to the PowerPC 970 family of 323 processors. 324 325config EDAC_HIGHBANK_MC 326 tristate "Highbank Memory Controller" 327 depends on ARCH_HIGHBANK 328 help 329 Support for error detection and correction on the 330 Calxeda Highbank memory controller. 331 332config EDAC_HIGHBANK_L2 333 tristate "Highbank L2 Cache" 334 depends on ARCH_HIGHBANK 335 help 336 Support for error detection and correction on the 337 Calxeda Highbank memory controller. 338 339config EDAC_OCTEON_PC 340 tristate "Cavium Octeon Primary Caches" 341 depends on CPU_CAVIUM_OCTEON 342 help 343 Support for error detection and correction on the primary caches of 344 the cnMIPS cores of Cavium Octeon family SOCs. 345 346config EDAC_OCTEON_L2C 347 tristate "Cavium Octeon Secondary Caches (L2C)" 348 depends on CAVIUM_OCTEON_SOC 349 help 350 Support for error detection and correction on the 351 Cavium Octeon family of SOCs. 352 353config EDAC_OCTEON_LMC 354 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 355 depends on CAVIUM_OCTEON_SOC 356 help 357 Support for error detection and correction on the 358 Cavium Octeon family of SOCs. 359 360config EDAC_OCTEON_PCI 361 tristate "Cavium Octeon PCI Controller" 362 depends on PCI && CAVIUM_OCTEON_SOC 363 help 364 Support for error detection and correction on the 365 Cavium Octeon family of SOCs. 366 367config EDAC_THUNDERX 368 tristate "Cavium ThunderX EDAC" 369 depends on ARM64 370 depends on PCI 371 help 372 Support for error detection and correction on the 373 Cavium ThunderX memory controllers (LMC), Cache 374 Coherent Processor Interconnect (CCPI) and L2 cache 375 blocks (TAD, CBC, MCI). 376 377config EDAC_ALTERA 378 bool "Altera SOCFPGA ECC" 379 depends on EDAC=y && ARCH_INTEL_SOCFPGA 380 help 381 Support for error detection and correction on the 382 Altera SOCs. This is the global enable for the 383 various Altera peripherals. 384 385config EDAC_ALTERA_SDRAM 386 bool "Altera SDRAM ECC" 387 depends on EDAC_ALTERA=y 388 help 389 Support for error detection and correction on the 390 Altera SDRAM Memory for Altera SoCs. Note that the 391 preloader must initialize the SDRAM before loading 392 the kernel. 393 394config EDAC_ALTERA_L2C 395 bool "Altera L2 Cache ECC" 396 depends on EDAC_ALTERA=y && CACHE_L2X0 397 help 398 Support for error detection and correction on the 399 Altera L2 cache Memory for Altera SoCs. This option 400 requires L2 cache. 401 402config EDAC_ALTERA_OCRAM 403 bool "Altera On-Chip RAM ECC" 404 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 405 help 406 Support for error detection and correction on the 407 Altera On-Chip RAM Memory for Altera SoCs. 408 409config EDAC_ALTERA_ETHERNET 410 bool "Altera Ethernet FIFO ECC" 411 depends on EDAC_ALTERA=y 412 help 413 Support for error detection and correction on the 414 Altera Ethernet FIFO Memory for Altera SoCs. 415 416config EDAC_ALTERA_NAND 417 bool "Altera NAND FIFO ECC" 418 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 419 help 420 Support for error detection and correction on the 421 Altera NAND FIFO Memory for Altera SoCs. 422 423config EDAC_ALTERA_DMA 424 bool "Altera DMA FIFO ECC" 425 depends on EDAC_ALTERA=y && PL330_DMA=y 426 help 427 Support for error detection and correction on the 428 Altera DMA FIFO Memory for Altera SoCs. 429 430config EDAC_ALTERA_USB 431 bool "Altera USB FIFO ECC" 432 depends on EDAC_ALTERA=y && USB_DWC2 433 help 434 Support for error detection and correction on the 435 Altera USB FIFO Memory for Altera SoCs. 436 437config EDAC_ALTERA_QSPI 438 bool "Altera QSPI FIFO ECC" 439 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 440 help 441 Support for error detection and correction on the 442 Altera QSPI FIFO Memory for Altera SoCs. 443 444config EDAC_ALTERA_SDMMC 445 bool "Altera SDMMC FIFO ECC" 446 depends on EDAC_ALTERA=y && MMC_DW 447 help 448 Support for error detection and correction on the 449 Altera SDMMC FIFO Memory for Altera SoCs. 450 451config EDAC_SIFIVE 452 bool "Sifive platform EDAC driver" 453 depends on EDAC=y && SIFIVE_CCACHE 454 help 455 Support for error detection and correction on the SiFive SoCs. 456 457config EDAC_ARMADA_XP 458 bool "Marvell Armada XP DDR and L2 Cache ECC" 459 depends on MACH_MVEBU_V7 460 help 461 Support for error correction and detection on the Marvell Aramada XP 462 DDR RAM and L2 cache controllers. 463 464config EDAC_SYNOPSYS 465 tristate "Synopsys DDR Memory Controller" 466 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 467 help 468 Support for error detection and correction on the Synopsys DDR 469 memory controller. 470 471config EDAC_XGENE 472 tristate "APM X-Gene SoC" 473 depends on (ARM64 || COMPILE_TEST) 474 help 475 Support for error detection and correction on the 476 APM X-Gene family of SOCs. 477 478config EDAC_TI 479 tristate "Texas Instruments DDR3 ECC Controller" 480 depends on ARCH_KEYSTONE || SOC_DRA7XX 481 help 482 Support for error detection and correction on the TI SoCs. 483 484config EDAC_QCOM 485 tristate "QCOM EDAC Controller" 486 depends on ARCH_QCOM && QCOM_LLCC 487 help 488 Support for error detection and correction on the 489 Qualcomm Technologies, Inc. SoCs. 490 491 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 492 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 493 of Tag RAM and Data RAM. 494 495 For debugging issues having to do with stability and overall system 496 health, you should probably say 'Y' here. 497 498config EDAC_ASPEED 499 tristate "Aspeed AST BMC SoC" 500 depends on ARCH_ASPEED 501 help 502 Support for error detection and correction on the Aspeed AST BMC SoC. 503 504 First, ECC must be configured in the bootloader. Then, this driver 505 will expose error counters via the EDAC kernel framework. 506 507config EDAC_BLUEFIELD 508 tristate "Mellanox BlueField Memory ECC" 509 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 510 help 511 Support for error detection and correction on the 512 Mellanox BlueField SoCs. 513 514config EDAC_DMC520 515 tristate "ARM DMC-520 ECC" 516 depends on ARM64 517 help 518 Support for error detection and correction on the 519 SoCs with ARM DMC-520 DRAM controller. 520 521config EDAC_ZYNQMP 522 tristate "Xilinx ZynqMP OCM Controller" 523 depends on ARCH_ZYNQMP || COMPILE_TEST 524 help 525 This driver supports error detection and correction for the 526 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 527 built as a module. In that case it will be called zynqmp_edac. 528 529config EDAC_NPCM 530 tristate "Nuvoton NPCM DDR Memory Controller" 531 depends on (ARCH_NPCM || COMPILE_TEST) 532 help 533 Support for error detection and correction on the Nuvoton NPCM DDR 534 memory controller. 535 536 The memory controller supports single bit error correction, double bit 537 error detection (in-line ECC in which a section 1/8th of the memory 538 device used to store data is used for ECC storage). 539 540config EDAC_VERSAL 541 tristate "Xilinx Versal DDR Memory Controller" 542 depends on ARCH_ZYNQMP || COMPILE_TEST 543 help 544 Support for error detection and correction on the Xilinx Versal DDR 545 memory controller. 546 547 Report both single bit errors (CE) and double bit errors (UE). 548 Support injecting both correctable and uncorrectable errors 549 for debugging purposes. 550 551config EDAC_LOONGSON 552 tristate "Loongson Memory Controller" 553 depends on LOONGARCH && ACPI 554 help 555 Support for error detection and correction on the Loongson 556 family memory controller. This driver reports single bit 557 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 558 are compatible. 559 560endif # EDAC 561