1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 help 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES 58 select UEFI_CPER 59 help 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 62 APEI/GHES driver. By enabling this option, the error reports provided 63 by GHES are sent to userspace via the EDAC API. 64 65 When this option is enabled, it will disable the hardware-driven 66 mechanisms, if a GHES BIOS is detected, entering into the 67 "Firmware First" mode. 68 69 It should be noticed that keeping both GHES and a hardware-driven 70 error mechanism won't work well, as BIOS will race with OS, while 71 reading the error registers. So, if you want to not use "Firmware 72 first" GHES error mechanism, you should disable GHES either at 73 compilation time or by passing "ghes.disable=1" Kernel parameter 74 at boot time. 75 76 In doubt, say 'Y'. 77 78config EDAC_SCRUB 79 bool "EDAC scrub feature" 80 help 81 The EDAC scrub feature is optional and is designed to control the 82 memory scrubbers in the system. The common sysfs scrub interface 83 abstracts the control of various arbitrary scrubbing functionalities 84 into a unified set of functions. 85 Say 'y/n' to enable/disable EDAC scrub feature. 86 87config EDAC_ECS 88 bool "EDAC ECS (Error Check Scrub) feature" 89 help 90 The EDAC ECS feature is optional and is designed to control on-die 91 error check scrub (e.g., DDR5 ECS) in the system. The common sysfs 92 ECS interface abstracts the control of various ECS functionalities 93 into a unified set of functions. 94 Say 'y/n' to enable/disable EDAC ECS feature. 95 96config EDAC_AMD64 97 tristate "AMD64 (Opteron, Athlon64)" 98 depends on AMD_NB && EDAC_DECODE_MCE 99 depends on AMD_NODE 100 imply AMD_ATL 101 help 102 Support for error detection and correction of DRAM ECC errors on 103 the AMD64 families (>= K8) of memory controllers. 104 105 When EDAC_DEBUG is enabled, hardware error injection facilities 106 through sysfs are available: 107 108 AMD CPUs up to and excluding family 0x17 provide for Memory 109 Error Injection into the ECC detection circuits. The amd64_edac 110 module allows the operator/user to inject Uncorrectable and 111 Correctable errors into DRAM. 112 113 When enabled, in each of the respective memory controller directories 114 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 115 116 - inject_section (0..3, 16-byte section of 64-byte cacheline), 117 - inject_word (0..8, 16-bit word of 16-byte section), 118 - inject_ecc_vector (hex ecc vector: select bits of inject word) 119 120 In addition, there are two control files, inject_read and inject_write, 121 which trigger the DRAM ECC Read and Write respectively. 122 123config EDAC_AL_MC 124 tristate "Amazon's Annapurna Lab Memory Controller" 125 depends on (ARCH_ALPINE || COMPILE_TEST) 126 help 127 Support for error detection and correction for Amazon's Annapurna 128 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 129 130config EDAC_AMD76X 131 tristate "AMD 76x (760, 762, 768)" 132 depends on PCI && X86_32 133 help 134 Support for error detection and correction on the AMD 76x 135 series of chipsets used with the Athlon processor. 136 137config EDAC_E7XXX 138 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 139 depends on PCI && X86_32 140 help 141 Support for error detection and correction on the Intel 142 E7205, E7500, E7501 and E7505 server chipsets. 143 144config EDAC_E752X 145 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 146 depends on PCI && X86 147 help 148 Support for error detection and correction on the Intel 149 E7520, E7525, E7320 server chipsets. 150 151config EDAC_I82443BXGX 152 tristate "Intel 82443BX/GX (440BX/GX)" 153 depends on PCI && X86_32 154 depends on BROKEN 155 help 156 Support for error detection and correction on the Intel 157 82443BX/GX memory controllers (440BX/GX chipsets). 158 159config EDAC_I82875P 160 tristate "Intel 82875p (D82875P, E7210)" 161 depends on PCI && X86_32 162 help 163 Support for error detection and correction on the Intel 164 DP82785P and E7210 server chipsets. 165 166config EDAC_I82975X 167 tristate "Intel 82975x (D82975x)" 168 depends on PCI && X86 169 help 170 Support for error detection and correction on the Intel 171 DP82975x server chipsets. 172 173config EDAC_I3000 174 tristate "Intel 3000/3010" 175 depends on PCI && X86 176 help 177 Support for error detection and correction on the Intel 178 3000 and 3010 server chipsets. 179 180config EDAC_I3200 181 tristate "Intel 3200" 182 depends on PCI && X86 183 help 184 Support for error detection and correction on the Intel 185 3200 and 3210 server chipsets. 186 187config EDAC_IE31200 188 tristate "Intel e312xx" 189 depends on PCI && X86 190 help 191 Support for error detection and correction on the Intel 192 E3-1200 based DRAM controllers. 193 194config EDAC_X38 195 tristate "Intel X38" 196 depends on PCI && X86 197 help 198 Support for error detection and correction on the Intel 199 X38 server chipsets. 200 201config EDAC_I5400 202 tristate "Intel 5400 (Seaburg) chipsets" 203 depends on PCI && X86 204 help 205 Support for error detection and correction the Intel 206 i5400 MCH chipset (Seaburg). 207 208config EDAC_I7CORE 209 tristate "Intel i7 Core (Nehalem) processors" 210 depends on PCI && X86 && X86_MCE_INTEL 211 help 212 Support for error detection and correction the Intel 213 i7 Core (Nehalem) Integrated Memory Controller that exists on 214 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 215 and Xeon 55xx processors. 216 217config EDAC_I82860 218 tristate "Intel 82860" 219 depends on PCI && X86_32 220 help 221 Support for error detection and correction on the Intel 222 82860 chipset. 223 224config EDAC_R82600 225 tristate "Radisys 82600 embedded chipset" 226 depends on PCI && X86_32 227 help 228 Support for error detection and correction on the Radisys 229 82600 embedded chipset. 230 231config EDAC_I5000 232 tristate "Intel Greencreek/Blackford chipset" 233 depends on X86 && PCI 234 depends on BROKEN 235 help 236 Support for error detection and correction the Intel 237 Greekcreek/Blackford chipsets. 238 239config EDAC_I5100 240 tristate "Intel San Clemente MCH" 241 depends on X86 && PCI 242 help 243 Support for error detection and correction the Intel 244 San Clemente MCH. 245 246config EDAC_I7300 247 tristate "Intel Clarksboro MCH" 248 depends on X86 && PCI 249 help 250 Support for error detection and correction the Intel 251 Clarksboro MCH (Intel 7300 chipset). 252 253config EDAC_SBRIDGE 254 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 255 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 256 help 257 Support for error detection and correction the Intel 258 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 259 260config EDAC_SKX 261 tristate "Intel Skylake server Integrated MC" 262 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 263 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 264 select DMI 265 select ACPI_ADXL 266 help 267 Support for error detection and correction the Intel 268 Skylake server Integrated Memory Controllers. If your 269 system has non-volatile DIMMs you should also manually 270 select CONFIG_ACPI_NFIT. 271 272config EDAC_I10NM 273 tristate "Intel 10nm server Integrated MC" 274 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 275 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 276 select DMI 277 select ACPI_ADXL 278 help 279 Support for error detection and correction the Intel 280 10nm server Integrated Memory Controllers. If your 281 system has non-volatile DIMMs you should also manually 282 select CONFIG_ACPI_NFIT. 283 284config EDAC_PND2 285 tristate "Intel Pondicherry2" 286 depends on PCI && X86_64 && X86_MCE_INTEL 287 select P2SB if X86 288 help 289 Support for error detection and correction on the Intel 290 Pondicherry2 Integrated Memory Controller. This SoC IP is 291 first used on the Apollo Lake platform and Denverton 292 micro-server but may appear on others in the future. 293 294config EDAC_IGEN6 295 tristate "Intel client SoC Integrated MC" 296 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 297 depends on X86_64 && X86_MCE_INTEL 298 help 299 Support for error detection and correction on the Intel 300 client SoC Integrated Memory Controller using In-Band ECC IP. 301 This In-Band ECC is first used on the Elkhart Lake SoC but 302 may appear on others in the future. 303 304config EDAC_MPC85XX 305 bool "Freescale MPC83xx / MPC85xx" 306 depends on FSL_SOC && EDAC=y 307 help 308 Support for error detection and correction on the Freescale 309 MPC8349, MPC8560, MPC8540, MPC8548, T4240 310 311config EDAC_LAYERSCAPE 312 tristate "Freescale Layerscape DDR" 313 depends on ARCH_LAYERSCAPE || SOC_LS1021A 314 help 315 Support for error detection and correction on Freescale memory 316 controllers on Layerscape SoCs. 317 318config EDAC_PASEMI 319 tristate "PA Semi PWRficient" 320 depends on PPC_PASEMI && PCI 321 help 322 Support for error detection and correction on PA Semi 323 PWRficient. 324 325config EDAC_CPC925 326 tristate "IBM CPC925 Memory Controller (PPC970FX)" 327 depends on PPC64 328 help 329 Support for error detection and correction on the 330 IBM CPC925 Bridge and Memory Controller, which is 331 a companion chip to the PowerPC 970 family of 332 processors. 333 334config EDAC_HIGHBANK_MC 335 tristate "Highbank Memory Controller" 336 depends on ARCH_HIGHBANK 337 help 338 Support for error detection and correction on the 339 Calxeda Highbank memory controller. 340 341config EDAC_HIGHBANK_L2 342 tristate "Highbank L2 Cache" 343 depends on ARCH_HIGHBANK 344 help 345 Support for error detection and correction on the 346 Calxeda Highbank memory controller. 347 348config EDAC_OCTEON_PC 349 tristate "Cavium Octeon Primary Caches" 350 depends on CPU_CAVIUM_OCTEON 351 help 352 Support for error detection and correction on the primary caches of 353 the cnMIPS cores of Cavium Octeon family SOCs. 354 355config EDAC_OCTEON_L2C 356 tristate "Cavium Octeon Secondary Caches (L2C)" 357 depends on CAVIUM_OCTEON_SOC 358 help 359 Support for error detection and correction on the 360 Cavium Octeon family of SOCs. 361 362config EDAC_OCTEON_LMC 363 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 364 depends on CAVIUM_OCTEON_SOC 365 help 366 Support for error detection and correction on the 367 Cavium Octeon family of SOCs. 368 369config EDAC_OCTEON_PCI 370 tristate "Cavium Octeon PCI Controller" 371 depends on PCI && CAVIUM_OCTEON_SOC 372 help 373 Support for error detection and correction on the 374 Cavium Octeon family of SOCs. 375 376config EDAC_THUNDERX 377 tristate "Cavium ThunderX EDAC" 378 depends on ARM64 379 depends on PCI 380 help 381 Support for error detection and correction on the 382 Cavium ThunderX memory controllers (LMC), Cache 383 Coherent Processor Interconnect (CCPI) and L2 cache 384 blocks (TAD, CBC, MCI). 385 386config EDAC_ALTERA 387 bool "Altera SOCFPGA ECC" 388 depends on EDAC=y && ARCH_INTEL_SOCFPGA 389 help 390 Support for error detection and correction on the 391 Altera SOCs. This is the global enable for the 392 various Altera peripherals. 393 394config EDAC_ALTERA_SDRAM 395 bool "Altera SDRAM ECC" 396 depends on EDAC_ALTERA=y 397 help 398 Support for error detection and correction on the 399 Altera SDRAM Memory for Altera SoCs. Note that the 400 preloader must initialize the SDRAM before loading 401 the kernel. 402 403config EDAC_ALTERA_L2C 404 bool "Altera L2 Cache ECC" 405 depends on EDAC_ALTERA=y && CACHE_L2X0 406 help 407 Support for error detection and correction on the 408 Altera L2 cache Memory for Altera SoCs. This option 409 requires L2 cache. 410 411config EDAC_ALTERA_OCRAM 412 bool "Altera On-Chip RAM ECC" 413 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 414 help 415 Support for error detection and correction on the 416 Altera On-Chip RAM Memory for Altera SoCs. 417 418config EDAC_ALTERA_ETHERNET 419 bool "Altera Ethernet FIFO ECC" 420 depends on EDAC_ALTERA=y 421 help 422 Support for error detection and correction on the 423 Altera Ethernet FIFO Memory for Altera SoCs. 424 425config EDAC_ALTERA_NAND 426 bool "Altera NAND FIFO ECC" 427 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 428 help 429 Support for error detection and correction on the 430 Altera NAND FIFO Memory for Altera SoCs. 431 432config EDAC_ALTERA_DMA 433 bool "Altera DMA FIFO ECC" 434 depends on EDAC_ALTERA=y && PL330_DMA=y 435 help 436 Support for error detection and correction on the 437 Altera DMA FIFO Memory for Altera SoCs. 438 439config EDAC_ALTERA_USB 440 bool "Altera USB FIFO ECC" 441 depends on EDAC_ALTERA=y && USB_DWC2 442 help 443 Support for error detection and correction on the 444 Altera USB FIFO Memory for Altera SoCs. 445 446config EDAC_ALTERA_QSPI 447 bool "Altera QSPI FIFO ECC" 448 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 449 help 450 Support for error detection and correction on the 451 Altera QSPI FIFO Memory for Altera SoCs. 452 453config EDAC_ALTERA_SDMMC 454 bool "Altera SDMMC FIFO ECC" 455 depends on EDAC_ALTERA=y && MMC_DW 456 help 457 Support for error detection and correction on the 458 Altera SDMMC FIFO Memory for Altera SoCs. 459 460config EDAC_SIFIVE 461 bool "Sifive platform EDAC driver" 462 depends on EDAC=y && SIFIVE_CCACHE 463 help 464 Support for error detection and correction on the SiFive SoCs. 465 466config EDAC_ARMADA_XP 467 bool "Marvell Armada XP DDR and L2 Cache ECC" 468 depends on MACH_MVEBU_V7 469 help 470 Support for error correction and detection on the Marvell Aramada XP 471 DDR RAM and L2 cache controllers. 472 473config EDAC_SYNOPSYS 474 tristate "Synopsys DDR Memory Controller" 475 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 476 help 477 Support for error detection and correction on the Synopsys DDR 478 memory controller. 479 480config EDAC_XGENE 481 tristate "APM X-Gene SoC" 482 depends on (ARM64 || COMPILE_TEST) 483 help 484 Support for error detection and correction on the 485 APM X-Gene family of SOCs. 486 487config EDAC_TI 488 tristate "Texas Instruments DDR3 ECC Controller" 489 depends on ARCH_KEYSTONE || SOC_DRA7XX 490 help 491 Support for error detection and correction on the TI SoCs. 492 493config EDAC_QCOM 494 tristate "QCOM EDAC Controller" 495 depends on ARCH_QCOM && QCOM_LLCC 496 help 497 Support for error detection and correction on the 498 Qualcomm Technologies, Inc. SoCs. 499 500 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 501 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 502 of Tag RAM and Data RAM. 503 504 For debugging issues having to do with stability and overall system 505 health, you should probably say 'Y' here. 506 507config EDAC_ASPEED 508 tristate "Aspeed AST BMC SoC" 509 depends on ARCH_ASPEED 510 help 511 Support for error detection and correction on the Aspeed AST BMC SoC. 512 513 First, ECC must be configured in the bootloader. Then, this driver 514 will expose error counters via the EDAC kernel framework. 515 516config EDAC_BLUEFIELD 517 tristate "Mellanox BlueField Memory ECC" 518 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 519 help 520 Support for error detection and correction on the 521 Mellanox BlueField SoCs. 522 523config EDAC_DMC520 524 tristate "ARM DMC-520 ECC" 525 depends on ARM64 526 help 527 Support for error detection and correction on the 528 SoCs with ARM DMC-520 DRAM controller. 529 530config EDAC_ZYNQMP 531 tristate "Xilinx ZynqMP OCM Controller" 532 depends on ARCH_ZYNQMP || COMPILE_TEST 533 help 534 This driver supports error detection and correction for the 535 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 536 built as a module. In that case it will be called zynqmp_edac. 537 538config EDAC_NPCM 539 tristate "Nuvoton NPCM DDR Memory Controller" 540 depends on (ARCH_NPCM || COMPILE_TEST) 541 help 542 Support for error detection and correction on the Nuvoton NPCM DDR 543 memory controller. 544 545 The memory controller supports single bit error correction, double bit 546 error detection (in-line ECC in which a section 1/8th of the memory 547 device used to store data is used for ECC storage). 548 549config EDAC_VERSAL 550 tristate "Xilinx Versal DDR Memory Controller" 551 depends on ARCH_ZYNQMP || COMPILE_TEST 552 help 553 Support for error detection and correction on the Xilinx Versal DDR 554 memory controller. 555 556 Report both single bit errors (CE) and double bit errors (UE). 557 Support injecting both correctable and uncorrectable errors 558 for debugging purposes. 559 560config EDAC_LOONGSON 561 tristate "Loongson Memory Controller" 562 depends on LOONGARCH && ACPI 563 help 564 Support for error detection and correction on the Loongson 565 family memory controller. This driver reports single bit 566 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 567 are compatible. 568 569endif # EDAC 570