1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_DEBUG 27 bool "Debugging" 28 select DEBUG_FS 29 help 30 This turns on debugging information for the entire EDAC subsystem. 31 You do so by inserting edac_module with "edac_debug_level=x." Valid 32 levels are 0-4 (from low to high) and by default it is set to 2. 33 Usually you should select 'N' here. 34 35config EDAC_DECODE_MCE 36 tristate "Decode MCEs in human-readable form (only on AMD for now)" 37 depends on CPU_SUP_AMD && X86_MCE_AMD 38 default y 39 help 40 Enable this option if you want to decode Machine Check Exceptions 41 occurring on your machine in human-readable form. 42 43 You should definitely say Y here in case you want to decode MCEs 44 which occur really early upon boot, before the module infrastructure 45 has been initialized. 46 47config EDAC_GHES 48 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 49 depends on ACPI_APEI_GHES 50 select UEFI_CPER 51 help 52 Not all machines support hardware-driven error report. Some of those 53 provide a BIOS-driven error report mechanism via ACPI, using the 54 APEI/GHES driver. By enabling this option, the error reports provided 55 by GHES are sent to userspace via the EDAC API. 56 57 When this option is enabled, it will disable the hardware-driven 58 mechanisms, if a GHES BIOS is detected, entering into the 59 "Firmware First" mode. 60 61 It should be noticed that keeping both GHES and a hardware-driven 62 error mechanism won't work well, as BIOS will race with OS, while 63 reading the error registers. So, if you want to not use "Firmware 64 first" GHES error mechanism, you should disable GHES either at 65 compilation time or by passing "ghes.disable=1" Kernel parameter 66 at boot time. 67 68 In doubt, say 'Y'. 69 70config EDAC_SCRUB 71 bool "EDAC scrub feature" 72 help 73 The EDAC scrub feature is optional and is designed to control the 74 memory scrubbers in the system. The common sysfs scrub interface 75 abstracts the control of various arbitrary scrubbing functionalities 76 into a unified set of functions. 77 Say 'y/n' to enable/disable EDAC scrub feature. 78 79config EDAC_ECS 80 bool "EDAC ECS (Error Check Scrub) feature" 81 help 82 The EDAC ECS feature is optional and is designed to control on-die 83 error check scrub (e.g., DDR5 ECS) in the system. The common sysfs 84 ECS interface abstracts the control of various ECS functionalities 85 into a unified set of functions. 86 Say 'y/n' to enable/disable EDAC ECS feature. 87 88config EDAC_MEM_REPAIR 89 bool "EDAC memory repair feature" 90 help 91 The EDAC memory repair feature is optional and is designed to control 92 the memory devices with repair features, such as Post Package Repair 93 (PPR), memory sparing etc. The common sysfs memory repair interface 94 abstracts the control of various memory repair functionalities into 95 a unified set of functions. 96 Say 'y/n' to enable/disable EDAC memory repair feature. 97 98config EDAC_AMD64 99 tristate "AMD64 (Opteron, Athlon64)" 100 depends on AMD_NB && EDAC_DECODE_MCE 101 depends on AMD_NODE 102 imply AMD_ATL 103 help 104 Support for error detection and correction of DRAM ECC errors on 105 the AMD64 families (>= K8) of memory controllers. 106 107 When EDAC_DEBUG is enabled, hardware error injection facilities 108 through sysfs are available: 109 110 AMD CPUs up to and excluding family 0x17 provide for Memory 111 Error Injection into the ECC detection circuits. The amd64_edac 112 module allows the operator/user to inject Uncorrectable and 113 Correctable errors into DRAM. 114 115 When enabled, in each of the respective memory controller directories 116 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 117 118 - inject_section (0..3, 16-byte section of 64-byte cacheline), 119 - inject_word (0..8, 16-bit word of 16-byte section), 120 - inject_ecc_vector (hex ecc vector: select bits of inject word) 121 122 In addition, there are two control files, inject_read and inject_write, 123 which trigger the DRAM ECC Read and Write respectively. 124 125config EDAC_AL_MC 126 tristate "Amazon's Annapurna Lab Memory Controller" 127 depends on (ARCH_ALPINE || COMPILE_TEST) 128 help 129 Support for error detection and correction for Amazon's Annapurna 130 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 131 132config EDAC_AMD76X 133 tristate "AMD 76x (760, 762, 768)" 134 depends on PCI && X86_32 135 help 136 Support for error detection and correction on the AMD 76x 137 series of chipsets used with the Athlon processor. 138 139config EDAC_E7XXX 140 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 141 depends on PCI && X86_32 142 help 143 Support for error detection and correction on the Intel 144 E7205, E7500, E7501 and E7505 server chipsets. 145 146config EDAC_E752X 147 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 148 depends on PCI && X86 149 help 150 Support for error detection and correction on the Intel 151 E7520, E7525, E7320 server chipsets. 152 153config EDAC_I82875P 154 tristate "Intel 82875p (D82875P, E7210)" 155 depends on PCI && X86_32 156 help 157 Support for error detection and correction on the Intel 158 DP82785P and E7210 server chipsets. 159 160config EDAC_I82975X 161 tristate "Intel 82975x (D82975x)" 162 depends on PCI && X86 163 help 164 Support for error detection and correction on the Intel 165 DP82975x server chipsets. 166 167config EDAC_I3000 168 tristate "Intel 3000/3010" 169 depends on PCI && X86 170 help 171 Support for error detection and correction on the Intel 172 3000 and 3010 server chipsets. 173 174config EDAC_I3200 175 tristate "Intel 3200" 176 depends on PCI && X86 177 help 178 Support for error detection and correction on the Intel 179 3200 and 3210 server chipsets. 180 181config EDAC_IE31200 182 tristate "Intel e312xx" 183 depends on PCI && X86 && X86_MCE_INTEL 184 help 185 Support for error detection and correction on the Intel 186 E3-1200 based DRAM controllers. 187 188config EDAC_X38 189 tristate "Intel X38" 190 depends on PCI && X86 191 help 192 Support for error detection and correction on the Intel 193 X38 server chipsets. 194 195config EDAC_I5400 196 tristate "Intel 5400 (Seaburg) chipsets" 197 depends on PCI && X86 198 help 199 Support for error detection and correction the Intel 200 i5400 MCH chipset (Seaburg). 201 202config EDAC_I7CORE 203 tristate "Intel i7 Core (Nehalem) processors" 204 depends on PCI && X86 && X86_MCE_INTEL 205 help 206 Support for error detection and correction the Intel 207 i7 Core (Nehalem) Integrated Memory Controller that exists on 208 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 209 and Xeon 55xx processors. 210 211config EDAC_I82860 212 tristate "Intel 82860" 213 depends on PCI && X86_32 214 help 215 Support for error detection and correction on the Intel 216 82860 chipset. 217 218config EDAC_R82600 219 tristate "Radisys 82600 embedded chipset" 220 depends on PCI && X86_32 221 help 222 Support for error detection and correction on the Radisys 223 82600 embedded chipset. 224 225config EDAC_I5000 226 tristate "Intel Greencreek/Blackford chipset" 227 depends on X86 && PCI 228 depends on BROKEN 229 help 230 Support for error detection and correction the Intel 231 Greekcreek/Blackford chipsets. 232 233config EDAC_I5100 234 tristate "Intel San Clemente MCH" 235 depends on X86 && PCI 236 help 237 Support for error detection and correction the Intel 238 San Clemente MCH. 239 240config EDAC_I7300 241 tristate "Intel Clarksboro MCH" 242 depends on X86 && PCI 243 help 244 Support for error detection and correction the Intel 245 Clarksboro MCH (Intel 7300 chipset). 246 247config EDAC_SBRIDGE 248 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 249 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 250 help 251 Support for error detection and correction the Intel 252 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 253 254config EDAC_SKX 255 tristate "Intel Skylake server Integrated MC" 256 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 257 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 258 select DMI 259 select ACPI_ADXL 260 help 261 Support for error detection and correction the Intel 262 Skylake server Integrated Memory Controllers. If your 263 system has non-volatile DIMMs you should also manually 264 select CONFIG_ACPI_NFIT. 265 266config EDAC_I10NM 267 tristate "Intel 10nm server Integrated MC" 268 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 269 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 270 select DMI 271 select ACPI_ADXL 272 help 273 Support for error detection and correction the Intel 274 10nm server Integrated Memory Controllers. If your 275 system has non-volatile DIMMs you should also manually 276 select CONFIG_ACPI_NFIT. 277 278config EDAC_IMH 279 tristate "Intel Integrated Memory/IO Hub MC" 280 depends on X86_64 && X86_MCE_INTEL && ACPI 281 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_IMH can't be y 282 select DMI 283 select ACPI_ADXL 284 help 285 Support for error detection and correction the Intel 286 Integrated Memory/IO Hub Memory Controller. This MC IP is 287 first used on the Diamond Rapids servers but may appear on 288 others in the future. 289 290config EDAC_PND2 291 tristate "Intel Pondicherry2" 292 depends on PCI && X86_64 && X86_MCE_INTEL 293 select P2SB if X86 294 help 295 Support for error detection and correction on the Intel 296 Pondicherry2 Integrated Memory Controller. This SoC IP is 297 first used on the Apollo Lake platform and Denverton 298 micro-server but may appear on others in the future. 299 300config EDAC_IGEN6 301 tristate "Intel client SoC Integrated MC" 302 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 303 depends on X86_64 && X86_MCE_INTEL 304 help 305 Support for error detection and correction on the Intel 306 client SoC Integrated Memory Controller using In-Band ECC IP. 307 This In-Band ECC is first used on the Elkhart Lake SoC but 308 may appear on others in the future. 309 310config EDAC_MPC85XX 311 bool "Freescale MPC83xx / MPC85xx" 312 depends on FSL_SOC && EDAC=y 313 help 314 Support for error detection and correction on the Freescale 315 MPC8349, MPC8560, MPC8540, MPC8548, T4240 316 317config EDAC_LAYERSCAPE 318 tristate "Freescale Layerscape DDR" 319 depends on ARCH_LAYERSCAPE || SOC_LS1021A 320 help 321 Support for error detection and correction on Freescale memory 322 controllers on Layerscape SoCs. 323 324config EDAC_PASEMI 325 tristate "PA Semi PWRficient" 326 depends on PPC_PASEMI && PCI 327 help 328 Support for error detection and correction on PA Semi 329 PWRficient. 330 331config EDAC_CPC925 332 tristate "IBM CPC925 Memory Controller (PPC970FX)" 333 depends on PPC64 334 help 335 Support for error detection and correction on the 336 IBM CPC925 Bridge and Memory Controller, which is 337 a companion chip to the PowerPC 970 family of 338 processors. 339 340config EDAC_HIGHBANK_MC 341 tristate "Highbank Memory Controller" 342 depends on ARCH_HIGHBANK 343 help 344 Support for error detection and correction on the 345 Calxeda Highbank memory controller. 346 347config EDAC_HIGHBANK_L2 348 tristate "Highbank L2 Cache" 349 depends on ARCH_HIGHBANK 350 help 351 Support for error detection and correction on the 352 Calxeda Highbank memory controller. 353 354config EDAC_OCTEON_PC 355 tristate "Cavium Octeon Primary Caches" 356 depends on CPU_CAVIUM_OCTEON 357 help 358 Support for error detection and correction on the primary caches of 359 the cnMIPS cores of Cavium Octeon family SOCs. 360 361config EDAC_OCTEON_L2C 362 tristate "Cavium Octeon Secondary Caches (L2C)" 363 depends on CAVIUM_OCTEON_SOC 364 help 365 Support for error detection and correction on the 366 Cavium Octeon family of SOCs. 367 368config EDAC_OCTEON_LMC 369 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 370 depends on CAVIUM_OCTEON_SOC 371 help 372 Support for error detection and correction on the 373 Cavium Octeon family of SOCs. 374 375config EDAC_OCTEON_PCI 376 tristate "Cavium Octeon PCI Controller" 377 depends on PCI && CAVIUM_OCTEON_SOC 378 help 379 Support for error detection and correction on the 380 Cavium Octeon family of SOCs. 381 382config EDAC_THUNDERX 383 tristate "Cavium ThunderX EDAC" 384 depends on ARM64 385 depends on PCI 386 help 387 Support for error detection and correction on the 388 Cavium ThunderX memory controllers (LMC), Cache 389 Coherent Processor Interconnect (CCPI) and L2 cache 390 blocks (TAD, CBC, MCI). 391 392config EDAC_ALTERA 393 bool "Altera SOCFPGA ECC" 394 depends on EDAC=y && ARCH_INTEL_SOCFPGA 395 help 396 Support for error detection and correction on the 397 Altera SOCs. This is the global enable for the 398 various Altera peripherals. 399 400config EDAC_ALTERA_SDRAM 401 bool "Altera SDRAM ECC" 402 depends on EDAC_ALTERA=y 403 help 404 Support for error detection and correction on the 405 Altera SDRAM Memory for Altera SoCs. Note that the 406 preloader must initialize the SDRAM before loading 407 the kernel. 408 409config EDAC_ALTERA_L2C 410 bool "Altera L2 Cache ECC" 411 depends on EDAC_ALTERA=y && CACHE_L2X0 412 help 413 Support for error detection and correction on the 414 Altera L2 cache Memory for Altera SoCs. This option 415 requires L2 cache. 416 417config EDAC_ALTERA_OCRAM 418 bool "Altera On-Chip RAM ECC" 419 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 420 help 421 Support for error detection and correction on the 422 Altera On-Chip RAM Memory for Altera SoCs. 423 424config EDAC_ALTERA_ETHERNET 425 bool "Altera Ethernet FIFO ECC" 426 depends on EDAC_ALTERA=y 427 help 428 Support for error detection and correction on the 429 Altera Ethernet FIFO Memory for Altera SoCs. 430 431config EDAC_ALTERA_NAND 432 bool "Altera NAND FIFO ECC" 433 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 434 help 435 Support for error detection and correction on the 436 Altera NAND FIFO Memory for Altera SoCs. 437 438config EDAC_ALTERA_DMA 439 bool "Altera DMA FIFO ECC" 440 depends on EDAC_ALTERA=y && PL330_DMA=y 441 help 442 Support for error detection and correction on the 443 Altera DMA FIFO Memory for Altera SoCs. 444 445config EDAC_ALTERA_USB 446 bool "Altera USB FIFO ECC" 447 depends on EDAC_ALTERA=y && USB_DWC2 448 help 449 Support for error detection and correction on the 450 Altera USB FIFO Memory for Altera SoCs. 451 452config EDAC_ALTERA_QSPI 453 bool "Altera QSPI FIFO ECC" 454 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 455 help 456 Support for error detection and correction on the 457 Altera QSPI FIFO Memory for Altera SoCs. 458 459config EDAC_ALTERA_SDMMC 460 bool "Altera SDMMC FIFO ECC" 461 depends on EDAC_ALTERA=y && MMC_DW 462 help 463 Support for error detection and correction on the 464 Altera SDMMC FIFO Memory for Altera SoCs. 465 466config EDAC_SIFIVE 467 bool "Sifive platform EDAC driver" 468 depends on EDAC=y && SIFIVE_CCACHE 469 help 470 Support for error detection and correction on the SiFive SoCs. 471 472config EDAC_ARMADA_XP 473 bool "Marvell Armada XP DDR and L2 Cache ECC" 474 depends on MACH_MVEBU_V7 475 help 476 Support for error correction and detection on the Marvell Aramada XP 477 DDR RAM and L2 cache controllers. 478 479config EDAC_SYNOPSYS 480 tristate "Synopsys DDR Memory Controller" 481 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 482 help 483 Support for error detection and correction on the Synopsys DDR 484 memory controller. 485 486config EDAC_XGENE 487 tristate "APM X-Gene SoC" 488 depends on (ARM64 || COMPILE_TEST) 489 help 490 Support for error detection and correction on the 491 APM X-Gene family of SOCs. 492 493config EDAC_TI 494 tristate "Texas Instruments DDR3 ECC Controller" 495 depends on ARCH_KEYSTONE || SOC_DRA7XX 496 help 497 Support for error detection and correction on the TI SoCs. 498 499config EDAC_QCOM 500 tristate "QCOM EDAC Controller" 501 depends on ARCH_QCOM && QCOM_LLCC 502 help 503 Support for error detection and correction on the 504 Qualcomm Technologies, Inc. SoCs. 505 506 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 507 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 508 of Tag RAM and Data RAM. 509 510 For debugging issues having to do with stability and overall system 511 health, you should probably say 'Y' here. 512 513config EDAC_ASPEED 514 tristate "Aspeed AST BMC SoC" 515 depends on ARCH_ASPEED 516 help 517 Support for error detection and correction on the Aspeed AST BMC SoC. 518 519 First, ECC must be configured in the bootloader. Then, this driver 520 will expose error counters via the EDAC kernel framework. 521 522config EDAC_BLUEFIELD 523 tristate "Mellanox BlueField Memory ECC" 524 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 525 help 526 Support for error detection and correction on the 527 Mellanox BlueField SoCs. 528 529config EDAC_DMC520 530 tristate "ARM DMC-520 ECC" 531 depends on ARM64 532 help 533 Support for error detection and correction on the 534 SoCs with ARM DMC-520 DRAM controller. 535 536config EDAC_ZYNQMP 537 tristate "Xilinx ZynqMP OCM Controller" 538 depends on ARCH_ZYNQMP || COMPILE_TEST 539 help 540 This driver supports error detection and correction for the 541 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 542 built as a module. In that case it will be called zynqmp_edac. 543 544config EDAC_NPCM 545 tristate "Nuvoton NPCM DDR Memory Controller" 546 depends on (ARCH_NPCM || COMPILE_TEST) 547 help 548 Support for error detection and correction on the Nuvoton NPCM DDR 549 memory controller. 550 551 The memory controller supports single bit error correction, double bit 552 error detection (in-line ECC in which a section 1/8th of the memory 553 device used to store data is used for ECC storage). 554 555config EDAC_VERSAL 556 tristate "Xilinx Versal DDR Memory Controller" 557 depends on ARCH_ZYNQMP || COMPILE_TEST 558 help 559 Support for error detection and correction on the Xilinx Versal DDR 560 memory controller. 561 562 Report both single bit errors (CE) and double bit errors (UE). 563 Support injecting both correctable and uncorrectable errors 564 for debugging purposes. 565 566config EDAC_LOONGSON 567 tristate "Loongson Memory Controller" 568 depends on LOONGARCH && ACPI 569 help 570 Support for error detection and correction on the Loongson 571 family memory controller. This driver reports single bit 572 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 573 are compatible. 574 575config EDAC_CORTEX_A72 576 tristate "ARM Cortex A72" 577 depends on ARM64 578 help 579 Support for L1/L2 cache error detection for ARM Cortex A72 processor. 580 The detected and reported errors are from reading CPU/L2 memory error 581 syndrome registers. 582 583config EDAC_VERSALNET 584 tristate "AMD VersalNET DDR Controller" 585 depends on CDX_CONTROLLER && ARCH_ZYNQMP 586 help 587 Support for single bit error correction, double bit error detection 588 and other system errors from various IP subsystems like RPU, NOCs, 589 HNICX, PL on the AMD Versal NET DDR memory controller. 590 591endif # EDAC 592