1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 help 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES 58 select UEFI_CPER 59 help 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 62 APEI/GHES driver. By enabling this option, the error reports provided 63 by GHES are sent to userspace via the EDAC API. 64 65 When this option is enabled, it will disable the hardware-driven 66 mechanisms, if a GHES BIOS is detected, entering into the 67 "Firmware First" mode. 68 69 It should be noticed that keeping both GHES and a hardware-driven 70 error mechanism won't work well, as BIOS will race with OS, while 71 reading the error registers. So, if you want to not use "Firmware 72 first" GHES error mechanism, you should disable GHES either at 73 compilation time or by passing "ghes.disable=1" Kernel parameter 74 at boot time. 75 76 In doubt, say 'Y'. 77 78config EDAC_AMD64 79 tristate "AMD64 (Opteron, Athlon64)" 80 depends on AMD_NB && EDAC_DECODE_MCE 81 imply AMD_ATL 82 help 83 Support for error detection and correction of DRAM ECC errors on 84 the AMD64 families (>= K8) of memory controllers. 85 86 When EDAC_DEBUG is enabled, hardware error injection facilities 87 through sysfs are available: 88 89 AMD CPUs up to and excluding family 0x17 provide for Memory 90 Error Injection into the ECC detection circuits. The amd64_edac 91 module allows the operator/user to inject Uncorrectable and 92 Correctable errors into DRAM. 93 94 When enabled, in each of the respective memory controller directories 95 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 96 97 - inject_section (0..3, 16-byte section of 64-byte cacheline), 98 - inject_word (0..8, 16-bit word of 16-byte section), 99 - inject_ecc_vector (hex ecc vector: select bits of inject word) 100 101 In addition, there are two control files, inject_read and inject_write, 102 which trigger the DRAM ECC Read and Write respectively. 103 104config EDAC_AL_MC 105 tristate "Amazon's Annapurna Lab Memory Controller" 106 depends on (ARCH_ALPINE || COMPILE_TEST) 107 help 108 Support for error detection and correction for Amazon's Annapurna 109 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 110 111config EDAC_AMD76X 112 tristate "AMD 76x (760, 762, 768)" 113 depends on PCI && X86_32 114 help 115 Support for error detection and correction on the AMD 76x 116 series of chipsets used with the Athlon processor. 117 118config EDAC_E7XXX 119 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 120 depends on PCI && X86_32 121 help 122 Support for error detection and correction on the Intel 123 E7205, E7500, E7501 and E7505 server chipsets. 124 125config EDAC_E752X 126 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 127 depends on PCI && X86 128 help 129 Support for error detection and correction on the Intel 130 E7520, E7525, E7320 server chipsets. 131 132config EDAC_I82443BXGX 133 tristate "Intel 82443BX/GX (440BX/GX)" 134 depends on PCI && X86_32 135 depends on BROKEN 136 help 137 Support for error detection and correction on the Intel 138 82443BX/GX memory controllers (440BX/GX chipsets). 139 140config EDAC_I82875P 141 tristate "Intel 82875p (D82875P, E7210)" 142 depends on PCI && X86_32 143 help 144 Support for error detection and correction on the Intel 145 DP82785P and E7210 server chipsets. 146 147config EDAC_I82975X 148 tristate "Intel 82975x (D82975x)" 149 depends on PCI && X86 150 help 151 Support for error detection and correction on the Intel 152 DP82975x server chipsets. 153 154config EDAC_I3000 155 tristate "Intel 3000/3010" 156 depends on PCI && X86 157 help 158 Support for error detection and correction on the Intel 159 3000 and 3010 server chipsets. 160 161config EDAC_I3200 162 tristate "Intel 3200" 163 depends on PCI && X86 164 help 165 Support for error detection and correction on the Intel 166 3200 and 3210 server chipsets. 167 168config EDAC_IE31200 169 tristate "Intel e312xx" 170 depends on PCI && X86 171 help 172 Support for error detection and correction on the Intel 173 E3-1200 based DRAM controllers. 174 175config EDAC_X38 176 tristate "Intel X38" 177 depends on PCI && X86 178 help 179 Support for error detection and correction on the Intel 180 X38 server chipsets. 181 182config EDAC_I5400 183 tristate "Intel 5400 (Seaburg) chipsets" 184 depends on PCI && X86 185 help 186 Support for error detection and correction the Intel 187 i5400 MCH chipset (Seaburg). 188 189config EDAC_I7CORE 190 tristate "Intel i7 Core (Nehalem) processors" 191 depends on PCI && X86 && X86_MCE_INTEL 192 help 193 Support for error detection and correction the Intel 194 i7 Core (Nehalem) Integrated Memory Controller that exists on 195 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 196 and Xeon 55xx processors. 197 198config EDAC_I82860 199 tristate "Intel 82860" 200 depends on PCI && X86_32 201 help 202 Support for error detection and correction on the Intel 203 82860 chipset. 204 205config EDAC_R82600 206 tristate "Radisys 82600 embedded chipset" 207 depends on PCI && X86_32 208 help 209 Support for error detection and correction on the Radisys 210 82600 embedded chipset. 211 212config EDAC_I5000 213 tristate "Intel Greencreek/Blackford chipset" 214 depends on X86 && PCI 215 depends on BROKEN 216 help 217 Support for error detection and correction the Intel 218 Greekcreek/Blackford chipsets. 219 220config EDAC_I5100 221 tristate "Intel San Clemente MCH" 222 depends on X86 && PCI 223 help 224 Support for error detection and correction the Intel 225 San Clemente MCH. 226 227config EDAC_I7300 228 tristate "Intel Clarksboro MCH" 229 depends on X86 && PCI 230 help 231 Support for error detection and correction the Intel 232 Clarksboro MCH (Intel 7300 chipset). 233 234config EDAC_SBRIDGE 235 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 236 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 237 help 238 Support for error detection and correction the Intel 239 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 240 241config EDAC_SKX 242 tristate "Intel Skylake server Integrated MC" 243 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 244 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 245 select DMI 246 select ACPI_ADXL 247 help 248 Support for error detection and correction the Intel 249 Skylake server Integrated Memory Controllers. If your 250 system has non-volatile DIMMs you should also manually 251 select CONFIG_ACPI_NFIT. 252 253config EDAC_I10NM 254 tristate "Intel 10nm server Integrated MC" 255 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 256 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 257 select DMI 258 select ACPI_ADXL 259 help 260 Support for error detection and correction the Intel 261 10nm server Integrated Memory Controllers. If your 262 system has non-volatile DIMMs you should also manually 263 select CONFIG_ACPI_NFIT. 264 265config EDAC_PND2 266 tristate "Intel Pondicherry2" 267 depends on PCI && X86_64 && X86_MCE_INTEL 268 select P2SB if X86 269 help 270 Support for error detection and correction on the Intel 271 Pondicherry2 Integrated Memory Controller. This SoC IP is 272 first used on the Apollo Lake platform and Denverton 273 micro-server but may appear on others in the future. 274 275config EDAC_IGEN6 276 tristate "Intel client SoC Integrated MC" 277 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 278 depends on X86_64 && X86_MCE_INTEL 279 help 280 Support for error detection and correction on the Intel 281 client SoC Integrated Memory Controller using In-Band ECC IP. 282 This In-Band ECC is first used on the Elkhart Lake SoC but 283 may appear on others in the future. 284 285config EDAC_MPC85XX 286 bool "Freescale MPC83xx / MPC85xx" 287 depends on FSL_SOC && EDAC=y 288 help 289 Support for error detection and correction on the Freescale 290 MPC8349, MPC8560, MPC8540, MPC8548, T4240 291 292config EDAC_LAYERSCAPE 293 tristate "Freescale Layerscape DDR" 294 depends on ARCH_LAYERSCAPE || SOC_LS1021A 295 help 296 Support for error detection and correction on Freescale memory 297 controllers on Layerscape SoCs. 298 299config EDAC_PASEMI 300 tristate "PA Semi PWRficient" 301 depends on PPC_PASEMI && PCI 302 help 303 Support for error detection and correction on PA Semi 304 PWRficient. 305 306config EDAC_CELL 307 tristate "Cell Broadband Engine memory controller" 308 depends on PPC_CELL_COMMON 309 help 310 Support for error detection and correction on the 311 Cell Broadband Engine internal memory controller 312 on platform without a hypervisor 313 314config EDAC_PPC4XX 315 tristate "PPC4xx IBM DDR2 Memory Controller" 316 depends on 4xx 317 help 318 This enables support for EDAC on the ECC memory used 319 with the IBM DDR2 memory controller found in various 320 PowerPC 4xx embedded processors such as the 405EX[r], 321 440SP, 440SPe, 460EX, 460GT and 460SX. 322 323config EDAC_AMD8131 324 tristate "AMD8131 HyperTransport PCI-X Tunnel" 325 depends on PCI && PPC_MAPLE 326 help 327 Support for error detection and correction on the 328 AMD8131 HyperTransport PCI-X Tunnel chip. 329 Note, add more Kconfig dependency if it's adopted 330 on some machine other than Maple. 331 332config EDAC_AMD8111 333 tristate "AMD8111 HyperTransport I/O Hub" 334 depends on PCI && PPC_MAPLE 335 help 336 Support for error detection and correction on the 337 AMD8111 HyperTransport I/O Hub chip. 338 Note, add more Kconfig dependency if it's adopted 339 on some machine other than Maple. 340 341config EDAC_CPC925 342 tristate "IBM CPC925 Memory Controller (PPC970FX)" 343 depends on PPC64 344 help 345 Support for error detection and correction on the 346 IBM CPC925 Bridge and Memory Controller, which is 347 a companion chip to the PowerPC 970 family of 348 processors. 349 350config EDAC_HIGHBANK_MC 351 tristate "Highbank Memory Controller" 352 depends on ARCH_HIGHBANK 353 help 354 Support for error detection and correction on the 355 Calxeda Highbank memory controller. 356 357config EDAC_HIGHBANK_L2 358 tristate "Highbank L2 Cache" 359 depends on ARCH_HIGHBANK 360 help 361 Support for error detection and correction on the 362 Calxeda Highbank memory controller. 363 364config EDAC_OCTEON_PC 365 tristate "Cavium Octeon Primary Caches" 366 depends on CPU_CAVIUM_OCTEON 367 help 368 Support for error detection and correction on the primary caches of 369 the cnMIPS cores of Cavium Octeon family SOCs. 370 371config EDAC_OCTEON_L2C 372 tristate "Cavium Octeon Secondary Caches (L2C)" 373 depends on CAVIUM_OCTEON_SOC 374 help 375 Support for error detection and correction on the 376 Cavium Octeon family of SOCs. 377 378config EDAC_OCTEON_LMC 379 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 380 depends on CAVIUM_OCTEON_SOC 381 help 382 Support for error detection and correction on the 383 Cavium Octeon family of SOCs. 384 385config EDAC_OCTEON_PCI 386 tristate "Cavium Octeon PCI Controller" 387 depends on PCI && CAVIUM_OCTEON_SOC 388 help 389 Support for error detection and correction on the 390 Cavium Octeon family of SOCs. 391 392config EDAC_THUNDERX 393 tristate "Cavium ThunderX EDAC" 394 depends on ARM64 395 depends on PCI 396 help 397 Support for error detection and correction on the 398 Cavium ThunderX memory controllers (LMC), Cache 399 Coherent Processor Interconnect (CCPI) and L2 cache 400 blocks (TAD, CBC, MCI). 401 402config EDAC_ALTERA 403 bool "Altera SOCFPGA ECC" 404 depends on EDAC=y && ARCH_INTEL_SOCFPGA 405 help 406 Support for error detection and correction on the 407 Altera SOCs. This is the global enable for the 408 various Altera peripherals. 409 410config EDAC_ALTERA_SDRAM 411 bool "Altera SDRAM ECC" 412 depends on EDAC_ALTERA=y 413 help 414 Support for error detection and correction on the 415 Altera SDRAM Memory for Altera SoCs. Note that the 416 preloader must initialize the SDRAM before loading 417 the kernel. 418 419config EDAC_ALTERA_L2C 420 bool "Altera L2 Cache ECC" 421 depends on EDAC_ALTERA=y && CACHE_L2X0 422 help 423 Support for error detection and correction on the 424 Altera L2 cache Memory for Altera SoCs. This option 425 requires L2 cache. 426 427config EDAC_ALTERA_OCRAM 428 bool "Altera On-Chip RAM ECC" 429 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 430 help 431 Support for error detection and correction on the 432 Altera On-Chip RAM Memory for Altera SoCs. 433 434config EDAC_ALTERA_ETHERNET 435 bool "Altera Ethernet FIFO ECC" 436 depends on EDAC_ALTERA=y 437 help 438 Support for error detection and correction on the 439 Altera Ethernet FIFO Memory for Altera SoCs. 440 441config EDAC_ALTERA_NAND 442 bool "Altera NAND FIFO ECC" 443 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 444 help 445 Support for error detection and correction on the 446 Altera NAND FIFO Memory for Altera SoCs. 447 448config EDAC_ALTERA_DMA 449 bool "Altera DMA FIFO ECC" 450 depends on EDAC_ALTERA=y && PL330_DMA=y 451 help 452 Support for error detection and correction on the 453 Altera DMA FIFO Memory for Altera SoCs. 454 455config EDAC_ALTERA_USB 456 bool "Altera USB FIFO ECC" 457 depends on EDAC_ALTERA=y && USB_DWC2 458 help 459 Support for error detection and correction on the 460 Altera USB FIFO Memory for Altera SoCs. 461 462config EDAC_ALTERA_QSPI 463 bool "Altera QSPI FIFO ECC" 464 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 465 help 466 Support for error detection and correction on the 467 Altera QSPI FIFO Memory for Altera SoCs. 468 469config EDAC_ALTERA_SDMMC 470 bool "Altera SDMMC FIFO ECC" 471 depends on EDAC_ALTERA=y && MMC_DW 472 help 473 Support for error detection and correction on the 474 Altera SDMMC FIFO Memory for Altera SoCs. 475 476config EDAC_SIFIVE 477 bool "Sifive platform EDAC driver" 478 depends on EDAC=y && SIFIVE_CCACHE 479 help 480 Support for error detection and correction on the SiFive SoCs. 481 482config EDAC_ARMADA_XP 483 bool "Marvell Armada XP DDR and L2 Cache ECC" 484 depends on MACH_MVEBU_V7 485 help 486 Support for error correction and detection on the Marvell Aramada XP 487 DDR RAM and L2 cache controllers. 488 489config EDAC_SYNOPSYS 490 tristate "Synopsys DDR Memory Controller" 491 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 492 help 493 Support for error detection and correction on the Synopsys DDR 494 memory controller. 495 496config EDAC_XGENE 497 tristate "APM X-Gene SoC" 498 depends on (ARM64 || COMPILE_TEST) 499 help 500 Support for error detection and correction on the 501 APM X-Gene family of SOCs. 502 503config EDAC_TI 504 tristate "Texas Instruments DDR3 ECC Controller" 505 depends on ARCH_KEYSTONE || SOC_DRA7XX 506 help 507 Support for error detection and correction on the TI SoCs. 508 509config EDAC_QCOM 510 tristate "QCOM EDAC Controller" 511 depends on ARCH_QCOM && QCOM_LLCC 512 help 513 Support for error detection and correction on the 514 Qualcomm Technologies, Inc. SoCs. 515 516 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 517 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 518 of Tag RAM and Data RAM. 519 520 For debugging issues having to do with stability and overall system 521 health, you should probably say 'Y' here. 522 523config EDAC_ASPEED 524 tristate "Aspeed AST BMC SoC" 525 depends on ARCH_ASPEED 526 help 527 Support for error detection and correction on the Aspeed AST BMC SoC. 528 529 First, ECC must be configured in the bootloader. Then, this driver 530 will expose error counters via the EDAC kernel framework. 531 532config EDAC_BLUEFIELD 533 tristate "Mellanox BlueField Memory ECC" 534 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 535 help 536 Support for error detection and correction on the 537 Mellanox BlueField SoCs. 538 539config EDAC_DMC520 540 tristate "ARM DMC-520 ECC" 541 depends on ARM64 542 help 543 Support for error detection and correction on the 544 SoCs with ARM DMC-520 DRAM controller. 545 546config EDAC_ZYNQMP 547 tristate "Xilinx ZynqMP OCM Controller" 548 depends on ARCH_ZYNQMP || COMPILE_TEST 549 help 550 This driver supports error detection and correction for the 551 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 552 built as a module. In that case it will be called zynqmp_edac. 553 554config EDAC_NPCM 555 tristate "Nuvoton NPCM DDR Memory Controller" 556 depends on (ARCH_NPCM || COMPILE_TEST) 557 help 558 Support for error detection and correction on the Nuvoton NPCM DDR 559 memory controller. 560 561 The memory controller supports single bit error correction, double bit 562 error detection (in-line ECC in which a section 1/8th of the memory 563 device used to store data is used for ECC storage). 564 565config EDAC_VERSAL 566 tristate "Xilinx Versal DDR Memory Controller" 567 depends on ARCH_ZYNQMP || COMPILE_TEST 568 help 569 Support for error detection and correction on the Xilinx Versal DDR 570 memory controller. 571 572 Report both single bit errors (CE) and double bit errors (UE). 573 Support injecting both correctable and uncorrectable errors 574 for debugging purposes. 575 576 577endif # EDAC 578