xref: /linux/drivers/edac/Kconfig (revision 2ba9268dd603d23e17643437b2246acb6844953b)
1#
2#	EDAC Kconfig
3#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4#	Licensed and distributed under the GPL
5#
6
7config EDAC_SUPPORT
8	bool
9
10menuconfig EDAC
11	bool "EDAC (Error Detection And Correction) reporting"
12	depends on HAS_IOMEM
13	depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
14	help
15	  EDAC is designed to report errors in the core system.
16	  These are low-level errors that are reported in the CPU or
17	  supporting chipset or other subsystems:
18	  memory errors, cache errors, PCI errors, thermal throttling, etc..
19	  If unsure, select 'Y'.
20
21	  If this code is reporting problems on your system, please
22	  see the EDAC project web pages for more information at:
23
24	  <http://bluesmoke.sourceforge.net/>
25
26	  and:
27
28	  <http://buttersideup.com/edacwiki>
29
30	  There is also a mailing list for the EDAC project, which can
31	  be found via the sourceforge page.
32
33if EDAC
34
35config EDAC_LEGACY_SYSFS
36	bool "EDAC legacy sysfs"
37	default y
38	help
39	  Enable the compatibility sysfs nodes.
40	  Use 'Y' if your edac utilities aren't ported to work with the newer
41	  structures.
42
43config EDAC_DEBUG
44	bool "Debugging"
45	help
46	  This turns on debugging information for the entire EDAC subsystem.
47	  You do so by inserting edac_module with "edac_debug_level=x." Valid
48	  levels are 0-4 (from low to high) and by default it is set to 2.
49	  Usually you should select 'N' here.
50
51config EDAC_DECODE_MCE
52	tristate "Decode MCEs in human-readable form (only on AMD for now)"
53	depends on CPU_SUP_AMD && X86_MCE_AMD
54	default y
55	---help---
56	  Enable this option if you want to decode Machine Check Exceptions
57	  occurring on your machine in human-readable form.
58
59	  You should definitely say Y here in case you want to decode MCEs
60	  which occur really early upon boot, before the module infrastructure
61	  has been initialized.
62
63config EDAC_MCE_INJ
64	tristate "Simple MCE injection interface"
65	depends on EDAC_DECODE_MCE && DEBUG_FS
66	default n
67	help
68	  This is a simple debugfs interface to inject MCEs and test different
69	  aspects of the MCE handling code.
70
71	  WARNING: Do not even assume this interface is staying stable!
72
73config EDAC_MM_EDAC
74	tristate "Main Memory EDAC (Error Detection And Correction) reporting"
75	select RAS
76	help
77	  Some systems are able to detect and correct errors in main
78	  memory.  EDAC can report statistics on memory error
79	  detection and correction (EDAC - or commonly referred to ECC
80	  errors).  EDAC will also try to decode where these errors
81	  occurred so that a particular failing memory module can be
82	  replaced.  If unsure, select 'Y'.
83
84config EDAC_GHES
85	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
86	depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
87	default y
88	help
89	  Not all machines support hardware-driven error report. Some of those
90	  provide a BIOS-driven error report mechanism via ACPI, using the
91	  APEI/GHES driver. By enabling this option, the error reports provided
92	  by GHES are sent to userspace via the EDAC API.
93
94	  When this option is enabled, it will disable the hardware-driven
95	  mechanisms, if a GHES BIOS is detected, entering into the
96	  "Firmware First" mode.
97
98	  It should be noticed that keeping both GHES and a hardware-driven
99	  error mechanism won't work well, as BIOS will race with OS, while
100	  reading the error registers. So, if you want to not use "Firmware
101	  first" GHES error mechanism, you should disable GHES either at
102	  compilation time or by passing "ghes.disable=1" Kernel parameter
103	  at boot time.
104
105	  In doubt, say 'Y'.
106
107config EDAC_AMD64
108	tristate "AMD64 (Opteron, Athlon64)"
109	depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
110	help
111	  Support for error detection and correction of DRAM ECC errors on
112	  the AMD64 families (>= K8) of memory controllers.
113
114config EDAC_AMD64_ERROR_INJECTION
115	bool "Sysfs HW Error injection facilities"
116	depends on EDAC_AMD64
117	help
118	  Recent Opterons (Family 10h and later) provide for Memory Error
119	  Injection into the ECC detection circuits. The amd64_edac module
120	  allows the operator/user to inject Uncorrectable and Correctable
121	  errors into DRAM.
122
123	  When enabled, in each of the respective memory controller directories
124	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:
125
126	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
127	  - inject_word (0..8, 16-bit word of 16-byte section),
128	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
129
130	  In addition, there are two control files, inject_read and inject_write,
131	  which trigger the DRAM ECC Read and Write respectively.
132
133config EDAC_AMD76X
134	tristate "AMD 76x (760, 762, 768)"
135	depends on EDAC_MM_EDAC && PCI && X86_32
136	help
137	  Support for error detection and correction on the AMD 76x
138	  series of chipsets used with the Athlon processor.
139
140config EDAC_E7XXX
141	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
142	depends on EDAC_MM_EDAC && PCI && X86_32
143	help
144	  Support for error detection and correction on the Intel
145	  E7205, E7500, E7501 and E7505 server chipsets.
146
147config EDAC_E752X
148	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
149	depends on EDAC_MM_EDAC && PCI && X86
150	help
151	  Support for error detection and correction on the Intel
152	  E7520, E7525, E7320 server chipsets.
153
154config EDAC_I82443BXGX
155	tristate "Intel 82443BX/GX (440BX/GX)"
156	depends on EDAC_MM_EDAC && PCI && X86_32
157	depends on BROKEN
158	help
159	  Support for error detection and correction on the Intel
160	  82443BX/GX memory controllers (440BX/GX chipsets).
161
162config EDAC_I82875P
163	tristate "Intel 82875p (D82875P, E7210)"
164	depends on EDAC_MM_EDAC && PCI && X86_32
165	help
166	  Support for error detection and correction on the Intel
167	  DP82785P and E7210 server chipsets.
168
169config EDAC_I82975X
170	tristate "Intel 82975x (D82975x)"
171	depends on EDAC_MM_EDAC && PCI && X86
172	help
173	  Support for error detection and correction on the Intel
174	  DP82975x server chipsets.
175
176config EDAC_I3000
177	tristate "Intel 3000/3010"
178	depends on EDAC_MM_EDAC && PCI && X86
179	help
180	  Support for error detection and correction on the Intel
181	  3000 and 3010 server chipsets.
182
183config EDAC_I3200
184	tristate "Intel 3200"
185	depends on EDAC_MM_EDAC && PCI && X86
186	help
187	  Support for error detection and correction on the Intel
188	  3200 and 3210 server chipsets.
189
190config EDAC_IE31200
191	tristate "Intel e312xx"
192	depends on EDAC_MM_EDAC && PCI && X86
193	help
194	  Support for error detection and correction on the Intel
195	  E3-1200 based DRAM controllers.
196
197config EDAC_X38
198	tristate "Intel X38"
199	depends on EDAC_MM_EDAC && PCI && X86
200	help
201	  Support for error detection and correction on the Intel
202	  X38 server chipsets.
203
204config EDAC_I5400
205	tristate "Intel 5400 (Seaburg) chipsets"
206	depends on EDAC_MM_EDAC && PCI && X86
207	help
208	  Support for error detection and correction the Intel
209	  i5400 MCH chipset (Seaburg).
210
211config EDAC_I7CORE
212	tristate "Intel i7 Core (Nehalem) processors"
213	depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
214	help
215	  Support for error detection and correction the Intel
216	  i7 Core (Nehalem) Integrated Memory Controller that exists on
217	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
218	  and Xeon 55xx processors.
219
220config EDAC_I82860
221	tristate "Intel 82860"
222	depends on EDAC_MM_EDAC && PCI && X86_32
223	help
224	  Support for error detection and correction on the Intel
225	  82860 chipset.
226
227config EDAC_R82600
228	tristate "Radisys 82600 embedded chipset"
229	depends on EDAC_MM_EDAC && PCI && X86_32
230	help
231	  Support for error detection and correction on the Radisys
232	  82600 embedded chipset.
233
234config EDAC_I5000
235	tristate "Intel Greencreek/Blackford chipset"
236	depends on EDAC_MM_EDAC && X86 && PCI
237	help
238	  Support for error detection and correction the Intel
239	  Greekcreek/Blackford chipsets.
240
241config EDAC_I5100
242	tristate "Intel San Clemente MCH"
243	depends on EDAC_MM_EDAC && X86 && PCI
244	help
245	  Support for error detection and correction the Intel
246	  San Clemente MCH.
247
248config EDAC_I7300
249	tristate "Intel Clarksboro MCH"
250	depends on EDAC_MM_EDAC && X86 && PCI
251	help
252	  Support for error detection and correction the Intel
253	  Clarksboro MCH (Intel 7300 chipset).
254
255config EDAC_SBRIDGE
256	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
257	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
258	depends on PCI_MMCONFIG
259	help
260	  Support for error detection and correction the Intel
261	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
262
263config EDAC_MPC85XX
264	tristate "Freescale MPC83xx / MPC85xx"
265	depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
266	help
267	  Support for error detection and correction on the Freescale
268	  MPC8349, MPC8560, MPC8540, MPC8548
269
270config EDAC_MV64X60
271	tristate "Marvell MV64x60"
272	depends on EDAC_MM_EDAC && MV64X60
273	help
274	  Support for error detection and correction on the Marvell
275	  MV64360 and MV64460 chipsets.
276
277config EDAC_PASEMI
278	tristate "PA Semi PWRficient"
279	depends on EDAC_MM_EDAC && PCI
280	depends on PPC_PASEMI
281	help
282	  Support for error detection and correction on PA Semi
283	  PWRficient.
284
285config EDAC_CELL
286	tristate "Cell Broadband Engine memory controller"
287	depends on EDAC_MM_EDAC && PPC_CELL_COMMON
288	help
289	  Support for error detection and correction on the
290	  Cell Broadband Engine internal memory controller
291	  on platform without a hypervisor
292
293config EDAC_PPC4XX
294	tristate "PPC4xx IBM DDR2 Memory Controller"
295	depends on EDAC_MM_EDAC && 4xx
296	help
297	  This enables support for EDAC on the ECC memory used
298	  with the IBM DDR2 memory controller found in various
299	  PowerPC 4xx embedded processors such as the 405EX[r],
300	  440SP, 440SPe, 460EX, 460GT and 460SX.
301
302config EDAC_AMD8131
303	tristate "AMD8131 HyperTransport PCI-X Tunnel"
304	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
305	help
306	  Support for error detection and correction on the
307	  AMD8131 HyperTransport PCI-X Tunnel chip.
308	  Note, add more Kconfig dependency if it's adopted
309	  on some machine other than Maple.
310
311config EDAC_AMD8111
312	tristate "AMD8111 HyperTransport I/O Hub"
313	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
314	help
315	  Support for error detection and correction on the
316	  AMD8111 HyperTransport I/O Hub chip.
317	  Note, add more Kconfig dependency if it's adopted
318	  on some machine other than Maple.
319
320config EDAC_CPC925
321	tristate "IBM CPC925 Memory Controller (PPC970FX)"
322	depends on EDAC_MM_EDAC && PPC64
323	help
324	  Support for error detection and correction on the
325	  IBM CPC925 Bridge and Memory Controller, which is
326	  a companion chip to the PowerPC 970 family of
327	  processors.
328
329config EDAC_TILE
330	tristate "Tilera Memory Controller"
331	depends on EDAC_MM_EDAC && TILE
332	default y
333	help
334	  Support for error detection and correction on the
335	  Tilera memory controller.
336
337config EDAC_HIGHBANK_MC
338	tristate "Highbank Memory Controller"
339	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
340	help
341	  Support for error detection and correction on the
342	  Calxeda Highbank memory controller.
343
344config EDAC_HIGHBANK_L2
345	tristate "Highbank L2 Cache"
346	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
347	help
348	  Support for error detection and correction on the
349	  Calxeda Highbank memory controller.
350
351config EDAC_OCTEON_PC
352	tristate "Cavium Octeon Primary Caches"
353	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
354	help
355	  Support for error detection and correction on the primary caches of
356	  the cnMIPS cores of Cavium Octeon family SOCs.
357
358config EDAC_OCTEON_L2C
359	tristate "Cavium Octeon Secondary Caches (L2C)"
360	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
361	help
362	  Support for error detection and correction on the
363	  Cavium Octeon family of SOCs.
364
365config EDAC_OCTEON_LMC
366	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
367	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
368	help
369	  Support for error detection and correction on the
370	  Cavium Octeon family of SOCs.
371
372config EDAC_OCTEON_PCI
373	tristate "Cavium Octeon PCI Controller"
374	depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
375	help
376	  Support for error detection and correction on the
377	  Cavium Octeon family of SOCs.
378
379config EDAC_ALTERA_MC
380	tristate "Altera SDRAM Memory Controller EDAC"
381	depends on EDAC_MM_EDAC && ARCH_SOCFPGA
382	help
383	  Support for error detection and correction on the
384	  Altera SDRAM memory controller. Note that the
385	  preloader must initialize the SDRAM before loading
386	  the kernel.
387
388config EDAC_SYNOPSYS
389	tristate "Synopsys DDR Memory Controller"
390	depends on EDAC_MM_EDAC && ARCH_ZYNQ
391	help
392	  Support for error detection and correction on the Synopsys DDR
393	  memory controller.
394
395endif # EDAC
396