1da9bb1d2SAlan Cox# 2da9bb1d2SAlan Cox# EDAC Kconfig 34577ca55SDoug Thompson# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4da9bb1d2SAlan Cox# Licensed and distributed under the GPL 5b01aec9bSBorislav Petkov 6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB 7b01aec9bSBorislav Petkov bool 8da9bb1d2SAlan Cox 954451663SBorislav Petkovconfig EDAC_SUPPORT 1054451663SBorislav Petkov bool 1154451663SBorislav Petkov 12751cb5e5SJan Engelhardtmenuconfig EDAC 13e3c4ff6dSBorislav Petkov tristate "EDAC (Error Detection And Correction) reporting" 14e3c4ff6dSBorislav Petkov depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15da9bb1d2SAlan Cox help 16a06b85ffSBorislav Petkov EDAC is a subsystem along with hardware-specific drivers designed to 17a06b85ffSBorislav Petkov report hardware errors. These are low-level errors that are reported 18a06b85ffSBorislav Petkov in the CPU or supporting chipset or other subsystems: 198cb2a398SDouglas Thompson memory errors, cache errors, PCI errors, thermal throttling, etc.. 208cb2a398SDouglas Thompson If unsure, select 'Y'. 21da9bb1d2SAlan Cox 22a06b85ffSBorislav Petkov The mailing list for the EDAC project is linux-edac@vger.kernel.org. 2357c432b5STim Small 24751cb5e5SJan Engelhardtif EDAC 25da9bb1d2SAlan Cox 2619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS 2719974710SMauro Carvalho Chehab bool "EDAC legacy sysfs" 2819974710SMauro Carvalho Chehab default y 2919974710SMauro Carvalho Chehab help 3019974710SMauro Carvalho Chehab Enable the compatibility sysfs nodes. 3119974710SMauro Carvalho Chehab Use 'Y' if your edac utilities aren't ported to work with the newer 3219974710SMauro Carvalho Chehab structures. 3319974710SMauro Carvalho Chehab 34da9bb1d2SAlan Coxconfig EDAC_DEBUG 35da9bb1d2SAlan Cox bool "Debugging" 361c5bf781SBorislav Petkov select DEBUG_FS 37da9bb1d2SAlan Cox help 3837929874SBorislav Petkov This turns on debugging information for the entire EDAC subsystem. 3937929874SBorislav Petkov You do so by inserting edac_module with "edac_debug_level=x." Valid 4037929874SBorislav Petkov levels are 0-4 (from low to high) and by default it is set to 2. 4137929874SBorislav Petkov Usually you should select 'N' here. 42da9bb1d2SAlan Cox 430d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE 440d18b2e3SBorislav Petkov tristate "Decode MCEs in human-readable form (only on AMD for now)" 45168eb34dSBorislav Petkov depends on CPU_SUP_AMD && X86_MCE_AMD 460d18b2e3SBorislav Petkov default y 47a7f7f624SMasahiro Yamada help 480d18b2e3SBorislav Petkov Enable this option if you want to decode Machine Check Exceptions 4925985edcSLucas De Marchi occurring on your machine in human-readable form. 500d18b2e3SBorislav Petkov 510d18b2e3SBorislav Petkov You should definitely say Y here in case you want to decode MCEs 520d18b2e3SBorislav Petkov which occur really early upon boot, before the module infrastructure 530d18b2e3SBorislav Petkov has been initialized. 540d18b2e3SBorislav Petkov 5577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES 56802e7f1dSJia He tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57802e7f1dSJia He depends on ACPI_APEI_GHES 58ed27b5dfSShuai Xue select UEFI_CPER 5977c5f5d2SMauro Carvalho Chehab help 6077c5f5d2SMauro Carvalho Chehab Not all machines support hardware-driven error report. Some of those 6177c5f5d2SMauro Carvalho Chehab provide a BIOS-driven error report mechanism via ACPI, using the 6277c5f5d2SMauro Carvalho Chehab APEI/GHES driver. By enabling this option, the error reports provided 6377c5f5d2SMauro Carvalho Chehab by GHES are sent to userspace via the EDAC API. 6477c5f5d2SMauro Carvalho Chehab 6577c5f5d2SMauro Carvalho Chehab When this option is enabled, it will disable the hardware-driven 6677c5f5d2SMauro Carvalho Chehab mechanisms, if a GHES BIOS is detected, entering into the 6777c5f5d2SMauro Carvalho Chehab "Firmware First" mode. 6877c5f5d2SMauro Carvalho Chehab 6977c5f5d2SMauro Carvalho Chehab It should be noticed that keeping both GHES and a hardware-driven 7077c5f5d2SMauro Carvalho Chehab error mechanism won't work well, as BIOS will race with OS, while 7177c5f5d2SMauro Carvalho Chehab reading the error registers. So, if you want to not use "Firmware 7277c5f5d2SMauro Carvalho Chehab first" GHES error mechanism, you should disable GHES either at 7377c5f5d2SMauro Carvalho Chehab compilation time or by passing "ghes.disable=1" Kernel parameter 7477c5f5d2SMauro Carvalho Chehab at boot time. 7577c5f5d2SMauro Carvalho Chehab 7677c5f5d2SMauro Carvalho Chehab In doubt, say 'Y'. 7777c5f5d2SMauro Carvalho Chehab 78*f90b7381SShiju Joseconfig EDAC_SCRUB 79*f90b7381SShiju Jose bool "EDAC scrub feature" 80*f90b7381SShiju Jose help 81*f90b7381SShiju Jose The EDAC scrub feature is optional and is designed to control the 82*f90b7381SShiju Jose memory scrubbers in the system. The common sysfs scrub interface 83*f90b7381SShiju Jose abstracts the control of various arbitrary scrubbing functionalities 84*f90b7381SShiju Jose into a unified set of functions. 85*f90b7381SShiju Jose Say 'y/n' to enable/disable EDAC scrub feature. 86*f90b7381SShiju Jose 877d6034d3SDoug Thompsonconfig EDAC_AMD64 88f5b10c45STomasz Pala tristate "AMD64 (Opteron, Athlon64)" 89e3c4ff6dSBorislav Petkov depends on AMD_NB && EDAC_DECODE_MCE 90d6caeafaSMario Limonciello depends on AMD_NODE 916c9058f4SYazen Ghannam imply AMD_ATL 927d6034d3SDoug Thompson help 93027dbd6fSBorislav Petkov Support for error detection and correction of DRAM ECC errors on 94f5b10c45STomasz Pala the AMD64 families (>= K8) of memory controllers. 957d6034d3SDoug Thompson 9661810096SBorislav Petkov When EDAC_DEBUG is enabled, hardware error injection facilities 9761810096SBorislav Petkov through sysfs are available: 9861810096SBorislav Petkov 991865bc71SBorislav Petkov AMD CPUs up to and excluding family 0x17 provide for Memory 1001865bc71SBorislav Petkov Error Injection into the ECC detection circuits. The amd64_edac 1011865bc71SBorislav Petkov module allows the operator/user to inject Uncorrectable and 1021865bc71SBorislav Petkov Correctable errors into DRAM. 1037d6034d3SDoug Thompson 1047d6034d3SDoug Thompson When enabled, in each of the respective memory controller directories 1057d6034d3SDoug Thompson (/sys/devices/system/edac/mc/mcX), there are 3 input files: 1067d6034d3SDoug Thompson 1077d6034d3SDoug Thompson - inject_section (0..3, 16-byte section of 64-byte cacheline), 1087d6034d3SDoug Thompson - inject_word (0..8, 16-bit word of 16-byte section), 1097d6034d3SDoug Thompson - inject_ecc_vector (hex ecc vector: select bits of inject word) 1107d6034d3SDoug Thompson 1117d6034d3SDoug Thompson In addition, there are two control files, inject_read and inject_write, 1127d6034d3SDoug Thompson which trigger the DRAM ECC Read and Write respectively. 113da9bb1d2SAlan Cox 114e23a7cdeSTalel Shenharconfig EDAC_AL_MC 115e23a7cdeSTalel Shenhar tristate "Amazon's Annapurna Lab Memory Controller" 116e23a7cdeSTalel Shenhar depends on (ARCH_ALPINE || COMPILE_TEST) 117e23a7cdeSTalel Shenhar help 118e23a7cdeSTalel Shenhar Support for error detection and correction for Amazon's Annapurna 119e23a7cdeSTalel Shenhar Labs Alpine chips which allow 1 bit correction and 2 bits detection. 120e23a7cdeSTalel Shenhar 121da9bb1d2SAlan Coxconfig EDAC_AMD76X 122da9bb1d2SAlan Cox tristate "AMD 76x (760, 762, 768)" 123e3c4ff6dSBorislav Petkov depends on PCI && X86_32 124da9bb1d2SAlan Cox help 125da9bb1d2SAlan Cox Support for error detection and correction on the AMD 76x 126da9bb1d2SAlan Cox series of chipsets used with the Athlon processor. 127da9bb1d2SAlan Cox 128da9bb1d2SAlan Coxconfig EDAC_E7XXX 129da9bb1d2SAlan Cox tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 130e3c4ff6dSBorislav Petkov depends on PCI && X86_32 131da9bb1d2SAlan Cox help 132da9bb1d2SAlan Cox Support for error detection and correction on the Intel 133da9bb1d2SAlan Cox E7205, E7500, E7501 and E7505 server chipsets. 134da9bb1d2SAlan Cox 135da9bb1d2SAlan Coxconfig EDAC_E752X 1365135b797SAndrei Konovalov tristate "Intel e752x (e7520, e7525, e7320) and 3100" 137e3c4ff6dSBorislav Petkov depends on PCI && X86 138da9bb1d2SAlan Cox help 139da9bb1d2SAlan Cox Support for error detection and correction on the Intel 140da9bb1d2SAlan Cox E7520, E7525, E7320 server chipsets. 141da9bb1d2SAlan Cox 1425a2c675cSTim Smallconfig EDAC_I82443BXGX 1435a2c675cSTim Small tristate "Intel 82443BX/GX (440BX/GX)" 144e3c4ff6dSBorislav Petkov depends on PCI && X86_32 14528f96eeaSAndrew Morton depends on BROKEN 1465a2c675cSTim Small help 1475a2c675cSTim Small Support for error detection and correction on the Intel 1485a2c675cSTim Small 82443BX/GX memory controllers (440BX/GX chipsets). 1495a2c675cSTim Small 150da9bb1d2SAlan Coxconfig EDAC_I82875P 151da9bb1d2SAlan Cox tristate "Intel 82875p (D82875P, E7210)" 152e3c4ff6dSBorislav Petkov depends on PCI && X86_32 153da9bb1d2SAlan Cox help 154da9bb1d2SAlan Cox Support for error detection and correction on the Intel 155da9bb1d2SAlan Cox DP82785P and E7210 server chipsets. 156da9bb1d2SAlan Cox 157420390f0SRanganathan Desikanconfig EDAC_I82975X 158420390f0SRanganathan Desikan tristate "Intel 82975x (D82975x)" 159e3c4ff6dSBorislav Petkov depends on PCI && X86 160420390f0SRanganathan Desikan help 161420390f0SRanganathan Desikan Support for error detection and correction on the Intel 162420390f0SRanganathan Desikan DP82975x server chipsets. 163420390f0SRanganathan Desikan 164535c6a53SJason Uhlenkottconfig EDAC_I3000 165535c6a53SJason Uhlenkott tristate "Intel 3000/3010" 166e3c4ff6dSBorislav Petkov depends on PCI && X86 167535c6a53SJason Uhlenkott help 168535c6a53SJason Uhlenkott Support for error detection and correction on the Intel 169535c6a53SJason Uhlenkott 3000 and 3010 server chipsets. 170535c6a53SJason Uhlenkott 171dd8ef1dbSJason Uhlenkottconfig EDAC_I3200 172dd8ef1dbSJason Uhlenkott tristate "Intel 3200" 173e3c4ff6dSBorislav Petkov depends on PCI && X86 174dd8ef1dbSJason Uhlenkott help 175dd8ef1dbSJason Uhlenkott Support for error detection and correction on the Intel 176dd8ef1dbSJason Uhlenkott 3200 and 3210 server chipsets. 177dd8ef1dbSJason Uhlenkott 1787ee40b89SJason Baronconfig EDAC_IE31200 1797ee40b89SJason Baron tristate "Intel e312xx" 180e3c4ff6dSBorislav Petkov depends on PCI && X86 1817ee40b89SJason Baron help 1827ee40b89SJason Baron Support for error detection and correction on the Intel 1837ee40b89SJason Baron E3-1200 based DRAM controllers. 1847ee40b89SJason Baron 185df8bc08cSHitoshi Mitakeconfig EDAC_X38 186df8bc08cSHitoshi Mitake tristate "Intel X38" 187e3c4ff6dSBorislav Petkov depends on PCI && X86 188df8bc08cSHitoshi Mitake help 189df8bc08cSHitoshi Mitake Support for error detection and correction on the Intel 190df8bc08cSHitoshi Mitake X38 server chipsets. 191df8bc08cSHitoshi Mitake 192920c8df6SMauro Carvalho Chehabconfig EDAC_I5400 193920c8df6SMauro Carvalho Chehab tristate "Intel 5400 (Seaburg) chipsets" 194e3c4ff6dSBorislav Petkov depends on PCI && X86 195920c8df6SMauro Carvalho Chehab help 196920c8df6SMauro Carvalho Chehab Support for error detection and correction the Intel 197920c8df6SMauro Carvalho Chehab i5400 MCH chipset (Seaburg). 198920c8df6SMauro Carvalho Chehab 199a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE 200a0c36a1fSMauro Carvalho Chehab tristate "Intel i7 Core (Nehalem) processors" 201e3c4ff6dSBorislav Petkov depends on PCI && X86 && X86_MCE_INTEL 202a0c36a1fSMauro Carvalho Chehab help 203a0c36a1fSMauro Carvalho Chehab Support for error detection and correction the Intel 204696e409dSMauro Carvalho Chehab i7 Core (Nehalem) Integrated Memory Controller that exists on 205696e409dSMauro Carvalho Chehab newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 206696e409dSMauro Carvalho Chehab and Xeon 55xx processors. 207a0c36a1fSMauro Carvalho Chehab 208da9bb1d2SAlan Coxconfig EDAC_I82860 209da9bb1d2SAlan Cox tristate "Intel 82860" 210e3c4ff6dSBorislav Petkov depends on PCI && X86_32 211da9bb1d2SAlan Cox help 212da9bb1d2SAlan Cox Support for error detection and correction on the Intel 213da9bb1d2SAlan Cox 82860 chipset. 214da9bb1d2SAlan Cox 215da9bb1d2SAlan Coxconfig EDAC_R82600 216da9bb1d2SAlan Cox tristate "Radisys 82600 embedded chipset" 217e3c4ff6dSBorislav Petkov depends on PCI && X86_32 218da9bb1d2SAlan Cox help 219da9bb1d2SAlan Cox Support for error detection and correction on the Radisys 220da9bb1d2SAlan Cox 82600 embedded chipset. 221da9bb1d2SAlan Cox 222eb60705aSEric Wollesenconfig EDAC_I5000 223eb60705aSEric Wollesen tristate "Intel Greencreek/Blackford chipset" 224e3c4ff6dSBorislav Petkov depends on X86 && PCI 22575564191SAristeu Rozanski depends on BROKEN 226eb60705aSEric Wollesen help 227eb60705aSEric Wollesen Support for error detection and correction the Intel 228eb60705aSEric Wollesen Greekcreek/Blackford chipsets. 229eb60705aSEric Wollesen 2308f421c59SArthur Jonesconfig EDAC_I5100 2318f421c59SArthur Jones tristate "Intel San Clemente MCH" 232e3c4ff6dSBorislav Petkov depends on X86 && PCI 2338f421c59SArthur Jones help 2348f421c59SArthur Jones Support for error detection and correction the Intel 2358f421c59SArthur Jones San Clemente MCH. 2368f421c59SArthur Jones 237fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300 238fcaf780bSMauro Carvalho Chehab tristate "Intel Clarksboro MCH" 239e3c4ff6dSBorislav Petkov depends on X86 && PCI 240fcaf780bSMauro Carvalho Chehab help 241fcaf780bSMauro Carvalho Chehab Support for error detection and correction the Intel 242fcaf780bSMauro Carvalho Chehab Clarksboro MCH (Intel 7300 chipset). 243fcaf780bSMauro Carvalho Chehab 2443d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE 24550d1bb93SAristeu Rozanski tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 246e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2473d78c9afSMauro Carvalho Chehab help 2483d78c9afSMauro Carvalho Chehab Support for error detection and correction the Intel 24950d1bb93SAristeu Rozanski Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2503d78c9afSMauro Carvalho Chehab 2514ec656bdSTony Luckconfig EDAC_SKX 2524ec656bdSTony Luck tristate "Intel Skylake server Integrated MC" 25324c9d423SLuck, Tony depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 254de245ae0SRandy Dunlap depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 25558ca9ac1STony Luck select DMI 25624c9d423SLuck, Tony select ACPI_ADXL 2574ec656bdSTony Luck help 2584ec656bdSTony Luck Support for error detection and correction the Intel 25958ca9ac1STony Luck Skylake server Integrated Memory Controllers. If your 26058ca9ac1STony Luck system has non-volatile DIMMs you should also manually 26158ca9ac1STony Luck select CONFIG_ACPI_NFIT. 2624ec656bdSTony Luck 263d4dc89d0SQiuxu Zhuoconfig EDAC_I10NM 264d4dc89d0SQiuxu Zhuo tristate "Intel 10nm server Integrated MC" 265d6a9f733STony Luck depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 266d4dc89d0SQiuxu Zhuo depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 267d4dc89d0SQiuxu Zhuo select DMI 268d6a9f733STony Luck select ACPI_ADXL 269d4dc89d0SQiuxu Zhuo help 270d4dc89d0SQiuxu Zhuo Support for error detection and correction the Intel 271d4dc89d0SQiuxu Zhuo 10nm server Integrated Memory Controllers. If your 272d4dc89d0SQiuxu Zhuo system has non-volatile DIMMs you should also manually 273d4dc89d0SQiuxu Zhuo select CONFIG_ACPI_NFIT. 274d4dc89d0SQiuxu Zhuo 2755c71ad17STony Luckconfig EDAC_PND2 2765c71ad17STony Luck tristate "Intel Pondicherry2" 277e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL 2787b2db704SAndy Shevchenko select P2SB if X86 2795c71ad17STony Luck help 2805c71ad17STony Luck Support for error detection and correction on the Intel 2815c71ad17STony Luck Pondicherry2 Integrated Memory Controller. This SoC IP is 2825c71ad17STony Luck first used on the Apollo Lake platform and Denverton 2835c71ad17STony Luck micro-server but may appear on others in the future. 2845c71ad17STony Luck 28510590a9dSQiuxu Zhuoconfig EDAC_IGEN6 28610590a9dSQiuxu Zhuo tristate "Intel client SoC Integrated MC" 2870a9ece9bSRandy Dunlap depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 288a1c9ca5fSRandy Dunlap depends on X86_64 && X86_MCE_INTEL 28910590a9dSQiuxu Zhuo help 29010590a9dSQiuxu Zhuo Support for error detection and correction on the Intel 29110590a9dSQiuxu Zhuo client SoC Integrated Memory Controller using In-Band ECC IP. 29210590a9dSQiuxu Zhuo This In-Band ECC is first used on the Elkhart Lake SoC but 29310590a9dSQiuxu Zhuo may appear on others in the future. 29410590a9dSQiuxu Zhuo 295a9a753d5SDave Jiangconfig EDAC_MPC85XX 2962b8358a9SMichael Ellerman bool "Freescale MPC83xx / MPC85xx" 2972b8358a9SMichael Ellerman depends on FSL_SOC && EDAC=y 298a9a753d5SDave Jiang help 299a9a753d5SDave Jiang Support for error detection and correction on the Freescale 30074210267SYork Sun MPC8349, MPC8560, MPC8540, MPC8548, T4240 301a9a753d5SDave Jiang 302eeb3d68bSYork Sunconfig EDAC_LAYERSCAPE 303eeb3d68bSYork Sun tristate "Freescale Layerscape DDR" 30428dd6726SRasmus Villemoes depends on ARCH_LAYERSCAPE || SOC_LS1021A 305eeb3d68bSYork Sun help 306eeb3d68bSYork Sun Support for error detection and correction on Freescale memory 307eeb3d68bSYork Sun controllers on Layerscape SoCs. 308eeb3d68bSYork Sun 3097d8536fbSEgor Martovetskyconfig EDAC_PASEMI 3107d8536fbSEgor Martovetsky tristate "PA Semi PWRficient" 311e3c4ff6dSBorislav Petkov depends on PPC_PASEMI && PCI 3127d8536fbSEgor Martovetsky help 3137d8536fbSEgor Martovetsky Support for error detection and correction on PA Semi 3147d8536fbSEgor Martovetsky PWRficient. 3157d8536fbSEgor Martovetsky 3162a9036afSHarry Ciaoconfig EDAC_CPC925 3172a9036afSHarry Ciao tristate "IBM CPC925 Memory Controller (PPC970FX)" 318e3c4ff6dSBorislav Petkov depends on PPC64 3192a9036afSHarry Ciao help 3202a9036afSHarry Ciao Support for error detection and correction on the 3212a9036afSHarry Ciao IBM CPC925 Bridge and Memory Controller, which is 3222a9036afSHarry Ciao a companion chip to the PowerPC 970 family of 3232a9036afSHarry Ciao processors. 3242a9036afSHarry Ciao 325a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC 326a1b01edbSRob Herring tristate "Highbank Memory Controller" 327e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 328a1b01edbSRob Herring help 329a1b01edbSRob Herring Support for error detection and correction on the 330a1b01edbSRob Herring Calxeda Highbank memory controller. 331a1b01edbSRob Herring 33269154d06SRob Herringconfig EDAC_HIGHBANK_L2 33369154d06SRob Herring tristate "Highbank L2 Cache" 334e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 33569154d06SRob Herring help 33669154d06SRob Herring Support for error detection and correction on the 33769154d06SRob Herring Calxeda Highbank memory controller. 33869154d06SRob Herring 339f65aad41SRalf Baechleconfig EDAC_OCTEON_PC 340f65aad41SRalf Baechle tristate "Cavium Octeon Primary Caches" 341e3c4ff6dSBorislav Petkov depends on CPU_CAVIUM_OCTEON 342f65aad41SRalf Baechle help 343f65aad41SRalf Baechle Support for error detection and correction on the primary caches of 344f65aad41SRalf Baechle the cnMIPS cores of Cavium Octeon family SOCs. 345f65aad41SRalf Baechle 346f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C 347f65aad41SRalf Baechle tristate "Cavium Octeon Secondary Caches (L2C)" 348e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 349f65aad41SRalf Baechle help 350f65aad41SRalf Baechle Support for error detection and correction on the 351f65aad41SRalf Baechle Cavium Octeon family of SOCs. 352f65aad41SRalf Baechle 353f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC 354f65aad41SRalf Baechle tristate "Cavium Octeon DRAM Memory Controller (LMC)" 355e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 356f65aad41SRalf Baechle help 357f65aad41SRalf Baechle Support for error detection and correction on the 358f65aad41SRalf Baechle Cavium Octeon family of SOCs. 359f65aad41SRalf Baechle 360f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI 361f65aad41SRalf Baechle tristate "Cavium Octeon PCI Controller" 362e3c4ff6dSBorislav Petkov depends on PCI && CAVIUM_OCTEON_SOC 363f65aad41SRalf Baechle help 364f65aad41SRalf Baechle Support for error detection and correction on the 365f65aad41SRalf Baechle Cavium Octeon family of SOCs. 366f65aad41SRalf Baechle 36741003396SSergey Temerkhanovconfig EDAC_THUNDERX 36841003396SSergey Temerkhanov tristate "Cavium ThunderX EDAC" 36941003396SSergey Temerkhanov depends on ARM64 37041003396SSergey Temerkhanov depends on PCI 37141003396SSergey Temerkhanov help 37241003396SSergey Temerkhanov Support for error detection and correction on the 37341003396SSergey Temerkhanov Cavium ThunderX memory controllers (LMC), Cache 37441003396SSergey Temerkhanov Coherent Processor Interconnect (CCPI) and L2 cache 37541003396SSergey Temerkhanov blocks (TAD, CBC, MCI). 37641003396SSergey Temerkhanov 377c3eea194SThor Thayerconfig EDAC_ALTERA 378c3eea194SThor Thayer bool "Altera SOCFPGA ECC" 379098da961SKrzysztof Kozlowski depends on EDAC=y && ARCH_INTEL_SOCFPGA 38071bcada8SThor Thayer help 38171bcada8SThor Thayer Support for error detection and correction on the 382580b5cf5SThor Thayer Altera SOCs. This is the global enable for the 383580b5cf5SThor Thayer various Altera peripherals. 384580b5cf5SThor Thayer 385580b5cf5SThor Thayerconfig EDAC_ALTERA_SDRAM 386580b5cf5SThor Thayer bool "Altera SDRAM ECC" 387580b5cf5SThor Thayer depends on EDAC_ALTERA=y 388580b5cf5SThor Thayer help 389580b5cf5SThor Thayer Support for error detection and correction on the 390580b5cf5SThor Thayer Altera SDRAM Memory for Altera SoCs. Note that the 391580b5cf5SThor Thayer preloader must initialize the SDRAM before loading 392580b5cf5SThor Thayer the kernel. 393c3eea194SThor Thayer 394c3eea194SThor Thayerconfig EDAC_ALTERA_L2C 395c3eea194SThor Thayer bool "Altera L2 Cache ECC" 3963a8f21f1SThor Thayer depends on EDAC_ALTERA=y && CACHE_L2X0 397c3eea194SThor Thayer help 398c3eea194SThor Thayer Support for error detection and correction on the 399c3eea194SThor Thayer Altera L2 cache Memory for Altera SoCs. This option 4003a8f21f1SThor Thayer requires L2 cache. 401c3eea194SThor Thayer 402c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM 403c3eea194SThor Thayer bool "Altera On-Chip RAM ECC" 404c3eea194SThor Thayer depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 405c3eea194SThor Thayer help 406c3eea194SThor Thayer Support for error detection and correction on the 407c3eea194SThor Thayer Altera On-Chip RAM Memory for Altera SoCs. 40871bcada8SThor Thayer 409ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET 410ab8c1e0fSThor Thayer bool "Altera Ethernet FIFO ECC" 411ab8c1e0fSThor Thayer depends on EDAC_ALTERA=y 412ab8c1e0fSThor Thayer help 413ab8c1e0fSThor Thayer Support for error detection and correction on the 414ab8c1e0fSThor Thayer Altera Ethernet FIFO Memory for Altera SoCs. 415ab8c1e0fSThor Thayer 416c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND 417c6882fb2SThor Thayer bool "Altera NAND FIFO ECC" 418c6882fb2SThor Thayer depends on EDAC_ALTERA=y && MTD_NAND_DENALI 419c6882fb2SThor Thayer help 420c6882fb2SThor Thayer Support for error detection and correction on the 421c6882fb2SThor Thayer Altera NAND FIFO Memory for Altera SoCs. 422c6882fb2SThor Thayer 423e8263793SThor Thayerconfig EDAC_ALTERA_DMA 424e8263793SThor Thayer bool "Altera DMA FIFO ECC" 425e8263793SThor Thayer depends on EDAC_ALTERA=y && PL330_DMA=y 426e8263793SThor Thayer help 427e8263793SThor Thayer Support for error detection and correction on the 428e8263793SThor Thayer Altera DMA FIFO Memory for Altera SoCs. 429e8263793SThor Thayer 430c609581dSThor Thayerconfig EDAC_ALTERA_USB 431c609581dSThor Thayer bool "Altera USB FIFO ECC" 432c609581dSThor Thayer depends on EDAC_ALTERA=y && USB_DWC2 433c609581dSThor Thayer help 434c609581dSThor Thayer Support for error detection and correction on the 435c609581dSThor Thayer Altera USB FIFO Memory for Altera SoCs. 436c609581dSThor Thayer 437485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI 438485fe9e2SThor Thayer bool "Altera QSPI FIFO ECC" 439485fe9e2SThor Thayer depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 440485fe9e2SThor Thayer help 441485fe9e2SThor Thayer Support for error detection and correction on the 442485fe9e2SThor Thayer Altera QSPI FIFO Memory for Altera SoCs. 443485fe9e2SThor Thayer 44491104984SThor Thayerconfig EDAC_ALTERA_SDMMC 44591104984SThor Thayer bool "Altera SDMMC FIFO ECC" 44691104984SThor Thayer depends on EDAC_ALTERA=y && MMC_DW 44791104984SThor Thayer help 44891104984SThor Thayer Support for error detection and correction on the 44991104984SThor Thayer Altera SDMMC FIFO Memory for Altera SoCs. 45091104984SThor Thayer 45191abaeaaSYash Shahconfig EDAC_SIFIVE 45291abaeaaSYash Shah bool "Sifive platform EDAC driver" 453ca120a79SGreentime Hu depends on EDAC=y && SIFIVE_CCACHE 45491abaeaaSYash Shah help 45591abaeaaSYash Shah Support for error detection and correction on the SiFive SoCs. 45691abaeaaSYash Shah 4577f6998a4SJan Luebbeconfig EDAC_ARMADA_XP 4587f6998a4SJan Luebbe bool "Marvell Armada XP DDR and L2 Cache ECC" 4597f6998a4SJan Luebbe depends on MACH_MVEBU_V7 4607f6998a4SJan Luebbe help 4617f6998a4SJan Luebbe Support for error correction and detection on the Marvell Aramada XP 4627f6998a4SJan Luebbe DDR RAM and L2 cache controllers. 4637f6998a4SJan Luebbe 464ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS 465ae9b56e3SPunnaiah Choudary Kalluri tristate "Synopsys DDR Memory Controller" 4665297ecfeSSherry Sun depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 467ae9b56e3SPunnaiah Choudary Kalluri help 468ae9b56e3SPunnaiah Choudary Kalluri Support for error detection and correction on the Synopsys DDR 469ae9b56e3SPunnaiah Choudary Kalluri memory controller. 470ae9b56e3SPunnaiah Choudary Kalluri 4710d442930SLoc Hoconfig EDAC_XGENE 4720d442930SLoc Ho tristate "APM X-Gene SoC" 473e3c4ff6dSBorislav Petkov depends on (ARM64 || COMPILE_TEST) 4740d442930SLoc Ho help 4750d442930SLoc Ho Support for error detection and correction on the 4760d442930SLoc Ho APM X-Gene family of SOCs. 4770d442930SLoc Ho 47886a18ee2STero Kristoconfig EDAC_TI 47986a18ee2STero Kristo tristate "Texas Instruments DDR3 ECC Controller" 48086a18ee2STero Kristo depends on ARCH_KEYSTONE || SOC_DRA7XX 48186a18ee2STero Kristo help 482a483e227SKrzysztof Kozlowski Support for error detection and correction on the TI SoCs. 48386a18ee2STero Kristo 48427450653SChannagoud Kadabiconfig EDAC_QCOM 48527450653SChannagoud Kadabi tristate "QCOM EDAC Controller" 48627450653SChannagoud Kadabi depends on ARCH_QCOM && QCOM_LLCC 48727450653SChannagoud Kadabi help 48827450653SChannagoud Kadabi Support for error detection and correction on the 48927450653SChannagoud Kadabi Qualcomm Technologies, Inc. SoCs. 49027450653SChannagoud Kadabi 49127450653SChannagoud Kadabi This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 49227450653SChannagoud Kadabi As of now, it supports error reporting for Last Level Cache Controller (LLCC) 49327450653SChannagoud Kadabi of Tag RAM and Data RAM. 49427450653SChannagoud Kadabi 49527450653SChannagoud Kadabi For debugging issues having to do with stability and overall system 49627450653SChannagoud Kadabi health, you should probably say 'Y' here. 49727450653SChannagoud Kadabi 4989b7e6242SStefan M Schaeckelerconfig EDAC_ASPEED 499edfc2d73STroy Lee tristate "Aspeed AST BMC SoC" 500edfc2d73STroy Lee depends on ARCH_ASPEED 5019b7e6242SStefan M Schaeckeler help 502edfc2d73STroy Lee Support for error detection and correction on the Aspeed AST BMC SoC. 5039b7e6242SStefan M Schaeckeler 5049b7e6242SStefan M Schaeckeler First, ECC must be configured in the bootloader. Then, this driver 5059b7e6242SStefan M Schaeckeler will expose error counters via the EDAC kernel framework. 5069b7e6242SStefan M Schaeckeler 50782413e56SShravan Kumar Ramaniconfig EDAC_BLUEFIELD 50882413e56SShravan Kumar Ramani tristate "Mellanox BlueField Memory ECC" 50982413e56SShravan Kumar Ramani depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 51082413e56SShravan Kumar Ramani help 51182413e56SShravan Kumar Ramani Support for error detection and correction on the 51282413e56SShravan Kumar Ramani Mellanox BlueField SoCs. 51382413e56SShravan Kumar Ramani 5141088750dSLei Wangconfig EDAC_DMC520 5151088750dSLei Wang tristate "ARM DMC-520 ECC" 5161088750dSLei Wang depends on ARM64 5171088750dSLei Wang help 5181088750dSLei Wang Support for error detection and correction on the 5191088750dSLei Wang SoCs with ARM DMC-520 DRAM controller. 5201088750dSLei Wang 5213bd2706cSSai Krishna Potthuriconfig EDAC_ZYNQMP 5223bd2706cSSai Krishna Potthuri tristate "Xilinx ZynqMP OCM Controller" 5233bd2706cSSai Krishna Potthuri depends on ARCH_ZYNQMP || COMPILE_TEST 5243bd2706cSSai Krishna Potthuri help 5253bd2706cSSai Krishna Potthuri This driver supports error detection and correction for the 5263bd2706cSSai Krishna Potthuri Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 5273bd2706cSSai Krishna Potthuri built as a module. In that case it will be called zynqmp_edac. 5283bd2706cSSai Krishna Potthuri 529d244c610SMarvin Linconfig EDAC_NPCM 530d244c610SMarvin Lin tristate "Nuvoton NPCM DDR Memory Controller" 531d244c610SMarvin Lin depends on (ARCH_NPCM || COMPILE_TEST) 532d244c610SMarvin Lin help 533d244c610SMarvin Lin Support for error detection and correction on the Nuvoton NPCM DDR 534d244c610SMarvin Lin memory controller. 535d244c610SMarvin Lin 536d244c610SMarvin Lin The memory controller supports single bit error correction, double bit 537d244c610SMarvin Lin error detection (in-line ECC in which a section 1/8th of the memory 538d244c610SMarvin Lin device used to store data is used for ECC storage). 539d244c610SMarvin Lin 5406f15b178SShubhrajyoti Dattaconfig EDAC_VERSAL 5416f15b178SShubhrajyoti Datta tristate "Xilinx Versal DDR Memory Controller" 5426f15b178SShubhrajyoti Datta depends on ARCH_ZYNQMP || COMPILE_TEST 5436f15b178SShubhrajyoti Datta help 5446f15b178SShubhrajyoti Datta Support for error detection and correction on the Xilinx Versal DDR 5456f15b178SShubhrajyoti Datta memory controller. 5466f15b178SShubhrajyoti Datta 5476f15b178SShubhrajyoti Datta Report both single bit errors (CE) and double bit errors (UE). 5486f15b178SShubhrajyoti Datta Support injecting both correctable and uncorrectable errors 5496f15b178SShubhrajyoti Datta for debugging purposes. 5506f15b178SShubhrajyoti Datta 551558aff7aSZhao Qunqinconfig EDAC_LOONGSON 552558aff7aSZhao Qunqin tristate "Loongson Memory Controller" 553558aff7aSZhao Qunqin depends on LOONGARCH && ACPI 554558aff7aSZhao Qunqin help 555558aff7aSZhao Qunqin Support for error detection and correction on the Loongson 556558aff7aSZhao Qunqin family memory controller. This driver reports single bit 557558aff7aSZhao Qunqin errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 558558aff7aSZhao Qunqin are compatible. 5596f15b178SShubhrajyoti Datta 560751cb5e5SJan Engelhardtendif # EDAC 561