1da9bb1d2SAlan Cox# 2da9bb1d2SAlan Cox# EDAC Kconfig 34577ca55SDoug Thompson# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4da9bb1d2SAlan Cox# Licensed and distributed under the GPL 5b01aec9bSBorislav Petkov 6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB 7b01aec9bSBorislav Petkov bool 8da9bb1d2SAlan Cox 954451663SBorislav Petkovconfig EDAC_SUPPORT 1054451663SBorislav Petkov bool 1154451663SBorislav Petkov 12751cb5e5SJan Engelhardtmenuconfig EDAC 13*e3c4ff6dSBorislav Petkov tristate "EDAC (Error Detection And Correction) reporting" 14*e3c4ff6dSBorislav Petkov depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15da9bb1d2SAlan Cox help 16da9bb1d2SAlan Cox EDAC is designed to report errors in the core system. 17da9bb1d2SAlan Cox These are low-level errors that are reported in the CPU or 188cb2a398SDouglas Thompson supporting chipset or other subsystems: 198cb2a398SDouglas Thompson memory errors, cache errors, PCI errors, thermal throttling, etc.. 208cb2a398SDouglas Thompson If unsure, select 'Y'. 21da9bb1d2SAlan Cox 2257c432b5STim Small If this code is reporting problems on your system, please 2357c432b5STim Small see the EDAC project web pages for more information at: 2457c432b5STim Small 2557c432b5STim Small <http://bluesmoke.sourceforge.net/> 2657c432b5STim Small 2757c432b5STim Small and: 2857c432b5STim Small 2957c432b5STim Small <http://buttersideup.com/edacwiki> 3057c432b5STim Small 3157c432b5STim Small There is also a mailing list for the EDAC project, which can 3257c432b5STim Small be found via the sourceforge page. 3357c432b5STim Small 34751cb5e5SJan Engelhardtif EDAC 35da9bb1d2SAlan Cox 3619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS 3719974710SMauro Carvalho Chehab bool "EDAC legacy sysfs" 3819974710SMauro Carvalho Chehab default y 3919974710SMauro Carvalho Chehab help 4019974710SMauro Carvalho Chehab Enable the compatibility sysfs nodes. 4119974710SMauro Carvalho Chehab Use 'Y' if your edac utilities aren't ported to work with the newer 4219974710SMauro Carvalho Chehab structures. 4319974710SMauro Carvalho Chehab 44da9bb1d2SAlan Coxconfig EDAC_DEBUG 45da9bb1d2SAlan Cox bool "Debugging" 461c5bf781SBorislav Petkov select DEBUG_FS 47da9bb1d2SAlan Cox help 4837929874SBorislav Petkov This turns on debugging information for the entire EDAC subsystem. 4937929874SBorislav Petkov You do so by inserting edac_module with "edac_debug_level=x." Valid 5037929874SBorislav Petkov levels are 0-4 (from low to high) and by default it is set to 2. 5137929874SBorislav Petkov Usually you should select 'N' here. 52da9bb1d2SAlan Cox 530d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE 540d18b2e3SBorislav Petkov tristate "Decode MCEs in human-readable form (only on AMD for now)" 55168eb34dSBorislav Petkov depends on CPU_SUP_AMD && X86_MCE_AMD 560d18b2e3SBorislav Petkov default y 570d18b2e3SBorislav Petkov ---help--- 580d18b2e3SBorislav Petkov Enable this option if you want to decode Machine Check Exceptions 5925985edcSLucas De Marchi occurring on your machine in human-readable form. 600d18b2e3SBorislav Petkov 610d18b2e3SBorislav Petkov You should definitely say Y here in case you want to decode MCEs 620d18b2e3SBorislav Petkov which occur really early upon boot, before the module infrastructure 630d18b2e3SBorislav Petkov has been initialized. 640d18b2e3SBorislav Petkov 6577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES 6677c5f5d2SMauro Carvalho Chehab bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 67*e3c4ff6dSBorislav Petkov depends on ACPI_APEI_GHES && (EDAC=y) 6877c5f5d2SMauro Carvalho Chehab default y 6977c5f5d2SMauro Carvalho Chehab help 7077c5f5d2SMauro Carvalho Chehab Not all machines support hardware-driven error report. Some of those 7177c5f5d2SMauro Carvalho Chehab provide a BIOS-driven error report mechanism via ACPI, using the 7277c5f5d2SMauro Carvalho Chehab APEI/GHES driver. By enabling this option, the error reports provided 7377c5f5d2SMauro Carvalho Chehab by GHES are sent to userspace via the EDAC API. 7477c5f5d2SMauro Carvalho Chehab 7577c5f5d2SMauro Carvalho Chehab When this option is enabled, it will disable the hardware-driven 7677c5f5d2SMauro Carvalho Chehab mechanisms, if a GHES BIOS is detected, entering into the 7777c5f5d2SMauro Carvalho Chehab "Firmware First" mode. 7877c5f5d2SMauro Carvalho Chehab 7977c5f5d2SMauro Carvalho Chehab It should be noticed that keeping both GHES and a hardware-driven 8077c5f5d2SMauro Carvalho Chehab error mechanism won't work well, as BIOS will race with OS, while 8177c5f5d2SMauro Carvalho Chehab reading the error registers. So, if you want to not use "Firmware 8277c5f5d2SMauro Carvalho Chehab first" GHES error mechanism, you should disable GHES either at 8377c5f5d2SMauro Carvalho Chehab compilation time or by passing "ghes.disable=1" Kernel parameter 8477c5f5d2SMauro Carvalho Chehab at boot time. 8577c5f5d2SMauro Carvalho Chehab 8677c5f5d2SMauro Carvalho Chehab In doubt, say 'Y'. 8777c5f5d2SMauro Carvalho Chehab 887d6034d3SDoug Thompsonconfig EDAC_AMD64 89f5b10c45STomasz Pala tristate "AMD64 (Opteron, Athlon64)" 90*e3c4ff6dSBorislav Petkov depends on AMD_NB && EDAC_DECODE_MCE 917d6034d3SDoug Thompson help 92027dbd6fSBorislav Petkov Support for error detection and correction of DRAM ECC errors on 93f5b10c45STomasz Pala the AMD64 families (>= K8) of memory controllers. 947d6034d3SDoug Thompson 957d6034d3SDoug Thompsonconfig EDAC_AMD64_ERROR_INJECTION 969cdeb404SBorislav Petkov bool "Sysfs HW Error injection facilities" 977d6034d3SDoug Thompson depends on EDAC_AMD64 987d6034d3SDoug Thompson help 997d6034d3SDoug Thompson Recent Opterons (Family 10h and later) provide for Memory Error 1007d6034d3SDoug Thompson Injection into the ECC detection circuits. The amd64_edac module 1017d6034d3SDoug Thompson allows the operator/user to inject Uncorrectable and Correctable 1027d6034d3SDoug Thompson errors into DRAM. 1037d6034d3SDoug Thompson 1047d6034d3SDoug Thompson When enabled, in each of the respective memory controller directories 1057d6034d3SDoug Thompson (/sys/devices/system/edac/mc/mcX), there are 3 input files: 1067d6034d3SDoug Thompson 1077d6034d3SDoug Thompson - inject_section (0..3, 16-byte section of 64-byte cacheline), 1087d6034d3SDoug Thompson - inject_word (0..8, 16-bit word of 16-byte section), 1097d6034d3SDoug Thompson - inject_ecc_vector (hex ecc vector: select bits of inject word) 1107d6034d3SDoug Thompson 1117d6034d3SDoug Thompson In addition, there are two control files, inject_read and inject_write, 1127d6034d3SDoug Thompson which trigger the DRAM ECC Read and Write respectively. 113da9bb1d2SAlan Cox 114da9bb1d2SAlan Coxconfig EDAC_AMD76X 115da9bb1d2SAlan Cox tristate "AMD 76x (760, 762, 768)" 116*e3c4ff6dSBorislav Petkov depends on PCI && X86_32 117da9bb1d2SAlan Cox help 118da9bb1d2SAlan Cox Support for error detection and correction on the AMD 76x 119da9bb1d2SAlan Cox series of chipsets used with the Athlon processor. 120da9bb1d2SAlan Cox 121da9bb1d2SAlan Coxconfig EDAC_E7XXX 122da9bb1d2SAlan Cox tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 123*e3c4ff6dSBorislav Petkov depends on PCI && X86_32 124da9bb1d2SAlan Cox help 125da9bb1d2SAlan Cox Support for error detection and correction on the Intel 126da9bb1d2SAlan Cox E7205, E7500, E7501 and E7505 server chipsets. 127da9bb1d2SAlan Cox 128da9bb1d2SAlan Coxconfig EDAC_E752X 1295135b797SAndrei Konovalov tristate "Intel e752x (e7520, e7525, e7320) and 3100" 130*e3c4ff6dSBorislav Petkov depends on PCI && X86 131da9bb1d2SAlan Cox help 132da9bb1d2SAlan Cox Support for error detection and correction on the Intel 133da9bb1d2SAlan Cox E7520, E7525, E7320 server chipsets. 134da9bb1d2SAlan Cox 1355a2c675cSTim Smallconfig EDAC_I82443BXGX 1365a2c675cSTim Small tristate "Intel 82443BX/GX (440BX/GX)" 137*e3c4ff6dSBorislav Petkov depends on PCI && X86_32 13828f96eeaSAndrew Morton depends on BROKEN 1395a2c675cSTim Small help 1405a2c675cSTim Small Support for error detection and correction on the Intel 1415a2c675cSTim Small 82443BX/GX memory controllers (440BX/GX chipsets). 1425a2c675cSTim Small 143da9bb1d2SAlan Coxconfig EDAC_I82875P 144da9bb1d2SAlan Cox tristate "Intel 82875p (D82875P, E7210)" 145*e3c4ff6dSBorislav Petkov depends on PCI && X86_32 146da9bb1d2SAlan Cox help 147da9bb1d2SAlan Cox Support for error detection and correction on the Intel 148da9bb1d2SAlan Cox DP82785P and E7210 server chipsets. 149da9bb1d2SAlan Cox 150420390f0SRanganathan Desikanconfig EDAC_I82975X 151420390f0SRanganathan Desikan tristate "Intel 82975x (D82975x)" 152*e3c4ff6dSBorislav Petkov depends on PCI && X86 153420390f0SRanganathan Desikan help 154420390f0SRanganathan Desikan Support for error detection and correction on the Intel 155420390f0SRanganathan Desikan DP82975x server chipsets. 156420390f0SRanganathan Desikan 157535c6a53SJason Uhlenkottconfig EDAC_I3000 158535c6a53SJason Uhlenkott tristate "Intel 3000/3010" 159*e3c4ff6dSBorislav Petkov depends on PCI && X86 160535c6a53SJason Uhlenkott help 161535c6a53SJason Uhlenkott Support for error detection and correction on the Intel 162535c6a53SJason Uhlenkott 3000 and 3010 server chipsets. 163535c6a53SJason Uhlenkott 164dd8ef1dbSJason Uhlenkottconfig EDAC_I3200 165dd8ef1dbSJason Uhlenkott tristate "Intel 3200" 166*e3c4ff6dSBorislav Petkov depends on PCI && X86 167dd8ef1dbSJason Uhlenkott help 168dd8ef1dbSJason Uhlenkott Support for error detection and correction on the Intel 169dd8ef1dbSJason Uhlenkott 3200 and 3210 server chipsets. 170dd8ef1dbSJason Uhlenkott 1717ee40b89SJason Baronconfig EDAC_IE31200 1727ee40b89SJason Baron tristate "Intel e312xx" 173*e3c4ff6dSBorislav Petkov depends on PCI && X86 1747ee40b89SJason Baron help 1757ee40b89SJason Baron Support for error detection and correction on the Intel 1767ee40b89SJason Baron E3-1200 based DRAM controllers. 1777ee40b89SJason Baron 178df8bc08cSHitoshi Mitakeconfig EDAC_X38 179df8bc08cSHitoshi Mitake tristate "Intel X38" 180*e3c4ff6dSBorislav Petkov depends on PCI && X86 181df8bc08cSHitoshi Mitake help 182df8bc08cSHitoshi Mitake Support for error detection and correction on the Intel 183df8bc08cSHitoshi Mitake X38 server chipsets. 184df8bc08cSHitoshi Mitake 185920c8df6SMauro Carvalho Chehabconfig EDAC_I5400 186920c8df6SMauro Carvalho Chehab tristate "Intel 5400 (Seaburg) chipsets" 187*e3c4ff6dSBorislav Petkov depends on PCI && X86 188920c8df6SMauro Carvalho Chehab help 189920c8df6SMauro Carvalho Chehab Support for error detection and correction the Intel 190920c8df6SMauro Carvalho Chehab i5400 MCH chipset (Seaburg). 191920c8df6SMauro Carvalho Chehab 192a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE 193a0c36a1fSMauro Carvalho Chehab tristate "Intel i7 Core (Nehalem) processors" 194*e3c4ff6dSBorislav Petkov depends on PCI && X86 && X86_MCE_INTEL 195a0c36a1fSMauro Carvalho Chehab help 196a0c36a1fSMauro Carvalho Chehab Support for error detection and correction the Intel 197696e409dSMauro Carvalho Chehab i7 Core (Nehalem) Integrated Memory Controller that exists on 198696e409dSMauro Carvalho Chehab newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 199696e409dSMauro Carvalho Chehab and Xeon 55xx processors. 200a0c36a1fSMauro Carvalho Chehab 201da9bb1d2SAlan Coxconfig EDAC_I82860 202da9bb1d2SAlan Cox tristate "Intel 82860" 203*e3c4ff6dSBorislav Petkov depends on PCI && X86_32 204da9bb1d2SAlan Cox help 205da9bb1d2SAlan Cox Support for error detection and correction on the Intel 206da9bb1d2SAlan Cox 82860 chipset. 207da9bb1d2SAlan Cox 208da9bb1d2SAlan Coxconfig EDAC_R82600 209da9bb1d2SAlan Cox tristate "Radisys 82600 embedded chipset" 210*e3c4ff6dSBorislav Petkov depends on PCI && X86_32 211da9bb1d2SAlan Cox help 212da9bb1d2SAlan Cox Support for error detection and correction on the Radisys 213da9bb1d2SAlan Cox 82600 embedded chipset. 214da9bb1d2SAlan Cox 215eb60705aSEric Wollesenconfig EDAC_I5000 216eb60705aSEric Wollesen tristate "Intel Greencreek/Blackford chipset" 217*e3c4ff6dSBorislav Petkov depends on X86 && PCI 218eb60705aSEric Wollesen help 219eb60705aSEric Wollesen Support for error detection and correction the Intel 220eb60705aSEric Wollesen Greekcreek/Blackford chipsets. 221eb60705aSEric Wollesen 2228f421c59SArthur Jonesconfig EDAC_I5100 2238f421c59SArthur Jones tristate "Intel San Clemente MCH" 224*e3c4ff6dSBorislav Petkov depends on X86 && PCI 2258f421c59SArthur Jones help 2268f421c59SArthur Jones Support for error detection and correction the Intel 2278f421c59SArthur Jones San Clemente MCH. 2288f421c59SArthur Jones 229fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300 230fcaf780bSMauro Carvalho Chehab tristate "Intel Clarksboro MCH" 231*e3c4ff6dSBorislav Petkov depends on X86 && PCI 232fcaf780bSMauro Carvalho Chehab help 233fcaf780bSMauro Carvalho Chehab Support for error detection and correction the Intel 234fcaf780bSMauro Carvalho Chehab Clarksboro MCH (Intel 7300 chipset). 235fcaf780bSMauro Carvalho Chehab 2363d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE 23750d1bb93SAristeu Rozanski tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 238*e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2393d78c9afSMauro Carvalho Chehab help 2403d78c9afSMauro Carvalho Chehab Support for error detection and correction the Intel 24150d1bb93SAristeu Rozanski Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2423d78c9afSMauro Carvalho Chehab 2434ec656bdSTony Luckconfig EDAC_SKX 2444ec656bdSTony Luck tristate "Intel Skylake server Integrated MC" 245*e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2464ec656bdSTony Luck help 2474ec656bdSTony Luck Support for error detection and correction the Intel 2484ec656bdSTony Luck Skylake server Integrated Memory Controllers. 2494ec656bdSTony Luck 2505c71ad17STony Luckconfig EDAC_PND2 2515c71ad17STony Luck tristate "Intel Pondicherry2" 252*e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL 2535c71ad17STony Luck help 2545c71ad17STony Luck Support for error detection and correction on the Intel 2555c71ad17STony Luck Pondicherry2 Integrated Memory Controller. This SoC IP is 2565c71ad17STony Luck first used on the Apollo Lake platform and Denverton 2575c71ad17STony Luck micro-server but may appear on others in the future. 2585c71ad17STony Luck 259a9a753d5SDave Jiangconfig EDAC_MPC85XX 260b4846251SIra W. Snyder tristate "Freescale MPC83xx / MPC85xx" 261*e3c4ff6dSBorislav Petkov depends on FSL_SOC 262a9a753d5SDave Jiang help 263a9a753d5SDave Jiang Support for error detection and correction on the Freescale 26474210267SYork Sun MPC8349, MPC8560, MPC8540, MPC8548, T4240 265a9a753d5SDave Jiang 266eeb3d68bSYork Sunconfig EDAC_LAYERSCAPE 267eeb3d68bSYork Sun tristate "Freescale Layerscape DDR" 268*e3c4ff6dSBorislav Petkov depends on ARCH_LAYERSCAPE 269eeb3d68bSYork Sun help 270eeb3d68bSYork Sun Support for error detection and correction on Freescale memory 271eeb3d68bSYork Sun controllers on Layerscape SoCs. 272eeb3d68bSYork Sun 2734f4aeeabSDave Jiangconfig EDAC_MV64X60 2744f4aeeabSDave Jiang tristate "Marvell MV64x60" 275*e3c4ff6dSBorislav Petkov depends on MV64X60 2764f4aeeabSDave Jiang help 2774f4aeeabSDave Jiang Support for error detection and correction on the Marvell 2784f4aeeabSDave Jiang MV64360 and MV64460 chipsets. 2794f4aeeabSDave Jiang 2807d8536fbSEgor Martovetskyconfig EDAC_PASEMI 2817d8536fbSEgor Martovetsky tristate "PA Semi PWRficient" 282*e3c4ff6dSBorislav Petkov depends on PPC_PASEMI && PCI 2837d8536fbSEgor Martovetsky help 2847d8536fbSEgor Martovetsky Support for error detection and correction on PA Semi 2857d8536fbSEgor Martovetsky PWRficient. 2867d8536fbSEgor Martovetsky 28748764e41SBenjamin Herrenschmidtconfig EDAC_CELL 28848764e41SBenjamin Herrenschmidt tristate "Cell Broadband Engine memory controller" 289*e3c4ff6dSBorislav Petkov depends on PPC_CELL_COMMON 29048764e41SBenjamin Herrenschmidt help 29148764e41SBenjamin Herrenschmidt Support for error detection and correction on the 29248764e41SBenjamin Herrenschmidt Cell Broadband Engine internal memory controller 29348764e41SBenjamin Herrenschmidt on platform without a hypervisor 2947d8536fbSEgor Martovetsky 295dba7a77cSGrant Ericksonconfig EDAC_PPC4XX 296dba7a77cSGrant Erickson tristate "PPC4xx IBM DDR2 Memory Controller" 297*e3c4ff6dSBorislav Petkov depends on 4xx 298dba7a77cSGrant Erickson help 299dba7a77cSGrant Erickson This enables support for EDAC on the ECC memory used 300dba7a77cSGrant Erickson with the IBM DDR2 memory controller found in various 301dba7a77cSGrant Erickson PowerPC 4xx embedded processors such as the 405EX[r], 302dba7a77cSGrant Erickson 440SP, 440SPe, 460EX, 460GT and 460SX. 303dba7a77cSGrant Erickson 304e8765584SHarry Ciaoconfig EDAC_AMD8131 305e8765584SHarry Ciao tristate "AMD8131 HyperTransport PCI-X Tunnel" 306*e3c4ff6dSBorislav Petkov depends on PCI && PPC_MAPLE 307e8765584SHarry Ciao help 308e8765584SHarry Ciao Support for error detection and correction on the 309e8765584SHarry Ciao AMD8131 HyperTransport PCI-X Tunnel chip. 310715fe7afSHarry Ciao Note, add more Kconfig dependency if it's adopted 311715fe7afSHarry Ciao on some machine other than Maple. 312e8765584SHarry Ciao 31358b4ce6fSHarry Ciaoconfig EDAC_AMD8111 31458b4ce6fSHarry Ciao tristate "AMD8111 HyperTransport I/O Hub" 315*e3c4ff6dSBorislav Petkov depends on PCI && PPC_MAPLE 31658b4ce6fSHarry Ciao help 31758b4ce6fSHarry Ciao Support for error detection and correction on the 31858b4ce6fSHarry Ciao AMD8111 HyperTransport I/O Hub chip. 319715fe7afSHarry Ciao Note, add more Kconfig dependency if it's adopted 320715fe7afSHarry Ciao on some machine other than Maple. 32158b4ce6fSHarry Ciao 3222a9036afSHarry Ciaoconfig EDAC_CPC925 3232a9036afSHarry Ciao tristate "IBM CPC925 Memory Controller (PPC970FX)" 324*e3c4ff6dSBorislav Petkov depends on PPC64 3252a9036afSHarry Ciao help 3262a9036afSHarry Ciao Support for error detection and correction on the 3272a9036afSHarry Ciao IBM CPC925 Bridge and Memory Controller, which is 3282a9036afSHarry Ciao a companion chip to the PowerPC 970 family of 3292a9036afSHarry Ciao processors. 3302a9036afSHarry Ciao 3315c770755SChris Metcalfconfig EDAC_TILE 3325c770755SChris Metcalf tristate "Tilera Memory Controller" 333*e3c4ff6dSBorislav Petkov depends on TILE 3345c770755SChris Metcalf default y 3355c770755SChris Metcalf help 3365c770755SChris Metcalf Support for error detection and correction on the 3375c770755SChris Metcalf Tilera memory controller. 3385c770755SChris Metcalf 339a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC 340a1b01edbSRob Herring tristate "Highbank Memory Controller" 341*e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 342a1b01edbSRob Herring help 343a1b01edbSRob Herring Support for error detection and correction on the 344a1b01edbSRob Herring Calxeda Highbank memory controller. 345a1b01edbSRob Herring 34669154d06SRob Herringconfig EDAC_HIGHBANK_L2 34769154d06SRob Herring tristate "Highbank L2 Cache" 348*e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 34969154d06SRob Herring help 35069154d06SRob Herring Support for error detection and correction on the 35169154d06SRob Herring Calxeda Highbank memory controller. 35269154d06SRob Herring 353f65aad41SRalf Baechleconfig EDAC_OCTEON_PC 354f65aad41SRalf Baechle tristate "Cavium Octeon Primary Caches" 355*e3c4ff6dSBorislav Petkov depends on CPU_CAVIUM_OCTEON 356f65aad41SRalf Baechle help 357f65aad41SRalf Baechle Support for error detection and correction on the primary caches of 358f65aad41SRalf Baechle the cnMIPS cores of Cavium Octeon family SOCs. 359f65aad41SRalf Baechle 360f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C 361f65aad41SRalf Baechle tristate "Cavium Octeon Secondary Caches (L2C)" 362*e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 363f65aad41SRalf Baechle help 364f65aad41SRalf Baechle Support for error detection and correction on the 365f65aad41SRalf Baechle Cavium Octeon family of SOCs. 366f65aad41SRalf Baechle 367f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC 368f65aad41SRalf Baechle tristate "Cavium Octeon DRAM Memory Controller (LMC)" 369*e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 370f65aad41SRalf Baechle help 371f65aad41SRalf Baechle Support for error detection and correction on the 372f65aad41SRalf Baechle Cavium Octeon family of SOCs. 373f65aad41SRalf Baechle 374f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI 375f65aad41SRalf Baechle tristate "Cavium Octeon PCI Controller" 376*e3c4ff6dSBorislav Petkov depends on PCI && CAVIUM_OCTEON_SOC 377f65aad41SRalf Baechle help 378f65aad41SRalf Baechle Support for error detection and correction on the 379f65aad41SRalf Baechle Cavium Octeon family of SOCs. 380f65aad41SRalf Baechle 38141003396SSergey Temerkhanovconfig EDAC_THUNDERX 38241003396SSergey Temerkhanov tristate "Cavium ThunderX EDAC" 38341003396SSergey Temerkhanov depends on ARM64 38441003396SSergey Temerkhanov depends on PCI 38541003396SSergey Temerkhanov help 38641003396SSergey Temerkhanov Support for error detection and correction on the 38741003396SSergey Temerkhanov Cavium ThunderX memory controllers (LMC), Cache 38841003396SSergey Temerkhanov Coherent Processor Interconnect (CCPI) and L2 cache 38941003396SSergey Temerkhanov blocks (TAD, CBC, MCI). 39041003396SSergey Temerkhanov 391c3eea194SThor Thayerconfig EDAC_ALTERA 392c3eea194SThor Thayer bool "Altera SOCFPGA ECC" 393*e3c4ff6dSBorislav Petkov depends on EDAC=y && ARCH_SOCFPGA 39471bcada8SThor Thayer help 39571bcada8SThor Thayer Support for error detection and correction on the 396c3eea194SThor Thayer Altera SOCs. This must be selected for SDRAM ECC. 397c3eea194SThor Thayer Note that the preloader must initialize the SDRAM 398c3eea194SThor Thayer before loading the kernel. 399c3eea194SThor Thayer 400c3eea194SThor Thayerconfig EDAC_ALTERA_L2C 401c3eea194SThor Thayer bool "Altera L2 Cache ECC" 4023a8f21f1SThor Thayer depends on EDAC_ALTERA=y && CACHE_L2X0 403c3eea194SThor Thayer help 404c3eea194SThor Thayer Support for error detection and correction on the 405c3eea194SThor Thayer Altera L2 cache Memory for Altera SoCs. This option 4063a8f21f1SThor Thayer requires L2 cache. 407c3eea194SThor Thayer 408c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM 409c3eea194SThor Thayer bool "Altera On-Chip RAM ECC" 410c3eea194SThor Thayer depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 411c3eea194SThor Thayer help 412c3eea194SThor Thayer Support for error detection and correction on the 413c3eea194SThor Thayer Altera On-Chip RAM Memory for Altera SoCs. 41471bcada8SThor Thayer 415ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET 416ab8c1e0fSThor Thayer bool "Altera Ethernet FIFO ECC" 417ab8c1e0fSThor Thayer depends on EDAC_ALTERA=y 418ab8c1e0fSThor Thayer help 419ab8c1e0fSThor Thayer Support for error detection and correction on the 420ab8c1e0fSThor Thayer Altera Ethernet FIFO Memory for Altera SoCs. 421ab8c1e0fSThor Thayer 422c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND 423c6882fb2SThor Thayer bool "Altera NAND FIFO ECC" 424c6882fb2SThor Thayer depends on EDAC_ALTERA=y && MTD_NAND_DENALI 425c6882fb2SThor Thayer help 426c6882fb2SThor Thayer Support for error detection and correction on the 427c6882fb2SThor Thayer Altera NAND FIFO Memory for Altera SoCs. 428c6882fb2SThor Thayer 429e8263793SThor Thayerconfig EDAC_ALTERA_DMA 430e8263793SThor Thayer bool "Altera DMA FIFO ECC" 431e8263793SThor Thayer depends on EDAC_ALTERA=y && PL330_DMA=y 432e8263793SThor Thayer help 433e8263793SThor Thayer Support for error detection and correction on the 434e8263793SThor Thayer Altera DMA FIFO Memory for Altera SoCs. 435e8263793SThor Thayer 436c609581dSThor Thayerconfig EDAC_ALTERA_USB 437c609581dSThor Thayer bool "Altera USB FIFO ECC" 438c609581dSThor Thayer depends on EDAC_ALTERA=y && USB_DWC2 439c609581dSThor Thayer help 440c609581dSThor Thayer Support for error detection and correction on the 441c609581dSThor Thayer Altera USB FIFO Memory for Altera SoCs. 442c609581dSThor Thayer 443485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI 444485fe9e2SThor Thayer bool "Altera QSPI FIFO ECC" 445485fe9e2SThor Thayer depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 446485fe9e2SThor Thayer help 447485fe9e2SThor Thayer Support for error detection and correction on the 448485fe9e2SThor Thayer Altera QSPI FIFO Memory for Altera SoCs. 449485fe9e2SThor Thayer 45091104984SThor Thayerconfig EDAC_ALTERA_SDMMC 45191104984SThor Thayer bool "Altera SDMMC FIFO ECC" 45291104984SThor Thayer depends on EDAC_ALTERA=y && MMC_DW 45391104984SThor Thayer help 45491104984SThor Thayer Support for error detection and correction on the 45591104984SThor Thayer Altera SDMMC FIFO Memory for Altera SoCs. 45691104984SThor Thayer 457ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS 458ae9b56e3SPunnaiah Choudary Kalluri tristate "Synopsys DDR Memory Controller" 459*e3c4ff6dSBorislav Petkov depends on ARCH_ZYNQ 460ae9b56e3SPunnaiah Choudary Kalluri help 461ae9b56e3SPunnaiah Choudary Kalluri Support for error detection and correction on the Synopsys DDR 462ae9b56e3SPunnaiah Choudary Kalluri memory controller. 463ae9b56e3SPunnaiah Choudary Kalluri 4640d442930SLoc Hoconfig EDAC_XGENE 4650d442930SLoc Ho tristate "APM X-Gene SoC" 466*e3c4ff6dSBorislav Petkov depends on (ARM64 || COMPILE_TEST) 4670d442930SLoc Ho help 4680d442930SLoc Ho Support for error detection and correction on the 4690d442930SLoc Ho APM X-Gene family of SOCs. 4700d442930SLoc Ho 471751cb5e5SJan Engelhardtendif # EDAC 472