xref: /linux/drivers/edac/Kconfig (revision e23a7cdeb3da8d3ca943fced1420020c1d524684)
1da9bb1d2SAlan Cox#
2da9bb1d2SAlan Cox#	EDAC Kconfig
34577ca55SDoug Thompson#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4da9bb1d2SAlan Cox#	Licensed and distributed under the GPL
5b01aec9bSBorislav Petkov
6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB
7b01aec9bSBorislav Petkov	bool
8da9bb1d2SAlan Cox
954451663SBorislav Petkovconfig EDAC_SUPPORT
1054451663SBorislav Petkov	bool
1154451663SBorislav Petkov
12751cb5e5SJan Engelhardtmenuconfig EDAC
13e3c4ff6dSBorislav Petkov	tristate "EDAC (Error Detection And Correction) reporting"
14e3c4ff6dSBorislav Petkov	depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15da9bb1d2SAlan Cox	help
16a06b85ffSBorislav Petkov	  EDAC is a subsystem along with hardware-specific drivers designed to
17a06b85ffSBorislav Petkov	  report hardware errors. These are low-level errors that are reported
18a06b85ffSBorislav Petkov	  in the CPU or supporting chipset or other subsystems:
198cb2a398SDouglas Thompson	  memory errors, cache errors, PCI errors, thermal throttling, etc..
208cb2a398SDouglas Thompson	  If unsure, select 'Y'.
21da9bb1d2SAlan Cox
22a06b85ffSBorislav Petkov	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
2357c432b5STim Small
24751cb5e5SJan Engelhardtif EDAC
25da9bb1d2SAlan Cox
2619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS
2719974710SMauro Carvalho Chehab	bool "EDAC legacy sysfs"
2819974710SMauro Carvalho Chehab	default y
2919974710SMauro Carvalho Chehab	help
3019974710SMauro Carvalho Chehab	  Enable the compatibility sysfs nodes.
3119974710SMauro Carvalho Chehab	  Use 'Y' if your edac utilities aren't ported to work with the newer
3219974710SMauro Carvalho Chehab	  structures.
3319974710SMauro Carvalho Chehab
34da9bb1d2SAlan Coxconfig EDAC_DEBUG
35da9bb1d2SAlan Cox	bool "Debugging"
361c5bf781SBorislav Petkov	select DEBUG_FS
37da9bb1d2SAlan Cox	help
3837929874SBorislav Petkov	  This turns on debugging information for the entire EDAC subsystem.
3937929874SBorislav Petkov	  You do so by inserting edac_module with "edac_debug_level=x." Valid
4037929874SBorislav Petkov	  levels are 0-4 (from low to high) and by default it is set to 2.
4137929874SBorislav Petkov	  Usually you should select 'N' here.
42da9bb1d2SAlan Cox
430d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE
440d18b2e3SBorislav Petkov	tristate "Decode MCEs in human-readable form (only on AMD for now)"
45168eb34dSBorislav Petkov	depends on CPU_SUP_AMD && X86_MCE_AMD
460d18b2e3SBorislav Petkov	default y
47a7f7f624SMasahiro Yamada	help
480d18b2e3SBorislav Petkov	  Enable this option if you want to decode Machine Check Exceptions
4925985edcSLucas De Marchi	  occurring on your machine in human-readable form.
500d18b2e3SBorislav Petkov
510d18b2e3SBorislav Petkov	  You should definitely say Y here in case you want to decode MCEs
520d18b2e3SBorislav Petkov	  which occur really early upon boot, before the module infrastructure
530d18b2e3SBorislav Petkov	  has been initialized.
540d18b2e3SBorislav Petkov
5577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES
5677c5f5d2SMauro Carvalho Chehab	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57e3c4ff6dSBorislav Petkov	depends on ACPI_APEI_GHES && (EDAC=y)
5877c5f5d2SMauro Carvalho Chehab	help
5977c5f5d2SMauro Carvalho Chehab	  Not all machines support hardware-driven error report. Some of those
6077c5f5d2SMauro Carvalho Chehab	  provide a BIOS-driven error report mechanism via ACPI, using the
6177c5f5d2SMauro Carvalho Chehab	  APEI/GHES driver. By enabling this option, the error reports provided
6277c5f5d2SMauro Carvalho Chehab	  by GHES are sent to userspace via the EDAC API.
6377c5f5d2SMauro Carvalho Chehab
6477c5f5d2SMauro Carvalho Chehab	  When this option is enabled, it will disable the hardware-driven
6577c5f5d2SMauro Carvalho Chehab	  mechanisms, if a GHES BIOS is detected, entering into the
6677c5f5d2SMauro Carvalho Chehab	  "Firmware First" mode.
6777c5f5d2SMauro Carvalho Chehab
6877c5f5d2SMauro Carvalho Chehab	  It should be noticed that keeping both GHES and a hardware-driven
6977c5f5d2SMauro Carvalho Chehab	  error mechanism won't work well, as BIOS will race with OS, while
7077c5f5d2SMauro Carvalho Chehab	  reading the error registers. So, if you want to not use "Firmware
7177c5f5d2SMauro Carvalho Chehab	  first" GHES error mechanism, you should disable GHES either at
7277c5f5d2SMauro Carvalho Chehab	  compilation time or by passing "ghes.disable=1" Kernel parameter
7377c5f5d2SMauro Carvalho Chehab	  at boot time.
7477c5f5d2SMauro Carvalho Chehab
7577c5f5d2SMauro Carvalho Chehab	  In doubt, say 'Y'.
7677c5f5d2SMauro Carvalho Chehab
777d6034d3SDoug Thompsonconfig EDAC_AMD64
78f5b10c45STomasz Pala	tristate "AMD64 (Opteron, Athlon64)"
79e3c4ff6dSBorislav Petkov	depends on AMD_NB && EDAC_DECODE_MCE
807d6034d3SDoug Thompson	help
81027dbd6fSBorislav Petkov	  Support for error detection and correction of DRAM ECC errors on
82f5b10c45STomasz Pala	  the AMD64 families (>= K8) of memory controllers.
837d6034d3SDoug Thompson
847d6034d3SDoug Thompsonconfig EDAC_AMD64_ERROR_INJECTION
859cdeb404SBorislav Petkov	bool "Sysfs HW Error injection facilities"
867d6034d3SDoug Thompson	depends on EDAC_AMD64
877d6034d3SDoug Thompson	help
887d6034d3SDoug Thompson	  Recent Opterons (Family 10h and later) provide for Memory Error
897d6034d3SDoug Thompson	  Injection into the ECC detection circuits. The amd64_edac module
907d6034d3SDoug Thompson	  allows the operator/user to inject Uncorrectable and Correctable
917d6034d3SDoug Thompson	  errors into DRAM.
927d6034d3SDoug Thompson
937d6034d3SDoug Thompson	  When enabled, in each of the respective memory controller directories
947d6034d3SDoug Thompson	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:
957d6034d3SDoug Thompson
967d6034d3SDoug Thompson	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
977d6034d3SDoug Thompson	  - inject_word (0..8, 16-bit word of 16-byte section),
987d6034d3SDoug Thompson	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
997d6034d3SDoug Thompson
1007d6034d3SDoug Thompson	  In addition, there are two control files, inject_read and inject_write,
1017d6034d3SDoug Thompson	  which trigger the DRAM ECC Read and Write respectively.
102da9bb1d2SAlan Cox
103*e23a7cdeSTalel Shenharconfig EDAC_AL_MC
104*e23a7cdeSTalel Shenhar	tristate "Amazon's Annapurna Lab Memory Controller"
105*e23a7cdeSTalel Shenhar	depends on (ARCH_ALPINE || COMPILE_TEST)
106*e23a7cdeSTalel Shenhar	help
107*e23a7cdeSTalel Shenhar	  Support for error detection and correction for Amazon's Annapurna
108*e23a7cdeSTalel Shenhar	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.
109*e23a7cdeSTalel Shenhar
110da9bb1d2SAlan Coxconfig EDAC_AMD76X
111da9bb1d2SAlan Cox	tristate "AMD 76x (760, 762, 768)"
112e3c4ff6dSBorislav Petkov	depends on PCI && X86_32
113da9bb1d2SAlan Cox	help
114da9bb1d2SAlan Cox	  Support for error detection and correction on the AMD 76x
115da9bb1d2SAlan Cox	  series of chipsets used with the Athlon processor.
116da9bb1d2SAlan Cox
117da9bb1d2SAlan Coxconfig EDAC_E7XXX
118da9bb1d2SAlan Cox	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
119e3c4ff6dSBorislav Petkov	depends on PCI && X86_32
120da9bb1d2SAlan Cox	help
121da9bb1d2SAlan Cox	  Support for error detection and correction on the Intel
122da9bb1d2SAlan Cox	  E7205, E7500, E7501 and E7505 server chipsets.
123da9bb1d2SAlan Cox
124da9bb1d2SAlan Coxconfig EDAC_E752X
1255135b797SAndrei Konovalov	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
126e3c4ff6dSBorislav Petkov	depends on PCI && X86
127da9bb1d2SAlan Cox	help
128da9bb1d2SAlan Cox	  Support for error detection and correction on the Intel
129da9bb1d2SAlan Cox	  E7520, E7525, E7320 server chipsets.
130da9bb1d2SAlan Cox
1315a2c675cSTim Smallconfig EDAC_I82443BXGX
1325a2c675cSTim Small	tristate "Intel 82443BX/GX (440BX/GX)"
133e3c4ff6dSBorislav Petkov	depends on PCI && X86_32
13428f96eeaSAndrew Morton	depends on BROKEN
1355a2c675cSTim Small	help
1365a2c675cSTim Small	  Support for error detection and correction on the Intel
1375a2c675cSTim Small	  82443BX/GX memory controllers (440BX/GX chipsets).
1385a2c675cSTim Small
139da9bb1d2SAlan Coxconfig EDAC_I82875P
140da9bb1d2SAlan Cox	tristate "Intel 82875p (D82875P, E7210)"
141e3c4ff6dSBorislav Petkov	depends on PCI && X86_32
142da9bb1d2SAlan Cox	help
143da9bb1d2SAlan Cox	  Support for error detection and correction on the Intel
144da9bb1d2SAlan Cox	  DP82785P and E7210 server chipsets.
145da9bb1d2SAlan Cox
146420390f0SRanganathan Desikanconfig EDAC_I82975X
147420390f0SRanganathan Desikan	tristate "Intel 82975x (D82975x)"
148e3c4ff6dSBorislav Petkov	depends on PCI && X86
149420390f0SRanganathan Desikan	help
150420390f0SRanganathan Desikan	  Support for error detection and correction on the Intel
151420390f0SRanganathan Desikan	  DP82975x server chipsets.
152420390f0SRanganathan Desikan
153535c6a53SJason Uhlenkottconfig EDAC_I3000
154535c6a53SJason Uhlenkott	tristate "Intel 3000/3010"
155e3c4ff6dSBorislav Petkov	depends on PCI && X86
156535c6a53SJason Uhlenkott	help
157535c6a53SJason Uhlenkott	  Support for error detection and correction on the Intel
158535c6a53SJason Uhlenkott	  3000 and 3010 server chipsets.
159535c6a53SJason Uhlenkott
160dd8ef1dbSJason Uhlenkottconfig EDAC_I3200
161dd8ef1dbSJason Uhlenkott	tristate "Intel 3200"
162e3c4ff6dSBorislav Petkov	depends on PCI && X86
163dd8ef1dbSJason Uhlenkott	help
164dd8ef1dbSJason Uhlenkott	  Support for error detection and correction on the Intel
165dd8ef1dbSJason Uhlenkott	  3200 and 3210 server chipsets.
166dd8ef1dbSJason Uhlenkott
1677ee40b89SJason Baronconfig EDAC_IE31200
1687ee40b89SJason Baron	tristate "Intel e312xx"
169e3c4ff6dSBorislav Petkov	depends on PCI && X86
1707ee40b89SJason Baron	help
1717ee40b89SJason Baron	  Support for error detection and correction on the Intel
1727ee40b89SJason Baron	  E3-1200 based DRAM controllers.
1737ee40b89SJason Baron
174df8bc08cSHitoshi Mitakeconfig EDAC_X38
175df8bc08cSHitoshi Mitake	tristate "Intel X38"
176e3c4ff6dSBorislav Petkov	depends on PCI && X86
177df8bc08cSHitoshi Mitake	help
178df8bc08cSHitoshi Mitake	  Support for error detection and correction on the Intel
179df8bc08cSHitoshi Mitake	  X38 server chipsets.
180df8bc08cSHitoshi Mitake
181920c8df6SMauro Carvalho Chehabconfig EDAC_I5400
182920c8df6SMauro Carvalho Chehab	tristate "Intel 5400 (Seaburg) chipsets"
183e3c4ff6dSBorislav Petkov	depends on PCI && X86
184920c8df6SMauro Carvalho Chehab	help
185920c8df6SMauro Carvalho Chehab	  Support for error detection and correction the Intel
186920c8df6SMauro Carvalho Chehab	  i5400 MCH chipset (Seaburg).
187920c8df6SMauro Carvalho Chehab
188a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE
189a0c36a1fSMauro Carvalho Chehab	tristate "Intel i7 Core (Nehalem) processors"
190e3c4ff6dSBorislav Petkov	depends on PCI && X86 && X86_MCE_INTEL
191a0c36a1fSMauro Carvalho Chehab	help
192a0c36a1fSMauro Carvalho Chehab	  Support for error detection and correction the Intel
193696e409dSMauro Carvalho Chehab	  i7 Core (Nehalem) Integrated Memory Controller that exists on
194696e409dSMauro Carvalho Chehab	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
195696e409dSMauro Carvalho Chehab	  and Xeon 55xx processors.
196a0c36a1fSMauro Carvalho Chehab
197da9bb1d2SAlan Coxconfig EDAC_I82860
198da9bb1d2SAlan Cox	tristate "Intel 82860"
199e3c4ff6dSBorislav Petkov	depends on PCI && X86_32
200da9bb1d2SAlan Cox	help
201da9bb1d2SAlan Cox	  Support for error detection and correction on the Intel
202da9bb1d2SAlan Cox	  82860 chipset.
203da9bb1d2SAlan Cox
204da9bb1d2SAlan Coxconfig EDAC_R82600
205da9bb1d2SAlan Cox	tristate "Radisys 82600 embedded chipset"
206e3c4ff6dSBorislav Petkov	depends on PCI && X86_32
207da9bb1d2SAlan Cox	help
208da9bb1d2SAlan Cox	  Support for error detection and correction on the Radisys
209da9bb1d2SAlan Cox	  82600 embedded chipset.
210da9bb1d2SAlan Cox
211eb60705aSEric Wollesenconfig EDAC_I5000
212eb60705aSEric Wollesen	tristate "Intel Greencreek/Blackford chipset"
213e3c4ff6dSBorislav Petkov	depends on X86 && PCI
214eb60705aSEric Wollesen	help
215eb60705aSEric Wollesen	  Support for error detection and correction the Intel
216eb60705aSEric Wollesen	  Greekcreek/Blackford chipsets.
217eb60705aSEric Wollesen
2188f421c59SArthur Jonesconfig EDAC_I5100
2198f421c59SArthur Jones	tristate "Intel San Clemente MCH"
220e3c4ff6dSBorislav Petkov	depends on X86 && PCI
2218f421c59SArthur Jones	help
2228f421c59SArthur Jones	  Support for error detection and correction the Intel
2238f421c59SArthur Jones	  San Clemente MCH.
2248f421c59SArthur Jones
225fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300
226fcaf780bSMauro Carvalho Chehab	tristate "Intel Clarksboro MCH"
227e3c4ff6dSBorislav Petkov	depends on X86 && PCI
228fcaf780bSMauro Carvalho Chehab	help
229fcaf780bSMauro Carvalho Chehab	  Support for error detection and correction the Intel
230fcaf780bSMauro Carvalho Chehab	  Clarksboro MCH (Intel 7300 chipset).
231fcaf780bSMauro Carvalho Chehab
2323d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE
23350d1bb93SAristeu Rozanski	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
234e3c4ff6dSBorislav Petkov	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
2353d78c9afSMauro Carvalho Chehab	help
2363d78c9afSMauro Carvalho Chehab	  Support for error detection and correction the Intel
23750d1bb93SAristeu Rozanski	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
2383d78c9afSMauro Carvalho Chehab
2394ec656bdSTony Luckconfig EDAC_SKX
2404ec656bdSTony Luck	tristate "Intel Skylake server Integrated MC"
24124c9d423SLuck, Tony	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
242de245ae0SRandy Dunlap	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
24358ca9ac1STony Luck	select DMI
24424c9d423SLuck, Tony	select ACPI_ADXL
2454ec656bdSTony Luck	help
2464ec656bdSTony Luck	  Support for error detection and correction the Intel
24758ca9ac1STony Luck	  Skylake server Integrated Memory Controllers. If your
24858ca9ac1STony Luck	  system has non-volatile DIMMs you should also manually
24958ca9ac1STony Luck	  select CONFIG_ACPI_NFIT.
2504ec656bdSTony Luck
251d4dc89d0SQiuxu Zhuoconfig EDAC_I10NM
252d4dc89d0SQiuxu Zhuo	tristate "Intel 10nm server Integrated MC"
253d6a9f733STony Luck	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
254d4dc89d0SQiuxu Zhuo	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
255d4dc89d0SQiuxu Zhuo	select DMI
256d6a9f733STony Luck	select ACPI_ADXL
257d4dc89d0SQiuxu Zhuo	help
258d4dc89d0SQiuxu Zhuo	  Support for error detection and correction the Intel
259d4dc89d0SQiuxu Zhuo	  10nm server Integrated Memory Controllers. If your
260d4dc89d0SQiuxu Zhuo	  system has non-volatile DIMMs you should also manually
261d4dc89d0SQiuxu Zhuo	  select CONFIG_ACPI_NFIT.
262d4dc89d0SQiuxu Zhuo
2635c71ad17STony Luckconfig EDAC_PND2
2645c71ad17STony Luck	tristate "Intel Pondicherry2"
265e3c4ff6dSBorislav Petkov	depends on PCI && X86_64 && X86_MCE_INTEL
2665c71ad17STony Luck	help
2675c71ad17STony Luck	  Support for error detection and correction on the Intel
2685c71ad17STony Luck	  Pondicherry2 Integrated Memory Controller. This SoC IP is
2695c71ad17STony Luck	  first used on the Apollo Lake platform and Denverton
2705c71ad17STony Luck	  micro-server but may appear on others in the future.
2715c71ad17STony Luck
272a9a753d5SDave Jiangconfig EDAC_MPC85XX
2732b8358a9SMichael Ellerman	bool "Freescale MPC83xx / MPC85xx"
2742b8358a9SMichael Ellerman	depends on FSL_SOC && EDAC=y
275a9a753d5SDave Jiang	help
276a9a753d5SDave Jiang	  Support for error detection and correction on the Freescale
27774210267SYork Sun	  MPC8349, MPC8560, MPC8540, MPC8548, T4240
278a9a753d5SDave Jiang
279eeb3d68bSYork Sunconfig EDAC_LAYERSCAPE
280eeb3d68bSYork Sun	tristate "Freescale Layerscape DDR"
28128dd6726SRasmus Villemoes	depends on ARCH_LAYERSCAPE || SOC_LS1021A
282eeb3d68bSYork Sun	help
283eeb3d68bSYork Sun	  Support for error detection and correction on Freescale memory
284eeb3d68bSYork Sun	  controllers on Layerscape SoCs.
285eeb3d68bSYork Sun
2864f4aeeabSDave Jiangconfig EDAC_MV64X60
2874f4aeeabSDave Jiang	tristate "Marvell MV64x60"
288e3c4ff6dSBorislav Petkov	depends on MV64X60
2894f4aeeabSDave Jiang	help
2904f4aeeabSDave Jiang	  Support for error detection and correction on the Marvell
2914f4aeeabSDave Jiang	  MV64360 and MV64460 chipsets.
2924f4aeeabSDave Jiang
2937d8536fbSEgor Martovetskyconfig EDAC_PASEMI
2947d8536fbSEgor Martovetsky	tristate "PA Semi PWRficient"
295e3c4ff6dSBorislav Petkov	depends on PPC_PASEMI && PCI
2967d8536fbSEgor Martovetsky	help
2977d8536fbSEgor Martovetsky	  Support for error detection and correction on PA Semi
2987d8536fbSEgor Martovetsky	  PWRficient.
2997d8536fbSEgor Martovetsky
30048764e41SBenjamin Herrenschmidtconfig EDAC_CELL
30148764e41SBenjamin Herrenschmidt	tristate "Cell Broadband Engine memory controller"
302e3c4ff6dSBorislav Petkov	depends on PPC_CELL_COMMON
30348764e41SBenjamin Herrenschmidt	help
30448764e41SBenjamin Herrenschmidt	  Support for error detection and correction on the
30548764e41SBenjamin Herrenschmidt	  Cell Broadband Engine internal memory controller
30648764e41SBenjamin Herrenschmidt	  on platform without a hypervisor
3077d8536fbSEgor Martovetsky
308dba7a77cSGrant Ericksonconfig EDAC_PPC4XX
309dba7a77cSGrant Erickson	tristate "PPC4xx IBM DDR2 Memory Controller"
310e3c4ff6dSBorislav Petkov	depends on 4xx
311dba7a77cSGrant Erickson	help
312dba7a77cSGrant Erickson	  This enables support for EDAC on the ECC memory used
313dba7a77cSGrant Erickson	  with the IBM DDR2 memory controller found in various
314dba7a77cSGrant Erickson	  PowerPC 4xx embedded processors such as the 405EX[r],
315dba7a77cSGrant Erickson	  440SP, 440SPe, 460EX, 460GT and 460SX.
316dba7a77cSGrant Erickson
317e8765584SHarry Ciaoconfig EDAC_AMD8131
318e8765584SHarry Ciao	tristate "AMD8131 HyperTransport PCI-X Tunnel"
319e3c4ff6dSBorislav Petkov	depends on PCI && PPC_MAPLE
320e8765584SHarry Ciao	help
321e8765584SHarry Ciao	  Support for error detection and correction on the
322e8765584SHarry Ciao	  AMD8131 HyperTransport PCI-X Tunnel chip.
323715fe7afSHarry Ciao	  Note, add more Kconfig dependency if it's adopted
324715fe7afSHarry Ciao	  on some machine other than Maple.
325e8765584SHarry Ciao
32658b4ce6fSHarry Ciaoconfig EDAC_AMD8111
32758b4ce6fSHarry Ciao	tristate "AMD8111 HyperTransport I/O Hub"
328e3c4ff6dSBorislav Petkov	depends on PCI && PPC_MAPLE
32958b4ce6fSHarry Ciao	help
33058b4ce6fSHarry Ciao	  Support for error detection and correction on the
33158b4ce6fSHarry Ciao	  AMD8111 HyperTransport I/O Hub chip.
332715fe7afSHarry Ciao	  Note, add more Kconfig dependency if it's adopted
333715fe7afSHarry Ciao	  on some machine other than Maple.
33458b4ce6fSHarry Ciao
3352a9036afSHarry Ciaoconfig EDAC_CPC925
3362a9036afSHarry Ciao	tristate "IBM CPC925 Memory Controller (PPC970FX)"
337e3c4ff6dSBorislav Petkov	depends on PPC64
3382a9036afSHarry Ciao	help
3392a9036afSHarry Ciao	  Support for error detection and correction on the
3402a9036afSHarry Ciao	  IBM CPC925 Bridge and Memory Controller, which is
3412a9036afSHarry Ciao	  a companion chip to the PowerPC 970 family of
3422a9036afSHarry Ciao	  processors.
3432a9036afSHarry Ciao
344a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC
345a1b01edbSRob Herring	tristate "Highbank Memory Controller"
346e3c4ff6dSBorislav Petkov	depends on ARCH_HIGHBANK
347a1b01edbSRob Herring	help
348a1b01edbSRob Herring	  Support for error detection and correction on the
349a1b01edbSRob Herring	  Calxeda Highbank memory controller.
350a1b01edbSRob Herring
35169154d06SRob Herringconfig EDAC_HIGHBANK_L2
35269154d06SRob Herring	tristate "Highbank L2 Cache"
353e3c4ff6dSBorislav Petkov	depends on ARCH_HIGHBANK
35469154d06SRob Herring	help
35569154d06SRob Herring	  Support for error detection and correction on the
35669154d06SRob Herring	  Calxeda Highbank memory controller.
35769154d06SRob Herring
358f65aad41SRalf Baechleconfig EDAC_OCTEON_PC
359f65aad41SRalf Baechle	tristate "Cavium Octeon Primary Caches"
360e3c4ff6dSBorislav Petkov	depends on CPU_CAVIUM_OCTEON
361f65aad41SRalf Baechle	help
362f65aad41SRalf Baechle	  Support for error detection and correction on the primary caches of
363f65aad41SRalf Baechle	  the cnMIPS cores of Cavium Octeon family SOCs.
364f65aad41SRalf Baechle
365f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C
366f65aad41SRalf Baechle	tristate "Cavium Octeon Secondary Caches (L2C)"
367e3c4ff6dSBorislav Petkov	depends on CAVIUM_OCTEON_SOC
368f65aad41SRalf Baechle	help
369f65aad41SRalf Baechle	  Support for error detection and correction on the
370f65aad41SRalf Baechle	  Cavium Octeon family of SOCs.
371f65aad41SRalf Baechle
372f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC
373f65aad41SRalf Baechle	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
374e3c4ff6dSBorislav Petkov	depends on CAVIUM_OCTEON_SOC
375f65aad41SRalf Baechle	help
376f65aad41SRalf Baechle	  Support for error detection and correction on the
377f65aad41SRalf Baechle	  Cavium Octeon family of SOCs.
378f65aad41SRalf Baechle
379f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI
380f65aad41SRalf Baechle	tristate "Cavium Octeon PCI Controller"
381e3c4ff6dSBorislav Petkov	depends on PCI && CAVIUM_OCTEON_SOC
382f65aad41SRalf Baechle	help
383f65aad41SRalf Baechle	  Support for error detection and correction on the
384f65aad41SRalf Baechle	  Cavium Octeon family of SOCs.
385f65aad41SRalf Baechle
38641003396SSergey Temerkhanovconfig EDAC_THUNDERX
38741003396SSergey Temerkhanov	tristate "Cavium ThunderX EDAC"
38841003396SSergey Temerkhanov	depends on ARM64
38941003396SSergey Temerkhanov	depends on PCI
39041003396SSergey Temerkhanov	help
39141003396SSergey Temerkhanov	  Support for error detection and correction on the
39241003396SSergey Temerkhanov	  Cavium ThunderX memory controllers (LMC), Cache
39341003396SSergey Temerkhanov	  Coherent Processor Interconnect (CCPI) and L2 cache
39441003396SSergey Temerkhanov	  blocks (TAD, CBC, MCI).
39541003396SSergey Temerkhanov
396c3eea194SThor Thayerconfig EDAC_ALTERA
397c3eea194SThor Thayer	bool "Altera SOCFPGA ECC"
3983dab6bd5SThor Thayer	depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
39971bcada8SThor Thayer	help
40071bcada8SThor Thayer	  Support for error detection and correction on the
401580b5cf5SThor Thayer	  Altera SOCs. This is the global enable for the
402580b5cf5SThor Thayer	  various Altera peripherals.
403580b5cf5SThor Thayer
404580b5cf5SThor Thayerconfig EDAC_ALTERA_SDRAM
405580b5cf5SThor Thayer	bool "Altera SDRAM ECC"
406580b5cf5SThor Thayer	depends on EDAC_ALTERA=y
407580b5cf5SThor Thayer	help
408580b5cf5SThor Thayer	  Support for error detection and correction on the
409580b5cf5SThor Thayer	  Altera SDRAM Memory for Altera SoCs. Note that the
410580b5cf5SThor Thayer	  preloader must initialize the SDRAM before loading
411580b5cf5SThor Thayer	  the kernel.
412c3eea194SThor Thayer
413c3eea194SThor Thayerconfig EDAC_ALTERA_L2C
414c3eea194SThor Thayer	bool "Altera L2 Cache ECC"
4153a8f21f1SThor Thayer	depends on EDAC_ALTERA=y && CACHE_L2X0
416c3eea194SThor Thayer	help
417c3eea194SThor Thayer	  Support for error detection and correction on the
418c3eea194SThor Thayer	  Altera L2 cache Memory for Altera SoCs. This option
4193a8f21f1SThor Thayer	  requires L2 cache.
420c3eea194SThor Thayer
421c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM
422c3eea194SThor Thayer	bool "Altera On-Chip RAM ECC"
423c3eea194SThor Thayer	depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
424c3eea194SThor Thayer	help
425c3eea194SThor Thayer	  Support for error detection and correction on the
426c3eea194SThor Thayer	  Altera On-Chip RAM Memory for Altera SoCs.
42771bcada8SThor Thayer
428ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET
429ab8c1e0fSThor Thayer	bool "Altera Ethernet FIFO ECC"
430ab8c1e0fSThor Thayer	depends on EDAC_ALTERA=y
431ab8c1e0fSThor Thayer	help
432ab8c1e0fSThor Thayer	  Support for error detection and correction on the
433ab8c1e0fSThor Thayer	  Altera Ethernet FIFO Memory for Altera SoCs.
434ab8c1e0fSThor Thayer
435c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND
436c6882fb2SThor Thayer	bool "Altera NAND FIFO ECC"
437c6882fb2SThor Thayer	depends on EDAC_ALTERA=y && MTD_NAND_DENALI
438c6882fb2SThor Thayer	help
439c6882fb2SThor Thayer	  Support for error detection and correction on the
440c6882fb2SThor Thayer	  Altera NAND FIFO Memory for Altera SoCs.
441c6882fb2SThor Thayer
442e8263793SThor Thayerconfig EDAC_ALTERA_DMA
443e8263793SThor Thayer	bool "Altera DMA FIFO ECC"
444e8263793SThor Thayer	depends on EDAC_ALTERA=y && PL330_DMA=y
445e8263793SThor Thayer	help
446e8263793SThor Thayer	  Support for error detection and correction on the
447e8263793SThor Thayer	  Altera DMA FIFO Memory for Altera SoCs.
448e8263793SThor Thayer
449c609581dSThor Thayerconfig EDAC_ALTERA_USB
450c609581dSThor Thayer	bool "Altera USB FIFO ECC"
451c609581dSThor Thayer	depends on EDAC_ALTERA=y && USB_DWC2
452c609581dSThor Thayer	help
453c609581dSThor Thayer	  Support for error detection and correction on the
454c609581dSThor Thayer	  Altera USB FIFO Memory for Altera SoCs.
455c609581dSThor Thayer
456485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI
457485fe9e2SThor Thayer	bool "Altera QSPI FIFO ECC"
458485fe9e2SThor Thayer	depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
459485fe9e2SThor Thayer	help
460485fe9e2SThor Thayer	  Support for error detection and correction on the
461485fe9e2SThor Thayer	  Altera QSPI FIFO Memory for Altera SoCs.
462485fe9e2SThor Thayer
46391104984SThor Thayerconfig EDAC_ALTERA_SDMMC
46491104984SThor Thayer	bool "Altera SDMMC FIFO ECC"
46591104984SThor Thayer	depends on EDAC_ALTERA=y && MMC_DW
46691104984SThor Thayer	help
46791104984SThor Thayer	  Support for error detection and correction on the
46891104984SThor Thayer	  Altera SDMMC FIFO Memory for Altera SoCs.
46991104984SThor Thayer
47091abaeaaSYash Shahconfig EDAC_SIFIVE
47191abaeaaSYash Shah	bool "Sifive platform EDAC driver"
4729209fb51SChristoph Hellwig	depends on EDAC=y && SIFIVE_L2
47391abaeaaSYash Shah	help
47491abaeaaSYash Shah	  Support for error detection and correction on the SiFive SoCs.
47591abaeaaSYash Shah
4767f6998a4SJan Luebbeconfig EDAC_ARMADA_XP
4777f6998a4SJan Luebbe	bool "Marvell Armada XP DDR and L2 Cache ECC"
4787f6998a4SJan Luebbe	depends on MACH_MVEBU_V7
4797f6998a4SJan Luebbe	help
4807f6998a4SJan Luebbe	  Support for error correction and detection on the Marvell Aramada XP
4817f6998a4SJan Luebbe	  DDR RAM and L2 cache controllers.
4827f6998a4SJan Luebbe
483ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS
484ae9b56e3SPunnaiah Choudary Kalluri	tristate "Synopsys DDR Memory Controller"
485b500b4a0SManish Narani	depends on ARCH_ZYNQ || ARCH_ZYNQMP
486ae9b56e3SPunnaiah Choudary Kalluri	help
487ae9b56e3SPunnaiah Choudary Kalluri	  Support for error detection and correction on the Synopsys DDR
488ae9b56e3SPunnaiah Choudary Kalluri	  memory controller.
489ae9b56e3SPunnaiah Choudary Kalluri
4900d442930SLoc Hoconfig EDAC_XGENE
4910d442930SLoc Ho	tristate "APM X-Gene SoC"
492e3c4ff6dSBorislav Petkov	depends on (ARM64 || COMPILE_TEST)
4930d442930SLoc Ho	help
4940d442930SLoc Ho	  Support for error detection and correction on the
4950d442930SLoc Ho	  APM X-Gene family of SOCs.
4960d442930SLoc Ho
49786a18ee2STero Kristoconfig EDAC_TI
49886a18ee2STero Kristo	tristate "Texas Instruments DDR3 ECC Controller"
49986a18ee2STero Kristo	depends on ARCH_KEYSTONE || SOC_DRA7XX
50086a18ee2STero Kristo	help
501a483e227SKrzysztof Kozlowski	  Support for error detection and correction on the TI SoCs.
50286a18ee2STero Kristo
50327450653SChannagoud Kadabiconfig EDAC_QCOM
50427450653SChannagoud Kadabi	tristate "QCOM EDAC Controller"
50527450653SChannagoud Kadabi	depends on ARCH_QCOM && QCOM_LLCC
50627450653SChannagoud Kadabi	help
50727450653SChannagoud Kadabi	  Support for error detection and correction on the
50827450653SChannagoud Kadabi	  Qualcomm Technologies, Inc. SoCs.
50927450653SChannagoud Kadabi
51027450653SChannagoud Kadabi	  This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
51127450653SChannagoud Kadabi	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
51227450653SChannagoud Kadabi	  of Tag RAM and Data RAM.
51327450653SChannagoud Kadabi
51427450653SChannagoud Kadabi	  For debugging issues having to do with stability and overall system
51527450653SChannagoud Kadabi	  health, you should probably say 'Y' here.
51627450653SChannagoud Kadabi
5179b7e6242SStefan M Schaeckelerconfig EDAC_ASPEED
5189b7e6242SStefan M Schaeckeler	tristate "Aspeed AST 2500 SoC"
5199b7e6242SStefan M Schaeckeler	depends on MACH_ASPEED_G5
5209b7e6242SStefan M Schaeckeler	help
5219b7e6242SStefan M Schaeckeler	  Support for error detection and correction on the Aspeed AST 2500 SoC.
5229b7e6242SStefan M Schaeckeler
5239b7e6242SStefan M Schaeckeler	  First, ECC must be configured in the bootloader. Then, this driver
5249b7e6242SStefan M Schaeckeler	  will expose error counters via the EDAC kernel framework.
5259b7e6242SStefan M Schaeckeler
52682413e56SShravan Kumar Ramaniconfig EDAC_BLUEFIELD
52782413e56SShravan Kumar Ramani	tristate "Mellanox BlueField Memory ECC"
52882413e56SShravan Kumar Ramani	depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
52982413e56SShravan Kumar Ramani	help
53082413e56SShravan Kumar Ramani	  Support for error detection and correction on the
53182413e56SShravan Kumar Ramani	  Mellanox BlueField SoCs.
53282413e56SShravan Kumar Ramani
5331088750dSLei Wangconfig EDAC_DMC520
5341088750dSLei Wang	tristate "ARM DMC-520 ECC"
5351088750dSLei Wang	depends on ARM64
5361088750dSLei Wang	help
5371088750dSLei Wang	  Support for error detection and correction on the
5381088750dSLei Wang	  SoCs with ARM DMC-520 DRAM controller.
5391088750dSLei Wang
540751cb5e5SJan Engelhardtendif # EDAC
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