1da9bb1d2SAlan Cox# 2da9bb1d2SAlan Cox# EDAC Kconfig 34577ca55SDoug Thompson# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4da9bb1d2SAlan Cox# Licensed and distributed under the GPL 5b01aec9bSBorislav Petkov 6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB 7b01aec9bSBorislav Petkov bool 8da9bb1d2SAlan Cox 954451663SBorislav Petkovconfig EDAC_SUPPORT 1054451663SBorislav Petkov bool 1154451663SBorislav Petkov 12751cb5e5SJan Engelhardtmenuconfig EDAC 13e3c4ff6dSBorislav Petkov tristate "EDAC (Error Detection And Correction) reporting" 14e3c4ff6dSBorislav Petkov depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15da9bb1d2SAlan Cox help 16a06b85ffSBorislav Petkov EDAC is a subsystem along with hardware-specific drivers designed to 17a06b85ffSBorislav Petkov report hardware errors. These are low-level errors that are reported 18a06b85ffSBorislav Petkov in the CPU or supporting chipset or other subsystems: 198cb2a398SDouglas Thompson memory errors, cache errors, PCI errors, thermal throttling, etc.. 208cb2a398SDouglas Thompson If unsure, select 'Y'. 21da9bb1d2SAlan Cox 22a06b85ffSBorislav Petkov The mailing list for the EDAC project is linux-edac@vger.kernel.org. 2357c432b5STim Small 24751cb5e5SJan Engelhardtif EDAC 25da9bb1d2SAlan Cox 2619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS 2719974710SMauro Carvalho Chehab bool "EDAC legacy sysfs" 2819974710SMauro Carvalho Chehab default y 2919974710SMauro Carvalho Chehab help 3019974710SMauro Carvalho Chehab Enable the compatibility sysfs nodes. 3119974710SMauro Carvalho Chehab Use 'Y' if your edac utilities aren't ported to work with the newer 3219974710SMauro Carvalho Chehab structures. 3319974710SMauro Carvalho Chehab 34da9bb1d2SAlan Coxconfig EDAC_DEBUG 35da9bb1d2SAlan Cox bool "Debugging" 361c5bf781SBorislav Petkov select DEBUG_FS 37da9bb1d2SAlan Cox help 3837929874SBorislav Petkov This turns on debugging information for the entire EDAC subsystem. 3937929874SBorislav Petkov You do so by inserting edac_module with "edac_debug_level=x." Valid 4037929874SBorislav Petkov levels are 0-4 (from low to high) and by default it is set to 2. 4137929874SBorislav Petkov Usually you should select 'N' here. 42da9bb1d2SAlan Cox 430d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE 440d18b2e3SBorislav Petkov tristate "Decode MCEs in human-readable form (only on AMD for now)" 45168eb34dSBorislav Petkov depends on CPU_SUP_AMD && X86_MCE_AMD 460d18b2e3SBorislav Petkov default y 47a7f7f624SMasahiro Yamada help 480d18b2e3SBorislav Petkov Enable this option if you want to decode Machine Check Exceptions 4925985edcSLucas De Marchi occurring on your machine in human-readable form. 500d18b2e3SBorislav Petkov 510d18b2e3SBorislav Petkov You should definitely say Y here in case you want to decode MCEs 520d18b2e3SBorislav Petkov which occur really early upon boot, before the module infrastructure 530d18b2e3SBorislav Petkov has been initialized. 540d18b2e3SBorislav Petkov 5577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES 56802e7f1dSJia He tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57802e7f1dSJia He depends on ACPI_APEI_GHES 58ed27b5dfSShuai Xue select UEFI_CPER 5977c5f5d2SMauro Carvalho Chehab help 6077c5f5d2SMauro Carvalho Chehab Not all machines support hardware-driven error report. Some of those 6177c5f5d2SMauro Carvalho Chehab provide a BIOS-driven error report mechanism via ACPI, using the 6277c5f5d2SMauro Carvalho Chehab APEI/GHES driver. By enabling this option, the error reports provided 6377c5f5d2SMauro Carvalho Chehab by GHES are sent to userspace via the EDAC API. 6477c5f5d2SMauro Carvalho Chehab 6577c5f5d2SMauro Carvalho Chehab When this option is enabled, it will disable the hardware-driven 6677c5f5d2SMauro Carvalho Chehab mechanisms, if a GHES BIOS is detected, entering into the 6777c5f5d2SMauro Carvalho Chehab "Firmware First" mode. 6877c5f5d2SMauro Carvalho Chehab 6977c5f5d2SMauro Carvalho Chehab It should be noticed that keeping both GHES and a hardware-driven 7077c5f5d2SMauro Carvalho Chehab error mechanism won't work well, as BIOS will race with OS, while 7177c5f5d2SMauro Carvalho Chehab reading the error registers. So, if you want to not use "Firmware 7277c5f5d2SMauro Carvalho Chehab first" GHES error mechanism, you should disable GHES either at 7377c5f5d2SMauro Carvalho Chehab compilation time or by passing "ghes.disable=1" Kernel parameter 7477c5f5d2SMauro Carvalho Chehab at boot time. 7577c5f5d2SMauro Carvalho Chehab 7677c5f5d2SMauro Carvalho Chehab In doubt, say 'Y'. 7777c5f5d2SMauro Carvalho Chehab 78f90b7381SShiju Joseconfig EDAC_SCRUB 79f90b7381SShiju Jose bool "EDAC scrub feature" 80f90b7381SShiju Jose help 81f90b7381SShiju Jose The EDAC scrub feature is optional and is designed to control the 82f90b7381SShiju Jose memory scrubbers in the system. The common sysfs scrub interface 83f90b7381SShiju Jose abstracts the control of various arbitrary scrubbing functionalities 84f90b7381SShiju Jose into a unified set of functions. 85f90b7381SShiju Jose Say 'y/n' to enable/disable EDAC scrub feature. 86f90b7381SShiju Jose 87*bcbd069bSShiju Joseconfig EDAC_ECS 88*bcbd069bSShiju Jose bool "EDAC ECS (Error Check Scrub) feature" 89*bcbd069bSShiju Jose help 90*bcbd069bSShiju Jose The EDAC ECS feature is optional and is designed to control on-die 91*bcbd069bSShiju Jose error check scrub (e.g., DDR5 ECS) in the system. The common sysfs 92*bcbd069bSShiju Jose ECS interface abstracts the control of various ECS functionalities 93*bcbd069bSShiju Jose into a unified set of functions. 94*bcbd069bSShiju Jose Say 'y/n' to enable/disable EDAC ECS feature. 95*bcbd069bSShiju Jose 967d6034d3SDoug Thompsonconfig EDAC_AMD64 97f5b10c45STomasz Pala tristate "AMD64 (Opteron, Athlon64)" 98e3c4ff6dSBorislav Petkov depends on AMD_NB && EDAC_DECODE_MCE 99d6caeafaSMario Limonciello depends on AMD_NODE 1006c9058f4SYazen Ghannam imply AMD_ATL 1017d6034d3SDoug Thompson help 102027dbd6fSBorislav Petkov Support for error detection and correction of DRAM ECC errors on 103f5b10c45STomasz Pala the AMD64 families (>= K8) of memory controllers. 1047d6034d3SDoug Thompson 10561810096SBorislav Petkov When EDAC_DEBUG is enabled, hardware error injection facilities 10661810096SBorislav Petkov through sysfs are available: 10761810096SBorislav Petkov 1081865bc71SBorislav Petkov AMD CPUs up to and excluding family 0x17 provide for Memory 1091865bc71SBorislav Petkov Error Injection into the ECC detection circuits. The amd64_edac 1101865bc71SBorislav Petkov module allows the operator/user to inject Uncorrectable and 1111865bc71SBorislav Petkov Correctable errors into DRAM. 1127d6034d3SDoug Thompson 1137d6034d3SDoug Thompson When enabled, in each of the respective memory controller directories 1147d6034d3SDoug Thompson (/sys/devices/system/edac/mc/mcX), there are 3 input files: 1157d6034d3SDoug Thompson 1167d6034d3SDoug Thompson - inject_section (0..3, 16-byte section of 64-byte cacheline), 1177d6034d3SDoug Thompson - inject_word (0..8, 16-bit word of 16-byte section), 1187d6034d3SDoug Thompson - inject_ecc_vector (hex ecc vector: select bits of inject word) 1197d6034d3SDoug Thompson 1207d6034d3SDoug Thompson In addition, there are two control files, inject_read and inject_write, 1217d6034d3SDoug Thompson which trigger the DRAM ECC Read and Write respectively. 122da9bb1d2SAlan Cox 123e23a7cdeSTalel Shenharconfig EDAC_AL_MC 124e23a7cdeSTalel Shenhar tristate "Amazon's Annapurna Lab Memory Controller" 125e23a7cdeSTalel Shenhar depends on (ARCH_ALPINE || COMPILE_TEST) 126e23a7cdeSTalel Shenhar help 127e23a7cdeSTalel Shenhar Support for error detection and correction for Amazon's Annapurna 128e23a7cdeSTalel Shenhar Labs Alpine chips which allow 1 bit correction and 2 bits detection. 129e23a7cdeSTalel Shenhar 130da9bb1d2SAlan Coxconfig EDAC_AMD76X 131da9bb1d2SAlan Cox tristate "AMD 76x (760, 762, 768)" 132e3c4ff6dSBorislav Petkov depends on PCI && X86_32 133da9bb1d2SAlan Cox help 134da9bb1d2SAlan Cox Support for error detection and correction on the AMD 76x 135da9bb1d2SAlan Cox series of chipsets used with the Athlon processor. 136da9bb1d2SAlan Cox 137da9bb1d2SAlan Coxconfig EDAC_E7XXX 138da9bb1d2SAlan Cox tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 139e3c4ff6dSBorislav Petkov depends on PCI && X86_32 140da9bb1d2SAlan Cox help 141da9bb1d2SAlan Cox Support for error detection and correction on the Intel 142da9bb1d2SAlan Cox E7205, E7500, E7501 and E7505 server chipsets. 143da9bb1d2SAlan Cox 144da9bb1d2SAlan Coxconfig EDAC_E752X 1455135b797SAndrei Konovalov tristate "Intel e752x (e7520, e7525, e7320) and 3100" 146e3c4ff6dSBorislav Petkov depends on PCI && X86 147da9bb1d2SAlan Cox help 148da9bb1d2SAlan Cox Support for error detection and correction on the Intel 149da9bb1d2SAlan Cox E7520, E7525, E7320 server chipsets. 150da9bb1d2SAlan Cox 1515a2c675cSTim Smallconfig EDAC_I82443BXGX 1525a2c675cSTim Small tristate "Intel 82443BX/GX (440BX/GX)" 153e3c4ff6dSBorislav Petkov depends on PCI && X86_32 15428f96eeaSAndrew Morton depends on BROKEN 1555a2c675cSTim Small help 1565a2c675cSTim Small Support for error detection and correction on the Intel 1575a2c675cSTim Small 82443BX/GX memory controllers (440BX/GX chipsets). 1585a2c675cSTim Small 159da9bb1d2SAlan Coxconfig EDAC_I82875P 160da9bb1d2SAlan Cox tristate "Intel 82875p (D82875P, E7210)" 161e3c4ff6dSBorislav Petkov depends on PCI && X86_32 162da9bb1d2SAlan Cox help 163da9bb1d2SAlan Cox Support for error detection and correction on the Intel 164da9bb1d2SAlan Cox DP82785P and E7210 server chipsets. 165da9bb1d2SAlan Cox 166420390f0SRanganathan Desikanconfig EDAC_I82975X 167420390f0SRanganathan Desikan tristate "Intel 82975x (D82975x)" 168e3c4ff6dSBorislav Petkov depends on PCI && X86 169420390f0SRanganathan Desikan help 170420390f0SRanganathan Desikan Support for error detection and correction on the Intel 171420390f0SRanganathan Desikan DP82975x server chipsets. 172420390f0SRanganathan Desikan 173535c6a53SJason Uhlenkottconfig EDAC_I3000 174535c6a53SJason Uhlenkott tristate "Intel 3000/3010" 175e3c4ff6dSBorislav Petkov depends on PCI && X86 176535c6a53SJason Uhlenkott help 177535c6a53SJason Uhlenkott Support for error detection and correction on the Intel 178535c6a53SJason Uhlenkott 3000 and 3010 server chipsets. 179535c6a53SJason Uhlenkott 180dd8ef1dbSJason Uhlenkottconfig EDAC_I3200 181dd8ef1dbSJason Uhlenkott tristate "Intel 3200" 182e3c4ff6dSBorislav Petkov depends on PCI && X86 183dd8ef1dbSJason Uhlenkott help 184dd8ef1dbSJason Uhlenkott Support for error detection and correction on the Intel 185dd8ef1dbSJason Uhlenkott 3200 and 3210 server chipsets. 186dd8ef1dbSJason Uhlenkott 1877ee40b89SJason Baronconfig EDAC_IE31200 1887ee40b89SJason Baron tristate "Intel e312xx" 189e3c4ff6dSBorislav Petkov depends on PCI && X86 1907ee40b89SJason Baron help 1917ee40b89SJason Baron Support for error detection and correction on the Intel 1927ee40b89SJason Baron E3-1200 based DRAM controllers. 1937ee40b89SJason Baron 194df8bc08cSHitoshi Mitakeconfig EDAC_X38 195df8bc08cSHitoshi Mitake tristate "Intel X38" 196e3c4ff6dSBorislav Petkov depends on PCI && X86 197df8bc08cSHitoshi Mitake help 198df8bc08cSHitoshi Mitake Support for error detection and correction on the Intel 199df8bc08cSHitoshi Mitake X38 server chipsets. 200df8bc08cSHitoshi Mitake 201920c8df6SMauro Carvalho Chehabconfig EDAC_I5400 202920c8df6SMauro Carvalho Chehab tristate "Intel 5400 (Seaburg) chipsets" 203e3c4ff6dSBorislav Petkov depends on PCI && X86 204920c8df6SMauro Carvalho Chehab help 205920c8df6SMauro Carvalho Chehab Support for error detection and correction the Intel 206920c8df6SMauro Carvalho Chehab i5400 MCH chipset (Seaburg). 207920c8df6SMauro Carvalho Chehab 208a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE 209a0c36a1fSMauro Carvalho Chehab tristate "Intel i7 Core (Nehalem) processors" 210e3c4ff6dSBorislav Petkov depends on PCI && X86 && X86_MCE_INTEL 211a0c36a1fSMauro Carvalho Chehab help 212a0c36a1fSMauro Carvalho Chehab Support for error detection and correction the Intel 213696e409dSMauro Carvalho Chehab i7 Core (Nehalem) Integrated Memory Controller that exists on 214696e409dSMauro Carvalho Chehab newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 215696e409dSMauro Carvalho Chehab and Xeon 55xx processors. 216a0c36a1fSMauro Carvalho Chehab 217da9bb1d2SAlan Coxconfig EDAC_I82860 218da9bb1d2SAlan Cox tristate "Intel 82860" 219e3c4ff6dSBorislav Petkov depends on PCI && X86_32 220da9bb1d2SAlan Cox help 221da9bb1d2SAlan Cox Support for error detection and correction on the Intel 222da9bb1d2SAlan Cox 82860 chipset. 223da9bb1d2SAlan Cox 224da9bb1d2SAlan Coxconfig EDAC_R82600 225da9bb1d2SAlan Cox tristate "Radisys 82600 embedded chipset" 226e3c4ff6dSBorislav Petkov depends on PCI && X86_32 227da9bb1d2SAlan Cox help 228da9bb1d2SAlan Cox Support for error detection and correction on the Radisys 229da9bb1d2SAlan Cox 82600 embedded chipset. 230da9bb1d2SAlan Cox 231eb60705aSEric Wollesenconfig EDAC_I5000 232eb60705aSEric Wollesen tristate "Intel Greencreek/Blackford chipset" 233e3c4ff6dSBorislav Petkov depends on X86 && PCI 23475564191SAristeu Rozanski depends on BROKEN 235eb60705aSEric Wollesen help 236eb60705aSEric Wollesen Support for error detection and correction the Intel 237eb60705aSEric Wollesen Greekcreek/Blackford chipsets. 238eb60705aSEric Wollesen 2398f421c59SArthur Jonesconfig EDAC_I5100 2408f421c59SArthur Jones tristate "Intel San Clemente MCH" 241e3c4ff6dSBorislav Petkov depends on X86 && PCI 2428f421c59SArthur Jones help 2438f421c59SArthur Jones Support for error detection and correction the Intel 2448f421c59SArthur Jones San Clemente MCH. 2458f421c59SArthur Jones 246fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300 247fcaf780bSMauro Carvalho Chehab tristate "Intel Clarksboro MCH" 248e3c4ff6dSBorislav Petkov depends on X86 && PCI 249fcaf780bSMauro Carvalho Chehab help 250fcaf780bSMauro Carvalho Chehab Support for error detection and correction the Intel 251fcaf780bSMauro Carvalho Chehab Clarksboro MCH (Intel 7300 chipset). 252fcaf780bSMauro Carvalho Chehab 2533d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE 25450d1bb93SAristeu Rozanski tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 255e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2563d78c9afSMauro Carvalho Chehab help 2573d78c9afSMauro Carvalho Chehab Support for error detection and correction the Intel 25850d1bb93SAristeu Rozanski Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2593d78c9afSMauro Carvalho Chehab 2604ec656bdSTony Luckconfig EDAC_SKX 2614ec656bdSTony Luck tristate "Intel Skylake server Integrated MC" 26224c9d423SLuck, Tony depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 263de245ae0SRandy Dunlap depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 26458ca9ac1STony Luck select DMI 26524c9d423SLuck, Tony select ACPI_ADXL 2664ec656bdSTony Luck help 2674ec656bdSTony Luck Support for error detection and correction the Intel 26858ca9ac1STony Luck Skylake server Integrated Memory Controllers. If your 26958ca9ac1STony Luck system has non-volatile DIMMs you should also manually 27058ca9ac1STony Luck select CONFIG_ACPI_NFIT. 2714ec656bdSTony Luck 272d4dc89d0SQiuxu Zhuoconfig EDAC_I10NM 273d4dc89d0SQiuxu Zhuo tristate "Intel 10nm server Integrated MC" 274d6a9f733STony Luck depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 275d4dc89d0SQiuxu Zhuo depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 276d4dc89d0SQiuxu Zhuo select DMI 277d6a9f733STony Luck select ACPI_ADXL 278d4dc89d0SQiuxu Zhuo help 279d4dc89d0SQiuxu Zhuo Support for error detection and correction the Intel 280d4dc89d0SQiuxu Zhuo 10nm server Integrated Memory Controllers. If your 281d4dc89d0SQiuxu Zhuo system has non-volatile DIMMs you should also manually 282d4dc89d0SQiuxu Zhuo select CONFIG_ACPI_NFIT. 283d4dc89d0SQiuxu Zhuo 2845c71ad17STony Luckconfig EDAC_PND2 2855c71ad17STony Luck tristate "Intel Pondicherry2" 286e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL 2877b2db704SAndy Shevchenko select P2SB if X86 2885c71ad17STony Luck help 2895c71ad17STony Luck Support for error detection and correction on the Intel 2905c71ad17STony Luck Pondicherry2 Integrated Memory Controller. This SoC IP is 2915c71ad17STony Luck first used on the Apollo Lake platform and Denverton 2925c71ad17STony Luck micro-server but may appear on others in the future. 2935c71ad17STony Luck 29410590a9dSQiuxu Zhuoconfig EDAC_IGEN6 29510590a9dSQiuxu Zhuo tristate "Intel client SoC Integrated MC" 2960a9ece9bSRandy Dunlap depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 297a1c9ca5fSRandy Dunlap depends on X86_64 && X86_MCE_INTEL 29810590a9dSQiuxu Zhuo help 29910590a9dSQiuxu Zhuo Support for error detection and correction on the Intel 30010590a9dSQiuxu Zhuo client SoC Integrated Memory Controller using In-Band ECC IP. 30110590a9dSQiuxu Zhuo This In-Band ECC is first used on the Elkhart Lake SoC but 30210590a9dSQiuxu Zhuo may appear on others in the future. 30310590a9dSQiuxu Zhuo 304a9a753d5SDave Jiangconfig EDAC_MPC85XX 3052b8358a9SMichael Ellerman bool "Freescale MPC83xx / MPC85xx" 3062b8358a9SMichael Ellerman depends on FSL_SOC && EDAC=y 307a9a753d5SDave Jiang help 308a9a753d5SDave Jiang Support for error detection and correction on the Freescale 30974210267SYork Sun MPC8349, MPC8560, MPC8540, MPC8548, T4240 310a9a753d5SDave Jiang 311eeb3d68bSYork Sunconfig EDAC_LAYERSCAPE 312eeb3d68bSYork Sun tristate "Freescale Layerscape DDR" 31328dd6726SRasmus Villemoes depends on ARCH_LAYERSCAPE || SOC_LS1021A 314eeb3d68bSYork Sun help 315eeb3d68bSYork Sun Support for error detection and correction on Freescale memory 316eeb3d68bSYork Sun controllers on Layerscape SoCs. 317eeb3d68bSYork Sun 3187d8536fbSEgor Martovetskyconfig EDAC_PASEMI 3197d8536fbSEgor Martovetsky tristate "PA Semi PWRficient" 320e3c4ff6dSBorislav Petkov depends on PPC_PASEMI && PCI 3217d8536fbSEgor Martovetsky help 3227d8536fbSEgor Martovetsky Support for error detection and correction on PA Semi 3237d8536fbSEgor Martovetsky PWRficient. 3247d8536fbSEgor Martovetsky 3252a9036afSHarry Ciaoconfig EDAC_CPC925 3262a9036afSHarry Ciao tristate "IBM CPC925 Memory Controller (PPC970FX)" 327e3c4ff6dSBorislav Petkov depends on PPC64 3282a9036afSHarry Ciao help 3292a9036afSHarry Ciao Support for error detection and correction on the 3302a9036afSHarry Ciao IBM CPC925 Bridge and Memory Controller, which is 3312a9036afSHarry Ciao a companion chip to the PowerPC 970 family of 3322a9036afSHarry Ciao processors. 3332a9036afSHarry Ciao 334a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC 335a1b01edbSRob Herring tristate "Highbank Memory Controller" 336e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 337a1b01edbSRob Herring help 338a1b01edbSRob Herring Support for error detection and correction on the 339a1b01edbSRob Herring Calxeda Highbank memory controller. 340a1b01edbSRob Herring 34169154d06SRob Herringconfig EDAC_HIGHBANK_L2 34269154d06SRob Herring tristate "Highbank L2 Cache" 343e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 34469154d06SRob Herring help 34569154d06SRob Herring Support for error detection and correction on the 34669154d06SRob Herring Calxeda Highbank memory controller. 34769154d06SRob Herring 348f65aad41SRalf Baechleconfig EDAC_OCTEON_PC 349f65aad41SRalf Baechle tristate "Cavium Octeon Primary Caches" 350e3c4ff6dSBorislav Petkov depends on CPU_CAVIUM_OCTEON 351f65aad41SRalf Baechle help 352f65aad41SRalf Baechle Support for error detection and correction on the primary caches of 353f65aad41SRalf Baechle the cnMIPS cores of Cavium Octeon family SOCs. 354f65aad41SRalf Baechle 355f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C 356f65aad41SRalf Baechle tristate "Cavium Octeon Secondary Caches (L2C)" 357e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 358f65aad41SRalf Baechle help 359f65aad41SRalf Baechle Support for error detection and correction on the 360f65aad41SRalf Baechle Cavium Octeon family of SOCs. 361f65aad41SRalf Baechle 362f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC 363f65aad41SRalf Baechle tristate "Cavium Octeon DRAM Memory Controller (LMC)" 364e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 365f65aad41SRalf Baechle help 366f65aad41SRalf Baechle Support for error detection and correction on the 367f65aad41SRalf Baechle Cavium Octeon family of SOCs. 368f65aad41SRalf Baechle 369f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI 370f65aad41SRalf Baechle tristate "Cavium Octeon PCI Controller" 371e3c4ff6dSBorislav Petkov depends on PCI && CAVIUM_OCTEON_SOC 372f65aad41SRalf Baechle help 373f65aad41SRalf Baechle Support for error detection and correction on the 374f65aad41SRalf Baechle Cavium Octeon family of SOCs. 375f65aad41SRalf Baechle 37641003396SSergey Temerkhanovconfig EDAC_THUNDERX 37741003396SSergey Temerkhanov tristate "Cavium ThunderX EDAC" 37841003396SSergey Temerkhanov depends on ARM64 37941003396SSergey Temerkhanov depends on PCI 38041003396SSergey Temerkhanov help 38141003396SSergey Temerkhanov Support for error detection and correction on the 38241003396SSergey Temerkhanov Cavium ThunderX memory controllers (LMC), Cache 38341003396SSergey Temerkhanov Coherent Processor Interconnect (CCPI) and L2 cache 38441003396SSergey Temerkhanov blocks (TAD, CBC, MCI). 38541003396SSergey Temerkhanov 386c3eea194SThor Thayerconfig EDAC_ALTERA 387c3eea194SThor Thayer bool "Altera SOCFPGA ECC" 388098da961SKrzysztof Kozlowski depends on EDAC=y && ARCH_INTEL_SOCFPGA 38971bcada8SThor Thayer help 39071bcada8SThor Thayer Support for error detection and correction on the 391580b5cf5SThor Thayer Altera SOCs. This is the global enable for the 392580b5cf5SThor Thayer various Altera peripherals. 393580b5cf5SThor Thayer 394580b5cf5SThor Thayerconfig EDAC_ALTERA_SDRAM 395580b5cf5SThor Thayer bool "Altera SDRAM ECC" 396580b5cf5SThor Thayer depends on EDAC_ALTERA=y 397580b5cf5SThor Thayer help 398580b5cf5SThor Thayer Support for error detection and correction on the 399580b5cf5SThor Thayer Altera SDRAM Memory for Altera SoCs. Note that the 400580b5cf5SThor Thayer preloader must initialize the SDRAM before loading 401580b5cf5SThor Thayer the kernel. 402c3eea194SThor Thayer 403c3eea194SThor Thayerconfig EDAC_ALTERA_L2C 404c3eea194SThor Thayer bool "Altera L2 Cache ECC" 4053a8f21f1SThor Thayer depends on EDAC_ALTERA=y && CACHE_L2X0 406c3eea194SThor Thayer help 407c3eea194SThor Thayer Support for error detection and correction on the 408c3eea194SThor Thayer Altera L2 cache Memory for Altera SoCs. This option 4093a8f21f1SThor Thayer requires L2 cache. 410c3eea194SThor Thayer 411c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM 412c3eea194SThor Thayer bool "Altera On-Chip RAM ECC" 413c3eea194SThor Thayer depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 414c3eea194SThor Thayer help 415c3eea194SThor Thayer Support for error detection and correction on the 416c3eea194SThor Thayer Altera On-Chip RAM Memory for Altera SoCs. 41771bcada8SThor Thayer 418ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET 419ab8c1e0fSThor Thayer bool "Altera Ethernet FIFO ECC" 420ab8c1e0fSThor Thayer depends on EDAC_ALTERA=y 421ab8c1e0fSThor Thayer help 422ab8c1e0fSThor Thayer Support for error detection and correction on the 423ab8c1e0fSThor Thayer Altera Ethernet FIFO Memory for Altera SoCs. 424ab8c1e0fSThor Thayer 425c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND 426c6882fb2SThor Thayer bool "Altera NAND FIFO ECC" 427c6882fb2SThor Thayer depends on EDAC_ALTERA=y && MTD_NAND_DENALI 428c6882fb2SThor Thayer help 429c6882fb2SThor Thayer Support for error detection and correction on the 430c6882fb2SThor Thayer Altera NAND FIFO Memory for Altera SoCs. 431c6882fb2SThor Thayer 432e8263793SThor Thayerconfig EDAC_ALTERA_DMA 433e8263793SThor Thayer bool "Altera DMA FIFO ECC" 434e8263793SThor Thayer depends on EDAC_ALTERA=y && PL330_DMA=y 435e8263793SThor Thayer help 436e8263793SThor Thayer Support for error detection and correction on the 437e8263793SThor Thayer Altera DMA FIFO Memory for Altera SoCs. 438e8263793SThor Thayer 439c609581dSThor Thayerconfig EDAC_ALTERA_USB 440c609581dSThor Thayer bool "Altera USB FIFO ECC" 441c609581dSThor Thayer depends on EDAC_ALTERA=y && USB_DWC2 442c609581dSThor Thayer help 443c609581dSThor Thayer Support for error detection and correction on the 444c609581dSThor Thayer Altera USB FIFO Memory for Altera SoCs. 445c609581dSThor Thayer 446485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI 447485fe9e2SThor Thayer bool "Altera QSPI FIFO ECC" 448485fe9e2SThor Thayer depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 449485fe9e2SThor Thayer help 450485fe9e2SThor Thayer Support for error detection and correction on the 451485fe9e2SThor Thayer Altera QSPI FIFO Memory for Altera SoCs. 452485fe9e2SThor Thayer 45391104984SThor Thayerconfig EDAC_ALTERA_SDMMC 45491104984SThor Thayer bool "Altera SDMMC FIFO ECC" 45591104984SThor Thayer depends on EDAC_ALTERA=y && MMC_DW 45691104984SThor Thayer help 45791104984SThor Thayer Support for error detection and correction on the 45891104984SThor Thayer Altera SDMMC FIFO Memory for Altera SoCs. 45991104984SThor Thayer 46091abaeaaSYash Shahconfig EDAC_SIFIVE 46191abaeaaSYash Shah bool "Sifive platform EDAC driver" 462ca120a79SGreentime Hu depends on EDAC=y && SIFIVE_CCACHE 46391abaeaaSYash Shah help 46491abaeaaSYash Shah Support for error detection and correction on the SiFive SoCs. 46591abaeaaSYash Shah 4667f6998a4SJan Luebbeconfig EDAC_ARMADA_XP 4677f6998a4SJan Luebbe bool "Marvell Armada XP DDR and L2 Cache ECC" 4687f6998a4SJan Luebbe depends on MACH_MVEBU_V7 4697f6998a4SJan Luebbe help 4707f6998a4SJan Luebbe Support for error correction and detection on the Marvell Aramada XP 4717f6998a4SJan Luebbe DDR RAM and L2 cache controllers. 4727f6998a4SJan Luebbe 473ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS 474ae9b56e3SPunnaiah Choudary Kalluri tristate "Synopsys DDR Memory Controller" 4755297ecfeSSherry Sun depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 476ae9b56e3SPunnaiah Choudary Kalluri help 477ae9b56e3SPunnaiah Choudary Kalluri Support for error detection and correction on the Synopsys DDR 478ae9b56e3SPunnaiah Choudary Kalluri memory controller. 479ae9b56e3SPunnaiah Choudary Kalluri 4800d442930SLoc Hoconfig EDAC_XGENE 4810d442930SLoc Ho tristate "APM X-Gene SoC" 482e3c4ff6dSBorislav Petkov depends on (ARM64 || COMPILE_TEST) 4830d442930SLoc Ho help 4840d442930SLoc Ho Support for error detection and correction on the 4850d442930SLoc Ho APM X-Gene family of SOCs. 4860d442930SLoc Ho 48786a18ee2STero Kristoconfig EDAC_TI 48886a18ee2STero Kristo tristate "Texas Instruments DDR3 ECC Controller" 48986a18ee2STero Kristo depends on ARCH_KEYSTONE || SOC_DRA7XX 49086a18ee2STero Kristo help 491a483e227SKrzysztof Kozlowski Support for error detection and correction on the TI SoCs. 49286a18ee2STero Kristo 49327450653SChannagoud Kadabiconfig EDAC_QCOM 49427450653SChannagoud Kadabi tristate "QCOM EDAC Controller" 49527450653SChannagoud Kadabi depends on ARCH_QCOM && QCOM_LLCC 49627450653SChannagoud Kadabi help 49727450653SChannagoud Kadabi Support for error detection and correction on the 49827450653SChannagoud Kadabi Qualcomm Technologies, Inc. SoCs. 49927450653SChannagoud Kadabi 50027450653SChannagoud Kadabi This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 50127450653SChannagoud Kadabi As of now, it supports error reporting for Last Level Cache Controller (LLCC) 50227450653SChannagoud Kadabi of Tag RAM and Data RAM. 50327450653SChannagoud Kadabi 50427450653SChannagoud Kadabi For debugging issues having to do with stability and overall system 50527450653SChannagoud Kadabi health, you should probably say 'Y' here. 50627450653SChannagoud Kadabi 5079b7e6242SStefan M Schaeckelerconfig EDAC_ASPEED 508edfc2d73STroy Lee tristate "Aspeed AST BMC SoC" 509edfc2d73STroy Lee depends on ARCH_ASPEED 5109b7e6242SStefan M Schaeckeler help 511edfc2d73STroy Lee Support for error detection and correction on the Aspeed AST BMC SoC. 5129b7e6242SStefan M Schaeckeler 5139b7e6242SStefan M Schaeckeler First, ECC must be configured in the bootloader. Then, this driver 5149b7e6242SStefan M Schaeckeler will expose error counters via the EDAC kernel framework. 5159b7e6242SStefan M Schaeckeler 51682413e56SShravan Kumar Ramaniconfig EDAC_BLUEFIELD 51782413e56SShravan Kumar Ramani tristate "Mellanox BlueField Memory ECC" 51882413e56SShravan Kumar Ramani depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 51982413e56SShravan Kumar Ramani help 52082413e56SShravan Kumar Ramani Support for error detection and correction on the 52182413e56SShravan Kumar Ramani Mellanox BlueField SoCs. 52282413e56SShravan Kumar Ramani 5231088750dSLei Wangconfig EDAC_DMC520 5241088750dSLei Wang tristate "ARM DMC-520 ECC" 5251088750dSLei Wang depends on ARM64 5261088750dSLei Wang help 5271088750dSLei Wang Support for error detection and correction on the 5281088750dSLei Wang SoCs with ARM DMC-520 DRAM controller. 5291088750dSLei Wang 5303bd2706cSSai Krishna Potthuriconfig EDAC_ZYNQMP 5313bd2706cSSai Krishna Potthuri tristate "Xilinx ZynqMP OCM Controller" 5323bd2706cSSai Krishna Potthuri depends on ARCH_ZYNQMP || COMPILE_TEST 5333bd2706cSSai Krishna Potthuri help 5343bd2706cSSai Krishna Potthuri This driver supports error detection and correction for the 5353bd2706cSSai Krishna Potthuri Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 5363bd2706cSSai Krishna Potthuri built as a module. In that case it will be called zynqmp_edac. 5373bd2706cSSai Krishna Potthuri 538d244c610SMarvin Linconfig EDAC_NPCM 539d244c610SMarvin Lin tristate "Nuvoton NPCM DDR Memory Controller" 540d244c610SMarvin Lin depends on (ARCH_NPCM || COMPILE_TEST) 541d244c610SMarvin Lin help 542d244c610SMarvin Lin Support for error detection and correction on the Nuvoton NPCM DDR 543d244c610SMarvin Lin memory controller. 544d244c610SMarvin Lin 545d244c610SMarvin Lin The memory controller supports single bit error correction, double bit 546d244c610SMarvin Lin error detection (in-line ECC in which a section 1/8th of the memory 547d244c610SMarvin Lin device used to store data is used for ECC storage). 548d244c610SMarvin Lin 5496f15b178SShubhrajyoti Dattaconfig EDAC_VERSAL 5506f15b178SShubhrajyoti Datta tristate "Xilinx Versal DDR Memory Controller" 5516f15b178SShubhrajyoti Datta depends on ARCH_ZYNQMP || COMPILE_TEST 5526f15b178SShubhrajyoti Datta help 5536f15b178SShubhrajyoti Datta Support for error detection and correction on the Xilinx Versal DDR 5546f15b178SShubhrajyoti Datta memory controller. 5556f15b178SShubhrajyoti Datta 5566f15b178SShubhrajyoti Datta Report both single bit errors (CE) and double bit errors (UE). 5576f15b178SShubhrajyoti Datta Support injecting both correctable and uncorrectable errors 5586f15b178SShubhrajyoti Datta for debugging purposes. 5596f15b178SShubhrajyoti Datta 560558aff7aSZhao Qunqinconfig EDAC_LOONGSON 561558aff7aSZhao Qunqin tristate "Loongson Memory Controller" 562558aff7aSZhao Qunqin depends on LOONGARCH && ACPI 563558aff7aSZhao Qunqin help 564558aff7aSZhao Qunqin Support for error detection and correction on the Loongson 565558aff7aSZhao Qunqin family memory controller. This driver reports single bit 566558aff7aSZhao Qunqin errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 567558aff7aSZhao Qunqin are compatible. 5686f15b178SShubhrajyoti Datta 569751cb5e5SJan Engelhardtendif # EDAC 570