1da9bb1d2SAlan Cox# 2da9bb1d2SAlan Cox# EDAC Kconfig 34577ca55SDoug Thompson# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4da9bb1d2SAlan Cox# Licensed and distributed under the GPL 5b01aec9bSBorislav Petkov 6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB 7b01aec9bSBorislav Petkov bool 8da9bb1d2SAlan Cox 954451663SBorislav Petkovconfig EDAC_SUPPORT 1054451663SBorislav Petkov bool 1154451663SBorislav Petkov 12751cb5e5SJan Engelhardtmenuconfig EDAC 13e3c4ff6dSBorislav Petkov tristate "EDAC (Error Detection And Correction) reporting" 14e3c4ff6dSBorislav Petkov depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15da9bb1d2SAlan Cox help 16a06b85ffSBorislav Petkov EDAC is a subsystem along with hardware-specific drivers designed to 17a06b85ffSBorislav Petkov report hardware errors. These are low-level errors that are reported 18a06b85ffSBorislav Petkov in the CPU or supporting chipset or other subsystems: 198cb2a398SDouglas Thompson memory errors, cache errors, PCI errors, thermal throttling, etc.. 208cb2a398SDouglas Thompson If unsure, select 'Y'. 21da9bb1d2SAlan Cox 22a06b85ffSBorislav Petkov The mailing list for the EDAC project is linux-edac@vger.kernel.org. 2357c432b5STim Small 24751cb5e5SJan Engelhardtif EDAC 25da9bb1d2SAlan Cox 2619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS 2719974710SMauro Carvalho Chehab bool "EDAC legacy sysfs" 2819974710SMauro Carvalho Chehab default y 2919974710SMauro Carvalho Chehab help 3019974710SMauro Carvalho Chehab Enable the compatibility sysfs nodes. 3119974710SMauro Carvalho Chehab Use 'Y' if your edac utilities aren't ported to work with the newer 3219974710SMauro Carvalho Chehab structures. 3319974710SMauro Carvalho Chehab 34da9bb1d2SAlan Coxconfig EDAC_DEBUG 35da9bb1d2SAlan Cox bool "Debugging" 361c5bf781SBorislav Petkov select DEBUG_FS 37da9bb1d2SAlan Cox help 3837929874SBorislav Petkov This turns on debugging information for the entire EDAC subsystem. 3937929874SBorislav Petkov You do so by inserting edac_module with "edac_debug_level=x." Valid 4037929874SBorislav Petkov levels are 0-4 (from low to high) and by default it is set to 2. 4137929874SBorislav Petkov Usually you should select 'N' here. 42da9bb1d2SAlan Cox 430d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE 440d18b2e3SBorislav Petkov tristate "Decode MCEs in human-readable form (only on AMD for now)" 45168eb34dSBorislav Petkov depends on CPU_SUP_AMD && X86_MCE_AMD 460d18b2e3SBorislav Petkov default y 47a7f7f624SMasahiro Yamada help 480d18b2e3SBorislav Petkov Enable this option if you want to decode Machine Check Exceptions 4925985edcSLucas De Marchi occurring on your machine in human-readable form. 500d18b2e3SBorislav Petkov 510d18b2e3SBorislav Petkov You should definitely say Y here in case you want to decode MCEs 520d18b2e3SBorislav Petkov which occur really early upon boot, before the module infrastructure 530d18b2e3SBorislav Petkov has been initialized. 540d18b2e3SBorislav Petkov 5577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES 56802e7f1dSJia He tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57802e7f1dSJia He depends on ACPI_APEI_GHES 58ed27b5dfSShuai Xue select UEFI_CPER 5977c5f5d2SMauro Carvalho Chehab help 6077c5f5d2SMauro Carvalho Chehab Not all machines support hardware-driven error report. Some of those 6177c5f5d2SMauro Carvalho Chehab provide a BIOS-driven error report mechanism via ACPI, using the 6277c5f5d2SMauro Carvalho Chehab APEI/GHES driver. By enabling this option, the error reports provided 6377c5f5d2SMauro Carvalho Chehab by GHES are sent to userspace via the EDAC API. 6477c5f5d2SMauro Carvalho Chehab 6577c5f5d2SMauro Carvalho Chehab When this option is enabled, it will disable the hardware-driven 6677c5f5d2SMauro Carvalho Chehab mechanisms, if a GHES BIOS is detected, entering into the 6777c5f5d2SMauro Carvalho Chehab "Firmware First" mode. 6877c5f5d2SMauro Carvalho Chehab 6977c5f5d2SMauro Carvalho Chehab It should be noticed that keeping both GHES and a hardware-driven 7077c5f5d2SMauro Carvalho Chehab error mechanism won't work well, as BIOS will race with OS, while 7177c5f5d2SMauro Carvalho Chehab reading the error registers. So, if you want to not use "Firmware 7277c5f5d2SMauro Carvalho Chehab first" GHES error mechanism, you should disable GHES either at 7377c5f5d2SMauro Carvalho Chehab compilation time or by passing "ghes.disable=1" Kernel parameter 7477c5f5d2SMauro Carvalho Chehab at boot time. 7577c5f5d2SMauro Carvalho Chehab 7677c5f5d2SMauro Carvalho Chehab In doubt, say 'Y'. 7777c5f5d2SMauro Carvalho Chehab 787d6034d3SDoug Thompsonconfig EDAC_AMD64 79f5b10c45STomasz Pala tristate "AMD64 (Opteron, Athlon64)" 80e3c4ff6dSBorislav Petkov depends on AMD_NB && EDAC_DECODE_MCE 81d6caeafaSMario Limonciello depends on AMD_NODE 826c9058f4SYazen Ghannam imply AMD_ATL 837d6034d3SDoug Thompson help 84027dbd6fSBorislav Petkov Support for error detection and correction of DRAM ECC errors on 85f5b10c45STomasz Pala the AMD64 families (>= K8) of memory controllers. 867d6034d3SDoug Thompson 8761810096SBorislav Petkov When EDAC_DEBUG is enabled, hardware error injection facilities 8861810096SBorislav Petkov through sysfs are available: 8961810096SBorislav Petkov 901865bc71SBorislav Petkov AMD CPUs up to and excluding family 0x17 provide for Memory 911865bc71SBorislav Petkov Error Injection into the ECC detection circuits. The amd64_edac 921865bc71SBorislav Petkov module allows the operator/user to inject Uncorrectable and 931865bc71SBorislav Petkov Correctable errors into DRAM. 947d6034d3SDoug Thompson 957d6034d3SDoug Thompson When enabled, in each of the respective memory controller directories 967d6034d3SDoug Thompson (/sys/devices/system/edac/mc/mcX), there are 3 input files: 977d6034d3SDoug Thompson 987d6034d3SDoug Thompson - inject_section (0..3, 16-byte section of 64-byte cacheline), 997d6034d3SDoug Thompson - inject_word (0..8, 16-bit word of 16-byte section), 1007d6034d3SDoug Thompson - inject_ecc_vector (hex ecc vector: select bits of inject word) 1017d6034d3SDoug Thompson 1027d6034d3SDoug Thompson In addition, there are two control files, inject_read and inject_write, 1037d6034d3SDoug Thompson which trigger the DRAM ECC Read and Write respectively. 104da9bb1d2SAlan Cox 105e23a7cdeSTalel Shenharconfig EDAC_AL_MC 106e23a7cdeSTalel Shenhar tristate "Amazon's Annapurna Lab Memory Controller" 107e23a7cdeSTalel Shenhar depends on (ARCH_ALPINE || COMPILE_TEST) 108e23a7cdeSTalel Shenhar help 109e23a7cdeSTalel Shenhar Support for error detection and correction for Amazon's Annapurna 110e23a7cdeSTalel Shenhar Labs Alpine chips which allow 1 bit correction and 2 bits detection. 111e23a7cdeSTalel Shenhar 112da9bb1d2SAlan Coxconfig EDAC_AMD76X 113da9bb1d2SAlan Cox tristate "AMD 76x (760, 762, 768)" 114e3c4ff6dSBorislav Petkov depends on PCI && X86_32 115da9bb1d2SAlan Cox help 116da9bb1d2SAlan Cox Support for error detection and correction on the AMD 76x 117da9bb1d2SAlan Cox series of chipsets used with the Athlon processor. 118da9bb1d2SAlan Cox 119da9bb1d2SAlan Coxconfig EDAC_E7XXX 120da9bb1d2SAlan Cox tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 121e3c4ff6dSBorislav Petkov depends on PCI && X86_32 122da9bb1d2SAlan Cox help 123da9bb1d2SAlan Cox Support for error detection and correction on the Intel 124da9bb1d2SAlan Cox E7205, E7500, E7501 and E7505 server chipsets. 125da9bb1d2SAlan Cox 126da9bb1d2SAlan Coxconfig EDAC_E752X 1275135b797SAndrei Konovalov tristate "Intel e752x (e7520, e7525, e7320) and 3100" 128e3c4ff6dSBorislav Petkov depends on PCI && X86 129da9bb1d2SAlan Cox help 130da9bb1d2SAlan Cox Support for error detection and correction on the Intel 131da9bb1d2SAlan Cox E7520, E7525, E7320 server chipsets. 132da9bb1d2SAlan Cox 1335a2c675cSTim Smallconfig EDAC_I82443BXGX 1345a2c675cSTim Small tristate "Intel 82443BX/GX (440BX/GX)" 135e3c4ff6dSBorislav Petkov depends on PCI && X86_32 13628f96eeaSAndrew Morton depends on BROKEN 1375a2c675cSTim Small help 1385a2c675cSTim Small Support for error detection and correction on the Intel 1395a2c675cSTim Small 82443BX/GX memory controllers (440BX/GX chipsets). 1405a2c675cSTim Small 141da9bb1d2SAlan Coxconfig EDAC_I82875P 142da9bb1d2SAlan Cox tristate "Intel 82875p (D82875P, E7210)" 143e3c4ff6dSBorislav Petkov depends on PCI && X86_32 144da9bb1d2SAlan Cox help 145da9bb1d2SAlan Cox Support for error detection and correction on the Intel 146da9bb1d2SAlan Cox DP82785P and E7210 server chipsets. 147da9bb1d2SAlan Cox 148420390f0SRanganathan Desikanconfig EDAC_I82975X 149420390f0SRanganathan Desikan tristate "Intel 82975x (D82975x)" 150e3c4ff6dSBorislav Petkov depends on PCI && X86 151420390f0SRanganathan Desikan help 152420390f0SRanganathan Desikan Support for error detection and correction on the Intel 153420390f0SRanganathan Desikan DP82975x server chipsets. 154420390f0SRanganathan Desikan 155535c6a53SJason Uhlenkottconfig EDAC_I3000 156535c6a53SJason Uhlenkott tristate "Intel 3000/3010" 157e3c4ff6dSBorislav Petkov depends on PCI && X86 158535c6a53SJason Uhlenkott help 159535c6a53SJason Uhlenkott Support for error detection and correction on the Intel 160535c6a53SJason Uhlenkott 3000 and 3010 server chipsets. 161535c6a53SJason Uhlenkott 162dd8ef1dbSJason Uhlenkottconfig EDAC_I3200 163dd8ef1dbSJason Uhlenkott tristate "Intel 3200" 164e3c4ff6dSBorislav Petkov depends on PCI && X86 165dd8ef1dbSJason Uhlenkott help 166dd8ef1dbSJason Uhlenkott Support for error detection and correction on the Intel 167dd8ef1dbSJason Uhlenkott 3200 and 3210 server chipsets. 168dd8ef1dbSJason Uhlenkott 1697ee40b89SJason Baronconfig EDAC_IE31200 1707ee40b89SJason Baron tristate "Intel e312xx" 171*a5db1b29SQiuxu Zhuo depends on PCI && X86 && X86_MCE_INTEL 1727ee40b89SJason Baron help 1737ee40b89SJason Baron Support for error detection and correction on the Intel 1747ee40b89SJason Baron E3-1200 based DRAM controllers. 1757ee40b89SJason Baron 176df8bc08cSHitoshi Mitakeconfig EDAC_X38 177df8bc08cSHitoshi Mitake tristate "Intel X38" 178e3c4ff6dSBorislav Petkov depends on PCI && X86 179df8bc08cSHitoshi Mitake help 180df8bc08cSHitoshi Mitake Support for error detection and correction on the Intel 181df8bc08cSHitoshi Mitake X38 server chipsets. 182df8bc08cSHitoshi Mitake 183920c8df6SMauro Carvalho Chehabconfig EDAC_I5400 184920c8df6SMauro Carvalho Chehab tristate "Intel 5400 (Seaburg) chipsets" 185e3c4ff6dSBorislav Petkov depends on PCI && X86 186920c8df6SMauro Carvalho Chehab help 187920c8df6SMauro Carvalho Chehab Support for error detection and correction the Intel 188920c8df6SMauro Carvalho Chehab i5400 MCH chipset (Seaburg). 189920c8df6SMauro Carvalho Chehab 190a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE 191a0c36a1fSMauro Carvalho Chehab tristate "Intel i7 Core (Nehalem) processors" 192e3c4ff6dSBorislav Petkov depends on PCI && X86 && X86_MCE_INTEL 193a0c36a1fSMauro Carvalho Chehab help 194a0c36a1fSMauro Carvalho Chehab Support for error detection and correction the Intel 195696e409dSMauro Carvalho Chehab i7 Core (Nehalem) Integrated Memory Controller that exists on 196696e409dSMauro Carvalho Chehab newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 197696e409dSMauro Carvalho Chehab and Xeon 55xx processors. 198a0c36a1fSMauro Carvalho Chehab 199da9bb1d2SAlan Coxconfig EDAC_I82860 200da9bb1d2SAlan Cox tristate "Intel 82860" 201e3c4ff6dSBorislav Petkov depends on PCI && X86_32 202da9bb1d2SAlan Cox help 203da9bb1d2SAlan Cox Support for error detection and correction on the Intel 204da9bb1d2SAlan Cox 82860 chipset. 205da9bb1d2SAlan Cox 206da9bb1d2SAlan Coxconfig EDAC_R82600 207da9bb1d2SAlan Cox tristate "Radisys 82600 embedded chipset" 208e3c4ff6dSBorislav Petkov depends on PCI && X86_32 209da9bb1d2SAlan Cox help 210da9bb1d2SAlan Cox Support for error detection and correction on the Radisys 211da9bb1d2SAlan Cox 82600 embedded chipset. 212da9bb1d2SAlan Cox 213eb60705aSEric Wollesenconfig EDAC_I5000 214eb60705aSEric Wollesen tristate "Intel Greencreek/Blackford chipset" 215e3c4ff6dSBorislav Petkov depends on X86 && PCI 21675564191SAristeu Rozanski depends on BROKEN 217eb60705aSEric Wollesen help 218eb60705aSEric Wollesen Support for error detection and correction the Intel 219eb60705aSEric Wollesen Greekcreek/Blackford chipsets. 220eb60705aSEric Wollesen 2218f421c59SArthur Jonesconfig EDAC_I5100 2228f421c59SArthur Jones tristate "Intel San Clemente MCH" 223e3c4ff6dSBorislav Petkov depends on X86 && PCI 2248f421c59SArthur Jones help 2258f421c59SArthur Jones Support for error detection and correction the Intel 2268f421c59SArthur Jones San Clemente MCH. 2278f421c59SArthur Jones 228fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300 229fcaf780bSMauro Carvalho Chehab tristate "Intel Clarksboro MCH" 230e3c4ff6dSBorislav Petkov depends on X86 && PCI 231fcaf780bSMauro Carvalho Chehab help 232fcaf780bSMauro Carvalho Chehab Support for error detection and correction the Intel 233fcaf780bSMauro Carvalho Chehab Clarksboro MCH (Intel 7300 chipset). 234fcaf780bSMauro Carvalho Chehab 2353d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE 23650d1bb93SAristeu Rozanski tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 237e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2383d78c9afSMauro Carvalho Chehab help 2393d78c9afSMauro Carvalho Chehab Support for error detection and correction the Intel 24050d1bb93SAristeu Rozanski Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2413d78c9afSMauro Carvalho Chehab 2424ec656bdSTony Luckconfig EDAC_SKX 2434ec656bdSTony Luck tristate "Intel Skylake server Integrated MC" 24424c9d423SLuck, Tony depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 245de245ae0SRandy Dunlap depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 24658ca9ac1STony Luck select DMI 24724c9d423SLuck, Tony select ACPI_ADXL 2484ec656bdSTony Luck help 2494ec656bdSTony Luck Support for error detection and correction the Intel 25058ca9ac1STony Luck Skylake server Integrated Memory Controllers. If your 25158ca9ac1STony Luck system has non-volatile DIMMs you should also manually 25258ca9ac1STony Luck select CONFIG_ACPI_NFIT. 2534ec656bdSTony Luck 254d4dc89d0SQiuxu Zhuoconfig EDAC_I10NM 255d4dc89d0SQiuxu Zhuo tristate "Intel 10nm server Integrated MC" 256d6a9f733STony Luck depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 257d4dc89d0SQiuxu Zhuo depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 258d4dc89d0SQiuxu Zhuo select DMI 259d6a9f733STony Luck select ACPI_ADXL 260d4dc89d0SQiuxu Zhuo help 261d4dc89d0SQiuxu Zhuo Support for error detection and correction the Intel 262d4dc89d0SQiuxu Zhuo 10nm server Integrated Memory Controllers. If your 263d4dc89d0SQiuxu Zhuo system has non-volatile DIMMs you should also manually 264d4dc89d0SQiuxu Zhuo select CONFIG_ACPI_NFIT. 265d4dc89d0SQiuxu Zhuo 2665c71ad17STony Luckconfig EDAC_PND2 2675c71ad17STony Luck tristate "Intel Pondicherry2" 268e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL 2697b2db704SAndy Shevchenko select P2SB if X86 2705c71ad17STony Luck help 2715c71ad17STony Luck Support for error detection and correction on the Intel 2725c71ad17STony Luck Pondicherry2 Integrated Memory Controller. This SoC IP is 2735c71ad17STony Luck first used on the Apollo Lake platform and Denverton 2745c71ad17STony Luck micro-server but may appear on others in the future. 2755c71ad17STony Luck 27610590a9dSQiuxu Zhuoconfig EDAC_IGEN6 27710590a9dSQiuxu Zhuo tristate "Intel client SoC Integrated MC" 2780a9ece9bSRandy Dunlap depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 279a1c9ca5fSRandy Dunlap depends on X86_64 && X86_MCE_INTEL 28010590a9dSQiuxu Zhuo help 28110590a9dSQiuxu Zhuo Support for error detection and correction on the Intel 28210590a9dSQiuxu Zhuo client SoC Integrated Memory Controller using In-Band ECC IP. 28310590a9dSQiuxu Zhuo This In-Band ECC is first used on the Elkhart Lake SoC but 28410590a9dSQiuxu Zhuo may appear on others in the future. 28510590a9dSQiuxu Zhuo 286a9a753d5SDave Jiangconfig EDAC_MPC85XX 2872b8358a9SMichael Ellerman bool "Freescale MPC83xx / MPC85xx" 2882b8358a9SMichael Ellerman depends on FSL_SOC && EDAC=y 289a9a753d5SDave Jiang help 290a9a753d5SDave Jiang Support for error detection and correction on the Freescale 29174210267SYork Sun MPC8349, MPC8560, MPC8540, MPC8548, T4240 292a9a753d5SDave Jiang 293eeb3d68bSYork Sunconfig EDAC_LAYERSCAPE 294eeb3d68bSYork Sun tristate "Freescale Layerscape DDR" 29528dd6726SRasmus Villemoes depends on ARCH_LAYERSCAPE || SOC_LS1021A 296eeb3d68bSYork Sun help 297eeb3d68bSYork Sun Support for error detection and correction on Freescale memory 298eeb3d68bSYork Sun controllers on Layerscape SoCs. 299eeb3d68bSYork Sun 3007d8536fbSEgor Martovetskyconfig EDAC_PASEMI 3017d8536fbSEgor Martovetsky tristate "PA Semi PWRficient" 302e3c4ff6dSBorislav Petkov depends on PPC_PASEMI && PCI 3037d8536fbSEgor Martovetsky help 3047d8536fbSEgor Martovetsky Support for error detection and correction on PA Semi 3057d8536fbSEgor Martovetsky PWRficient. 3067d8536fbSEgor Martovetsky 3072a9036afSHarry Ciaoconfig EDAC_CPC925 3082a9036afSHarry Ciao tristate "IBM CPC925 Memory Controller (PPC970FX)" 309e3c4ff6dSBorislav Petkov depends on PPC64 3102a9036afSHarry Ciao help 3112a9036afSHarry Ciao Support for error detection and correction on the 3122a9036afSHarry Ciao IBM CPC925 Bridge and Memory Controller, which is 3132a9036afSHarry Ciao a companion chip to the PowerPC 970 family of 3142a9036afSHarry Ciao processors. 3152a9036afSHarry Ciao 316a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC 317a1b01edbSRob Herring tristate "Highbank Memory Controller" 318e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 319a1b01edbSRob Herring help 320a1b01edbSRob Herring Support for error detection and correction on the 321a1b01edbSRob Herring Calxeda Highbank memory controller. 322a1b01edbSRob Herring 32369154d06SRob Herringconfig EDAC_HIGHBANK_L2 32469154d06SRob Herring tristate "Highbank L2 Cache" 325e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 32669154d06SRob Herring help 32769154d06SRob Herring Support for error detection and correction on the 32869154d06SRob Herring Calxeda Highbank memory controller. 32969154d06SRob Herring 330f65aad41SRalf Baechleconfig EDAC_OCTEON_PC 331f65aad41SRalf Baechle tristate "Cavium Octeon Primary Caches" 332e3c4ff6dSBorislav Petkov depends on CPU_CAVIUM_OCTEON 333f65aad41SRalf Baechle help 334f65aad41SRalf Baechle Support for error detection and correction on the primary caches of 335f65aad41SRalf Baechle the cnMIPS cores of Cavium Octeon family SOCs. 336f65aad41SRalf Baechle 337f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C 338f65aad41SRalf Baechle tristate "Cavium Octeon Secondary Caches (L2C)" 339e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 340f65aad41SRalf Baechle help 341f65aad41SRalf Baechle Support for error detection and correction on the 342f65aad41SRalf Baechle Cavium Octeon family of SOCs. 343f65aad41SRalf Baechle 344f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC 345f65aad41SRalf Baechle tristate "Cavium Octeon DRAM Memory Controller (LMC)" 346e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 347f65aad41SRalf Baechle help 348f65aad41SRalf Baechle Support for error detection and correction on the 349f65aad41SRalf Baechle Cavium Octeon family of SOCs. 350f65aad41SRalf Baechle 351f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI 352f65aad41SRalf Baechle tristate "Cavium Octeon PCI Controller" 353e3c4ff6dSBorislav Petkov depends on PCI && CAVIUM_OCTEON_SOC 354f65aad41SRalf Baechle help 355f65aad41SRalf Baechle Support for error detection and correction on the 356f65aad41SRalf Baechle Cavium Octeon family of SOCs. 357f65aad41SRalf Baechle 35841003396SSergey Temerkhanovconfig EDAC_THUNDERX 35941003396SSergey Temerkhanov tristate "Cavium ThunderX EDAC" 36041003396SSergey Temerkhanov depends on ARM64 36141003396SSergey Temerkhanov depends on PCI 36241003396SSergey Temerkhanov help 36341003396SSergey Temerkhanov Support for error detection and correction on the 36441003396SSergey Temerkhanov Cavium ThunderX memory controllers (LMC), Cache 36541003396SSergey Temerkhanov Coherent Processor Interconnect (CCPI) and L2 cache 36641003396SSergey Temerkhanov blocks (TAD, CBC, MCI). 36741003396SSergey Temerkhanov 368c3eea194SThor Thayerconfig EDAC_ALTERA 369c3eea194SThor Thayer bool "Altera SOCFPGA ECC" 370098da961SKrzysztof Kozlowski depends on EDAC=y && ARCH_INTEL_SOCFPGA 37171bcada8SThor Thayer help 37271bcada8SThor Thayer Support for error detection and correction on the 373580b5cf5SThor Thayer Altera SOCs. This is the global enable for the 374580b5cf5SThor Thayer various Altera peripherals. 375580b5cf5SThor Thayer 376580b5cf5SThor Thayerconfig EDAC_ALTERA_SDRAM 377580b5cf5SThor Thayer bool "Altera SDRAM ECC" 378580b5cf5SThor Thayer depends on EDAC_ALTERA=y 379580b5cf5SThor Thayer help 380580b5cf5SThor Thayer Support for error detection and correction on the 381580b5cf5SThor Thayer Altera SDRAM Memory for Altera SoCs. Note that the 382580b5cf5SThor Thayer preloader must initialize the SDRAM before loading 383580b5cf5SThor Thayer the kernel. 384c3eea194SThor Thayer 385c3eea194SThor Thayerconfig EDAC_ALTERA_L2C 386c3eea194SThor Thayer bool "Altera L2 Cache ECC" 3873a8f21f1SThor Thayer depends on EDAC_ALTERA=y && CACHE_L2X0 388c3eea194SThor Thayer help 389c3eea194SThor Thayer Support for error detection and correction on the 390c3eea194SThor Thayer Altera L2 cache Memory for Altera SoCs. This option 3913a8f21f1SThor Thayer requires L2 cache. 392c3eea194SThor Thayer 393c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM 394c3eea194SThor Thayer bool "Altera On-Chip RAM ECC" 395c3eea194SThor Thayer depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 396c3eea194SThor Thayer help 397c3eea194SThor Thayer Support for error detection and correction on the 398c3eea194SThor Thayer Altera On-Chip RAM Memory for Altera SoCs. 39971bcada8SThor Thayer 400ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET 401ab8c1e0fSThor Thayer bool "Altera Ethernet FIFO ECC" 402ab8c1e0fSThor Thayer depends on EDAC_ALTERA=y 403ab8c1e0fSThor Thayer help 404ab8c1e0fSThor Thayer Support for error detection and correction on the 405ab8c1e0fSThor Thayer Altera Ethernet FIFO Memory for Altera SoCs. 406ab8c1e0fSThor Thayer 407c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND 408c6882fb2SThor Thayer bool "Altera NAND FIFO ECC" 409c6882fb2SThor Thayer depends on EDAC_ALTERA=y && MTD_NAND_DENALI 410c6882fb2SThor Thayer help 411c6882fb2SThor Thayer Support for error detection and correction on the 412c6882fb2SThor Thayer Altera NAND FIFO Memory for Altera SoCs. 413c6882fb2SThor Thayer 414e8263793SThor Thayerconfig EDAC_ALTERA_DMA 415e8263793SThor Thayer bool "Altera DMA FIFO ECC" 416e8263793SThor Thayer depends on EDAC_ALTERA=y && PL330_DMA=y 417e8263793SThor Thayer help 418e8263793SThor Thayer Support for error detection and correction on the 419e8263793SThor Thayer Altera DMA FIFO Memory for Altera SoCs. 420e8263793SThor Thayer 421c609581dSThor Thayerconfig EDAC_ALTERA_USB 422c609581dSThor Thayer bool "Altera USB FIFO ECC" 423c609581dSThor Thayer depends on EDAC_ALTERA=y && USB_DWC2 424c609581dSThor Thayer help 425c609581dSThor Thayer Support for error detection and correction on the 426c609581dSThor Thayer Altera USB FIFO Memory for Altera SoCs. 427c609581dSThor Thayer 428485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI 429485fe9e2SThor Thayer bool "Altera QSPI FIFO ECC" 430485fe9e2SThor Thayer depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 431485fe9e2SThor Thayer help 432485fe9e2SThor Thayer Support for error detection and correction on the 433485fe9e2SThor Thayer Altera QSPI FIFO Memory for Altera SoCs. 434485fe9e2SThor Thayer 43591104984SThor Thayerconfig EDAC_ALTERA_SDMMC 43691104984SThor Thayer bool "Altera SDMMC FIFO ECC" 43791104984SThor Thayer depends on EDAC_ALTERA=y && MMC_DW 43891104984SThor Thayer help 43991104984SThor Thayer Support for error detection and correction on the 44091104984SThor Thayer Altera SDMMC FIFO Memory for Altera SoCs. 44191104984SThor Thayer 44291abaeaaSYash Shahconfig EDAC_SIFIVE 44391abaeaaSYash Shah bool "Sifive platform EDAC driver" 444ca120a79SGreentime Hu depends on EDAC=y && SIFIVE_CCACHE 44591abaeaaSYash Shah help 44691abaeaaSYash Shah Support for error detection and correction on the SiFive SoCs. 44791abaeaaSYash Shah 4487f6998a4SJan Luebbeconfig EDAC_ARMADA_XP 4497f6998a4SJan Luebbe bool "Marvell Armada XP DDR and L2 Cache ECC" 4507f6998a4SJan Luebbe depends on MACH_MVEBU_V7 4517f6998a4SJan Luebbe help 4527f6998a4SJan Luebbe Support for error correction and detection on the Marvell Aramada XP 4537f6998a4SJan Luebbe DDR RAM and L2 cache controllers. 4547f6998a4SJan Luebbe 455ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS 456ae9b56e3SPunnaiah Choudary Kalluri tristate "Synopsys DDR Memory Controller" 4575297ecfeSSherry Sun depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 458ae9b56e3SPunnaiah Choudary Kalluri help 459ae9b56e3SPunnaiah Choudary Kalluri Support for error detection and correction on the Synopsys DDR 460ae9b56e3SPunnaiah Choudary Kalluri memory controller. 461ae9b56e3SPunnaiah Choudary Kalluri 4620d442930SLoc Hoconfig EDAC_XGENE 4630d442930SLoc Ho tristate "APM X-Gene SoC" 464e3c4ff6dSBorislav Petkov depends on (ARM64 || COMPILE_TEST) 4650d442930SLoc Ho help 4660d442930SLoc Ho Support for error detection and correction on the 4670d442930SLoc Ho APM X-Gene family of SOCs. 4680d442930SLoc Ho 46986a18ee2STero Kristoconfig EDAC_TI 47086a18ee2STero Kristo tristate "Texas Instruments DDR3 ECC Controller" 47186a18ee2STero Kristo depends on ARCH_KEYSTONE || SOC_DRA7XX 47286a18ee2STero Kristo help 473a483e227SKrzysztof Kozlowski Support for error detection and correction on the TI SoCs. 47486a18ee2STero Kristo 47527450653SChannagoud Kadabiconfig EDAC_QCOM 47627450653SChannagoud Kadabi tristate "QCOM EDAC Controller" 47727450653SChannagoud Kadabi depends on ARCH_QCOM && QCOM_LLCC 47827450653SChannagoud Kadabi help 47927450653SChannagoud Kadabi Support for error detection and correction on the 48027450653SChannagoud Kadabi Qualcomm Technologies, Inc. SoCs. 48127450653SChannagoud Kadabi 48227450653SChannagoud Kadabi This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 48327450653SChannagoud Kadabi As of now, it supports error reporting for Last Level Cache Controller (LLCC) 48427450653SChannagoud Kadabi of Tag RAM and Data RAM. 48527450653SChannagoud Kadabi 48627450653SChannagoud Kadabi For debugging issues having to do with stability and overall system 48727450653SChannagoud Kadabi health, you should probably say 'Y' here. 48827450653SChannagoud Kadabi 4899b7e6242SStefan M Schaeckelerconfig EDAC_ASPEED 490edfc2d73STroy Lee tristate "Aspeed AST BMC SoC" 491edfc2d73STroy Lee depends on ARCH_ASPEED 4929b7e6242SStefan M Schaeckeler help 493edfc2d73STroy Lee Support for error detection and correction on the Aspeed AST BMC SoC. 4949b7e6242SStefan M Schaeckeler 4959b7e6242SStefan M Schaeckeler First, ECC must be configured in the bootloader. Then, this driver 4969b7e6242SStefan M Schaeckeler will expose error counters via the EDAC kernel framework. 4979b7e6242SStefan M Schaeckeler 49882413e56SShravan Kumar Ramaniconfig EDAC_BLUEFIELD 49982413e56SShravan Kumar Ramani tristate "Mellanox BlueField Memory ECC" 50082413e56SShravan Kumar Ramani depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 50182413e56SShravan Kumar Ramani help 50282413e56SShravan Kumar Ramani Support for error detection and correction on the 50382413e56SShravan Kumar Ramani Mellanox BlueField SoCs. 50482413e56SShravan Kumar Ramani 5051088750dSLei Wangconfig EDAC_DMC520 5061088750dSLei Wang tristate "ARM DMC-520 ECC" 5071088750dSLei Wang depends on ARM64 5081088750dSLei Wang help 5091088750dSLei Wang Support for error detection and correction on the 5101088750dSLei Wang SoCs with ARM DMC-520 DRAM controller. 5111088750dSLei Wang 5123bd2706cSSai Krishna Potthuriconfig EDAC_ZYNQMP 5133bd2706cSSai Krishna Potthuri tristate "Xilinx ZynqMP OCM Controller" 5143bd2706cSSai Krishna Potthuri depends on ARCH_ZYNQMP || COMPILE_TEST 5153bd2706cSSai Krishna Potthuri help 5163bd2706cSSai Krishna Potthuri This driver supports error detection and correction for the 5173bd2706cSSai Krishna Potthuri Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 5183bd2706cSSai Krishna Potthuri built as a module. In that case it will be called zynqmp_edac. 5193bd2706cSSai Krishna Potthuri 520d244c610SMarvin Linconfig EDAC_NPCM 521d244c610SMarvin Lin tristate "Nuvoton NPCM DDR Memory Controller" 522d244c610SMarvin Lin depends on (ARCH_NPCM || COMPILE_TEST) 523d244c610SMarvin Lin help 524d244c610SMarvin Lin Support for error detection and correction on the Nuvoton NPCM DDR 525d244c610SMarvin Lin memory controller. 526d244c610SMarvin Lin 527d244c610SMarvin Lin The memory controller supports single bit error correction, double bit 528d244c610SMarvin Lin error detection (in-line ECC in which a section 1/8th of the memory 529d244c610SMarvin Lin device used to store data is used for ECC storage). 530d244c610SMarvin Lin 5316f15b178SShubhrajyoti Dattaconfig EDAC_VERSAL 5326f15b178SShubhrajyoti Datta tristate "Xilinx Versal DDR Memory Controller" 5336f15b178SShubhrajyoti Datta depends on ARCH_ZYNQMP || COMPILE_TEST 5346f15b178SShubhrajyoti Datta help 5356f15b178SShubhrajyoti Datta Support for error detection and correction on the Xilinx Versal DDR 5366f15b178SShubhrajyoti Datta memory controller. 5376f15b178SShubhrajyoti Datta 5386f15b178SShubhrajyoti Datta Report both single bit errors (CE) and double bit errors (UE). 5396f15b178SShubhrajyoti Datta Support injecting both correctable and uncorrectable errors 5406f15b178SShubhrajyoti Datta for debugging purposes. 5416f15b178SShubhrajyoti Datta 542558aff7aSZhao Qunqinconfig EDAC_LOONGSON 543558aff7aSZhao Qunqin tristate "Loongson Memory Controller" 544558aff7aSZhao Qunqin depends on LOONGARCH && ACPI 545558aff7aSZhao Qunqin help 546558aff7aSZhao Qunqin Support for error detection and correction on the Loongson 547558aff7aSZhao Qunqin family memory controller. This driver reports single bit 548558aff7aSZhao Qunqin errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 549558aff7aSZhao Qunqin are compatible. 5506f15b178SShubhrajyoti Datta 551751cb5e5SJan Engelhardtendif # EDAC 552