1da9bb1d2SAlan Cox# 2da9bb1d2SAlan Cox# EDAC Kconfig 34577ca55SDoug Thompson# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4da9bb1d2SAlan Cox# Licensed and distributed under the GPL 5b01aec9bSBorislav Petkov 6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB 7b01aec9bSBorislav Petkov bool 8da9bb1d2SAlan Cox 954451663SBorislav Petkovconfig EDAC_SUPPORT 1054451663SBorislav Petkov bool 1154451663SBorislav Petkov 12751cb5e5SJan Engelhardtmenuconfig EDAC 13e24aca67SGeunSik Lim bool "EDAC (Error Detection And Correction) reporting" 14b01aec9bSBorislav Petkov depends on HAS_IOMEM && EDAC_SUPPORT 15da9bb1d2SAlan Cox help 16da9bb1d2SAlan Cox EDAC is designed to report errors in the core system. 17da9bb1d2SAlan Cox These are low-level errors that are reported in the CPU or 188cb2a398SDouglas Thompson supporting chipset or other subsystems: 198cb2a398SDouglas Thompson memory errors, cache errors, PCI errors, thermal throttling, etc.. 208cb2a398SDouglas Thompson If unsure, select 'Y'. 21da9bb1d2SAlan Cox 2257c432b5STim Small If this code is reporting problems on your system, please 2357c432b5STim Small see the EDAC project web pages for more information at: 2457c432b5STim Small 2557c432b5STim Small <http://bluesmoke.sourceforge.net/> 2657c432b5STim Small 2757c432b5STim Small and: 2857c432b5STim Small 2957c432b5STim Small <http://buttersideup.com/edacwiki> 3057c432b5STim Small 3157c432b5STim Small There is also a mailing list for the EDAC project, which can 3257c432b5STim Small be found via the sourceforge page. 3357c432b5STim Small 34751cb5e5SJan Engelhardtif EDAC 35da9bb1d2SAlan Cox 3619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS 3719974710SMauro Carvalho Chehab bool "EDAC legacy sysfs" 3819974710SMauro Carvalho Chehab default y 3919974710SMauro Carvalho Chehab help 4019974710SMauro Carvalho Chehab Enable the compatibility sysfs nodes. 4119974710SMauro Carvalho Chehab Use 'Y' if your edac utilities aren't ported to work with the newer 4219974710SMauro Carvalho Chehab structures. 4319974710SMauro Carvalho Chehab 44da9bb1d2SAlan Coxconfig EDAC_DEBUG 45da9bb1d2SAlan Cox bool "Debugging" 46da9bb1d2SAlan Cox help 4737929874SBorislav Petkov This turns on debugging information for the entire EDAC subsystem. 4837929874SBorislav Petkov You do so by inserting edac_module with "edac_debug_level=x." Valid 4937929874SBorislav Petkov levels are 0-4 (from low to high) and by default it is set to 2. 5037929874SBorislav Petkov Usually you should select 'N' here. 51da9bb1d2SAlan Cox 520d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE 530d18b2e3SBorislav Petkov tristate "Decode MCEs in human-readable form (only on AMD for now)" 54168eb34dSBorislav Petkov depends on CPU_SUP_AMD && X86_MCE_AMD 550d18b2e3SBorislav Petkov default y 560d18b2e3SBorislav Petkov ---help--- 570d18b2e3SBorislav Petkov Enable this option if you want to decode Machine Check Exceptions 5825985edcSLucas De Marchi occurring on your machine in human-readable form. 590d18b2e3SBorislav Petkov 600d18b2e3SBorislav Petkov You should definitely say Y here in case you want to decode MCEs 610d18b2e3SBorislav Petkov which occur really early upon boot, before the module infrastructure 620d18b2e3SBorislav Petkov has been initialized. 630d18b2e3SBorislav Petkov 64da9bb1d2SAlan Coxconfig EDAC_MM_EDAC 65da9bb1d2SAlan Cox tristate "Main Memory EDAC (Error Detection And Correction) reporting" 6676ac8275SChen, Gong select RAS 67da9bb1d2SAlan Cox help 68da9bb1d2SAlan Cox Some systems are able to detect and correct errors in main 69da9bb1d2SAlan Cox memory. EDAC can report statistics on memory error 70da9bb1d2SAlan Cox detection and correction (EDAC - or commonly referred to ECC 71da9bb1d2SAlan Cox errors). EDAC will also try to decode where these errors 72da9bb1d2SAlan Cox occurred so that a particular failing memory module can be 73da9bb1d2SAlan Cox replaced. If unsure, select 'Y'. 74da9bb1d2SAlan Cox 7577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES 7677c5f5d2SMauro Carvalho Chehab bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 7777c5f5d2SMauro Carvalho Chehab depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y) 7877c5f5d2SMauro Carvalho Chehab default y 7977c5f5d2SMauro Carvalho Chehab help 8077c5f5d2SMauro Carvalho Chehab Not all machines support hardware-driven error report. Some of those 8177c5f5d2SMauro Carvalho Chehab provide a BIOS-driven error report mechanism via ACPI, using the 8277c5f5d2SMauro Carvalho Chehab APEI/GHES driver. By enabling this option, the error reports provided 8377c5f5d2SMauro Carvalho Chehab by GHES are sent to userspace via the EDAC API. 8477c5f5d2SMauro Carvalho Chehab 8577c5f5d2SMauro Carvalho Chehab When this option is enabled, it will disable the hardware-driven 8677c5f5d2SMauro Carvalho Chehab mechanisms, if a GHES BIOS is detected, entering into the 8777c5f5d2SMauro Carvalho Chehab "Firmware First" mode. 8877c5f5d2SMauro Carvalho Chehab 8977c5f5d2SMauro Carvalho Chehab It should be noticed that keeping both GHES and a hardware-driven 9077c5f5d2SMauro Carvalho Chehab error mechanism won't work well, as BIOS will race with OS, while 9177c5f5d2SMauro Carvalho Chehab reading the error registers. So, if you want to not use "Firmware 9277c5f5d2SMauro Carvalho Chehab first" GHES error mechanism, you should disable GHES either at 9377c5f5d2SMauro Carvalho Chehab compilation time or by passing "ghes.disable=1" Kernel parameter 9477c5f5d2SMauro Carvalho Chehab at boot time. 9577c5f5d2SMauro Carvalho Chehab 9677c5f5d2SMauro Carvalho Chehab In doubt, say 'Y'. 9777c5f5d2SMauro Carvalho Chehab 987d6034d3SDoug Thompsonconfig EDAC_AMD64 99f5b10c45STomasz Pala tristate "AMD64 (Opteron, Athlon64)" 100f5b10c45STomasz Pala depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE 1017d6034d3SDoug Thompson help 102027dbd6fSBorislav Petkov Support for error detection and correction of DRAM ECC errors on 103f5b10c45STomasz Pala the AMD64 families (>= K8) of memory controllers. 1047d6034d3SDoug Thompson 1057d6034d3SDoug Thompsonconfig EDAC_AMD64_ERROR_INJECTION 1069cdeb404SBorislav Petkov bool "Sysfs HW Error injection facilities" 1077d6034d3SDoug Thompson depends on EDAC_AMD64 1087d6034d3SDoug Thompson help 1097d6034d3SDoug Thompson Recent Opterons (Family 10h and later) provide for Memory Error 1107d6034d3SDoug Thompson Injection into the ECC detection circuits. The amd64_edac module 1117d6034d3SDoug Thompson allows the operator/user to inject Uncorrectable and Correctable 1127d6034d3SDoug Thompson errors into DRAM. 1137d6034d3SDoug Thompson 1147d6034d3SDoug Thompson When enabled, in each of the respective memory controller directories 1157d6034d3SDoug Thompson (/sys/devices/system/edac/mc/mcX), there are 3 input files: 1167d6034d3SDoug Thompson 1177d6034d3SDoug Thompson - inject_section (0..3, 16-byte section of 64-byte cacheline), 1187d6034d3SDoug Thompson - inject_word (0..8, 16-bit word of 16-byte section), 1197d6034d3SDoug Thompson - inject_ecc_vector (hex ecc vector: select bits of inject word) 1207d6034d3SDoug Thompson 1217d6034d3SDoug Thompson In addition, there are two control files, inject_read and inject_write, 1227d6034d3SDoug Thompson which trigger the DRAM ECC Read and Write respectively. 123da9bb1d2SAlan Cox 124da9bb1d2SAlan Coxconfig EDAC_AMD76X 125da9bb1d2SAlan Cox tristate "AMD 76x (760, 762, 768)" 12690cbc45bSDave Jones depends on EDAC_MM_EDAC && PCI && X86_32 127da9bb1d2SAlan Cox help 128da9bb1d2SAlan Cox Support for error detection and correction on the AMD 76x 129da9bb1d2SAlan Cox series of chipsets used with the Athlon processor. 130da9bb1d2SAlan Cox 131da9bb1d2SAlan Coxconfig EDAC_E7XXX 132da9bb1d2SAlan Cox tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 13339f1d8d3SDave Peterson depends on EDAC_MM_EDAC && PCI && X86_32 134da9bb1d2SAlan Cox help 135da9bb1d2SAlan Cox Support for error detection and correction on the Intel 136da9bb1d2SAlan Cox E7205, E7500, E7501 and E7505 server chipsets. 137da9bb1d2SAlan Cox 138da9bb1d2SAlan Coxconfig EDAC_E752X 1395135b797SAndrei Konovalov tristate "Intel e752x (e7520, e7525, e7320) and 3100" 14040b31360SStephen Rothwell depends on EDAC_MM_EDAC && PCI && X86 141da9bb1d2SAlan Cox help 142da9bb1d2SAlan Cox Support for error detection and correction on the Intel 143da9bb1d2SAlan Cox E7520, E7525, E7320 server chipsets. 144da9bb1d2SAlan Cox 1455a2c675cSTim Smallconfig EDAC_I82443BXGX 1465a2c675cSTim Small tristate "Intel 82443BX/GX (440BX/GX)" 1475a2c675cSTim Small depends on EDAC_MM_EDAC && PCI && X86_32 14828f96eeaSAndrew Morton depends on BROKEN 1495a2c675cSTim Small help 1505a2c675cSTim Small Support for error detection and correction on the Intel 1515a2c675cSTim Small 82443BX/GX memory controllers (440BX/GX chipsets). 1525a2c675cSTim Small 153da9bb1d2SAlan Coxconfig EDAC_I82875P 154da9bb1d2SAlan Cox tristate "Intel 82875p (D82875P, E7210)" 15539f1d8d3SDave Peterson depends on EDAC_MM_EDAC && PCI && X86_32 156da9bb1d2SAlan Cox help 157da9bb1d2SAlan Cox Support for error detection and correction on the Intel 158da9bb1d2SAlan Cox DP82785P and E7210 server chipsets. 159da9bb1d2SAlan Cox 160420390f0SRanganathan Desikanconfig EDAC_I82975X 161420390f0SRanganathan Desikan tristate "Intel 82975x (D82975x)" 162420390f0SRanganathan Desikan depends on EDAC_MM_EDAC && PCI && X86 163420390f0SRanganathan Desikan help 164420390f0SRanganathan Desikan Support for error detection and correction on the Intel 165420390f0SRanganathan Desikan DP82975x server chipsets. 166420390f0SRanganathan Desikan 167535c6a53SJason Uhlenkottconfig EDAC_I3000 168535c6a53SJason Uhlenkott tristate "Intel 3000/3010" 169f5c0454cSJason Uhlenkott depends on EDAC_MM_EDAC && PCI && X86 170535c6a53SJason Uhlenkott help 171535c6a53SJason Uhlenkott Support for error detection and correction on the Intel 172535c6a53SJason Uhlenkott 3000 and 3010 server chipsets. 173535c6a53SJason Uhlenkott 174dd8ef1dbSJason Uhlenkottconfig EDAC_I3200 175dd8ef1dbSJason Uhlenkott tristate "Intel 3200" 176053417a5SKees Cook depends on EDAC_MM_EDAC && PCI && X86 177dd8ef1dbSJason Uhlenkott help 178dd8ef1dbSJason Uhlenkott Support for error detection and correction on the Intel 179dd8ef1dbSJason Uhlenkott 3200 and 3210 server chipsets. 180dd8ef1dbSJason Uhlenkott 1817ee40b89SJason Baronconfig EDAC_IE31200 1827ee40b89SJason Baron tristate "Intel e312xx" 1837ee40b89SJason Baron depends on EDAC_MM_EDAC && PCI && X86 1847ee40b89SJason Baron help 1857ee40b89SJason Baron Support for error detection and correction on the Intel 1867ee40b89SJason Baron E3-1200 based DRAM controllers. 1877ee40b89SJason Baron 188df8bc08cSHitoshi Mitakeconfig EDAC_X38 189df8bc08cSHitoshi Mitake tristate "Intel X38" 190df8bc08cSHitoshi Mitake depends on EDAC_MM_EDAC && PCI && X86 191df8bc08cSHitoshi Mitake help 192df8bc08cSHitoshi Mitake Support for error detection and correction on the Intel 193df8bc08cSHitoshi Mitake X38 server chipsets. 194df8bc08cSHitoshi Mitake 195920c8df6SMauro Carvalho Chehabconfig EDAC_I5400 196920c8df6SMauro Carvalho Chehab tristate "Intel 5400 (Seaburg) chipsets" 197920c8df6SMauro Carvalho Chehab depends on EDAC_MM_EDAC && PCI && X86 198920c8df6SMauro Carvalho Chehab help 199920c8df6SMauro Carvalho Chehab Support for error detection and correction the Intel 200920c8df6SMauro Carvalho Chehab i5400 MCH chipset (Seaburg). 201920c8df6SMauro Carvalho Chehab 202a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE 203a0c36a1fSMauro Carvalho Chehab tristate "Intel i7 Core (Nehalem) processors" 204168eb34dSBorislav Petkov depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL 205a0c36a1fSMauro Carvalho Chehab help 206a0c36a1fSMauro Carvalho Chehab Support for error detection and correction the Intel 207696e409dSMauro Carvalho Chehab i7 Core (Nehalem) Integrated Memory Controller that exists on 208696e409dSMauro Carvalho Chehab newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 209696e409dSMauro Carvalho Chehab and Xeon 55xx processors. 210a0c36a1fSMauro Carvalho Chehab 211da9bb1d2SAlan Coxconfig EDAC_I82860 212da9bb1d2SAlan Cox tristate "Intel 82860" 21339f1d8d3SDave Peterson depends on EDAC_MM_EDAC && PCI && X86_32 214da9bb1d2SAlan Cox help 215da9bb1d2SAlan Cox Support for error detection and correction on the Intel 216da9bb1d2SAlan Cox 82860 chipset. 217da9bb1d2SAlan Cox 218da9bb1d2SAlan Coxconfig EDAC_R82600 219da9bb1d2SAlan Cox tristate "Radisys 82600 embedded chipset" 22039f1d8d3SDave Peterson depends on EDAC_MM_EDAC && PCI && X86_32 221da9bb1d2SAlan Cox help 222da9bb1d2SAlan Cox Support for error detection and correction on the Radisys 223da9bb1d2SAlan Cox 82600 embedded chipset. 224da9bb1d2SAlan Cox 225eb60705aSEric Wollesenconfig EDAC_I5000 226eb60705aSEric Wollesen tristate "Intel Greencreek/Blackford chipset" 227eb60705aSEric Wollesen depends on EDAC_MM_EDAC && X86 && PCI 228eb60705aSEric Wollesen help 229eb60705aSEric Wollesen Support for error detection and correction the Intel 230eb60705aSEric Wollesen Greekcreek/Blackford chipsets. 231eb60705aSEric Wollesen 2328f421c59SArthur Jonesconfig EDAC_I5100 2338f421c59SArthur Jones tristate "Intel San Clemente MCH" 2348f421c59SArthur Jones depends on EDAC_MM_EDAC && X86 && PCI 2358f421c59SArthur Jones help 2368f421c59SArthur Jones Support for error detection and correction the Intel 2378f421c59SArthur Jones San Clemente MCH. 2388f421c59SArthur Jones 239fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300 240fcaf780bSMauro Carvalho Chehab tristate "Intel Clarksboro MCH" 241fcaf780bSMauro Carvalho Chehab depends on EDAC_MM_EDAC && X86 && PCI 242fcaf780bSMauro Carvalho Chehab help 243fcaf780bSMauro Carvalho Chehab Support for error detection and correction the Intel 244fcaf780bSMauro Carvalho Chehab Clarksboro MCH (Intel 7300 chipset). 245fcaf780bSMauro Carvalho Chehab 2463d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE 24750d1bb93SAristeu Rozanski tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 24822a5c27bSHui Wang depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL 249053417a5SKees Cook depends on PCI_MMCONFIG 2503d78c9afSMauro Carvalho Chehab help 2513d78c9afSMauro Carvalho Chehab Support for error detection and correction the Intel 25250d1bb93SAristeu Rozanski Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2533d78c9afSMauro Carvalho Chehab 254a9a753d5SDave Jiangconfig EDAC_MPC85XX 255b4846251SIra W. Snyder tristate "Freescale MPC83xx / MPC85xx" 25674210267SYork Sun depends on EDAC_MM_EDAC && FSL_SOC 257a9a753d5SDave Jiang help 258a9a753d5SDave Jiang Support for error detection and correction on the Freescale 25974210267SYork Sun MPC8349, MPC8560, MPC8540, MPC8548, T4240 260a9a753d5SDave Jiang 2614f4aeeabSDave Jiangconfig EDAC_MV64X60 2624f4aeeabSDave Jiang tristate "Marvell MV64x60" 2634f4aeeabSDave Jiang depends on EDAC_MM_EDAC && MV64X60 2644f4aeeabSDave Jiang help 2654f4aeeabSDave Jiang Support for error detection and correction on the Marvell 2664f4aeeabSDave Jiang MV64360 and MV64460 chipsets. 2674f4aeeabSDave Jiang 2687d8536fbSEgor Martovetskyconfig EDAC_PASEMI 2697d8536fbSEgor Martovetsky tristate "PA Semi PWRficient" 2707d8536fbSEgor Martovetsky depends on EDAC_MM_EDAC && PCI 271ddcc3050SDoug Thompson depends on PPC_PASEMI 2727d8536fbSEgor Martovetsky help 2737d8536fbSEgor Martovetsky Support for error detection and correction on PA Semi 2747d8536fbSEgor Martovetsky PWRficient. 2757d8536fbSEgor Martovetsky 27648764e41SBenjamin Herrenschmidtconfig EDAC_CELL 27748764e41SBenjamin Herrenschmidt tristate "Cell Broadband Engine memory controller" 278def434c2SBenjamin Krill depends on EDAC_MM_EDAC && PPC_CELL_COMMON 27948764e41SBenjamin Herrenschmidt help 28048764e41SBenjamin Herrenschmidt Support for error detection and correction on the 28148764e41SBenjamin Herrenschmidt Cell Broadband Engine internal memory controller 28248764e41SBenjamin Herrenschmidt on platform without a hypervisor 2837d8536fbSEgor Martovetsky 284dba7a77cSGrant Ericksonconfig EDAC_PPC4XX 285dba7a77cSGrant Erickson tristate "PPC4xx IBM DDR2 Memory Controller" 286dba7a77cSGrant Erickson depends on EDAC_MM_EDAC && 4xx 287dba7a77cSGrant Erickson help 288dba7a77cSGrant Erickson This enables support for EDAC on the ECC memory used 289dba7a77cSGrant Erickson with the IBM DDR2 memory controller found in various 290dba7a77cSGrant Erickson PowerPC 4xx embedded processors such as the 405EX[r], 291dba7a77cSGrant Erickson 440SP, 440SPe, 460EX, 460GT and 460SX. 292dba7a77cSGrant Erickson 293e8765584SHarry Ciaoconfig EDAC_AMD8131 294e8765584SHarry Ciao tristate "AMD8131 HyperTransport PCI-X Tunnel" 295715fe7afSHarry Ciao depends on EDAC_MM_EDAC && PCI && PPC_MAPLE 296e8765584SHarry Ciao help 297e8765584SHarry Ciao Support for error detection and correction on the 298e8765584SHarry Ciao AMD8131 HyperTransport PCI-X Tunnel chip. 299715fe7afSHarry Ciao Note, add more Kconfig dependency if it's adopted 300715fe7afSHarry Ciao on some machine other than Maple. 301e8765584SHarry Ciao 30258b4ce6fSHarry Ciaoconfig EDAC_AMD8111 30358b4ce6fSHarry Ciao tristate "AMD8111 HyperTransport I/O Hub" 304715fe7afSHarry Ciao depends on EDAC_MM_EDAC && PCI && PPC_MAPLE 30558b4ce6fSHarry Ciao help 30658b4ce6fSHarry Ciao Support for error detection and correction on the 30758b4ce6fSHarry Ciao AMD8111 HyperTransport I/O Hub chip. 308715fe7afSHarry Ciao Note, add more Kconfig dependency if it's adopted 309715fe7afSHarry Ciao on some machine other than Maple. 31058b4ce6fSHarry Ciao 3112a9036afSHarry Ciaoconfig EDAC_CPC925 3122a9036afSHarry Ciao tristate "IBM CPC925 Memory Controller (PPC970FX)" 3132a9036afSHarry Ciao depends on EDAC_MM_EDAC && PPC64 3142a9036afSHarry Ciao help 3152a9036afSHarry Ciao Support for error detection and correction on the 3162a9036afSHarry Ciao IBM CPC925 Bridge and Memory Controller, which is 3172a9036afSHarry Ciao a companion chip to the PowerPC 970 family of 3182a9036afSHarry Ciao processors. 3192a9036afSHarry Ciao 3205c770755SChris Metcalfconfig EDAC_TILE 3215c770755SChris Metcalf tristate "Tilera Memory Controller" 3225c770755SChris Metcalf depends on EDAC_MM_EDAC && TILE 3235c770755SChris Metcalf default y 3245c770755SChris Metcalf help 3255c770755SChris Metcalf Support for error detection and correction on the 3265c770755SChris Metcalf Tilera memory controller. 3275c770755SChris Metcalf 328a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC 329a1b01edbSRob Herring tristate "Highbank Memory Controller" 330a1b01edbSRob Herring depends on EDAC_MM_EDAC && ARCH_HIGHBANK 331a1b01edbSRob Herring help 332a1b01edbSRob Herring Support for error detection and correction on the 333a1b01edbSRob Herring Calxeda Highbank memory controller. 334a1b01edbSRob Herring 33569154d06SRob Herringconfig EDAC_HIGHBANK_L2 33669154d06SRob Herring tristate "Highbank L2 Cache" 33769154d06SRob Herring depends on EDAC_MM_EDAC && ARCH_HIGHBANK 33869154d06SRob Herring help 33969154d06SRob Herring Support for error detection and correction on the 34069154d06SRob Herring Calxeda Highbank memory controller. 34169154d06SRob Herring 342f65aad41SRalf Baechleconfig EDAC_OCTEON_PC 343f65aad41SRalf Baechle tristate "Cavium Octeon Primary Caches" 344f65aad41SRalf Baechle depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON 345f65aad41SRalf Baechle help 346f65aad41SRalf Baechle Support for error detection and correction on the primary caches of 347f65aad41SRalf Baechle the cnMIPS cores of Cavium Octeon family SOCs. 348f65aad41SRalf Baechle 349f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C 350f65aad41SRalf Baechle tristate "Cavium Octeon Secondary Caches (L2C)" 3519ddebc46SDavid Daney depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC 352f65aad41SRalf Baechle help 353f65aad41SRalf Baechle Support for error detection and correction on the 354f65aad41SRalf Baechle Cavium Octeon family of SOCs. 355f65aad41SRalf Baechle 356f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC 357f65aad41SRalf Baechle tristate "Cavium Octeon DRAM Memory Controller (LMC)" 3589ddebc46SDavid Daney depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC 359f65aad41SRalf Baechle help 360f65aad41SRalf Baechle Support for error detection and correction on the 361f65aad41SRalf Baechle Cavium Octeon family of SOCs. 362f65aad41SRalf Baechle 363f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI 364f65aad41SRalf Baechle tristate "Cavium Octeon PCI Controller" 3659ddebc46SDavid Daney depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC 366f65aad41SRalf Baechle help 367f65aad41SRalf Baechle Support for error detection and correction on the 368f65aad41SRalf Baechle Cavium Octeon family of SOCs. 369f65aad41SRalf Baechle 370c3eea194SThor Thayerconfig EDAC_ALTERA 371c3eea194SThor Thayer bool "Altera SOCFPGA ECC" 3727e52a036SThor Thayer depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA 37371bcada8SThor Thayer help 37471bcada8SThor Thayer Support for error detection and correction on the 375c3eea194SThor Thayer Altera SOCs. This must be selected for SDRAM ECC. 376c3eea194SThor Thayer Note that the preloader must initialize the SDRAM 377c3eea194SThor Thayer before loading the kernel. 378c3eea194SThor Thayer 379c3eea194SThor Thayerconfig EDAC_ALTERA_L2C 380c3eea194SThor Thayer bool "Altera L2 Cache ECC" 3813a8f21f1SThor Thayer depends on EDAC_ALTERA=y && CACHE_L2X0 382c3eea194SThor Thayer help 383c3eea194SThor Thayer Support for error detection and correction on the 384c3eea194SThor Thayer Altera L2 cache Memory for Altera SoCs. This option 3853a8f21f1SThor Thayer requires L2 cache. 386c3eea194SThor Thayer 387c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM 388c3eea194SThor Thayer bool "Altera On-Chip RAM ECC" 389c3eea194SThor Thayer depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 390c3eea194SThor Thayer help 391c3eea194SThor Thayer Support for error detection and correction on the 392c3eea194SThor Thayer Altera On-Chip RAM Memory for Altera SoCs. 39371bcada8SThor Thayer 394ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET 395ab8c1e0fSThor Thayer bool "Altera Ethernet FIFO ECC" 396ab8c1e0fSThor Thayer depends on EDAC_ALTERA=y 397ab8c1e0fSThor Thayer help 398ab8c1e0fSThor Thayer Support for error detection and correction on the 399ab8c1e0fSThor Thayer Altera Ethernet FIFO Memory for Altera SoCs. 400ab8c1e0fSThor Thayer 401c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND 402c6882fb2SThor Thayer bool "Altera NAND FIFO ECC" 403c6882fb2SThor Thayer depends on EDAC_ALTERA=y && MTD_NAND_DENALI 404c6882fb2SThor Thayer help 405c6882fb2SThor Thayer Support for error detection and correction on the 406c6882fb2SThor Thayer Altera NAND FIFO Memory for Altera SoCs. 407c6882fb2SThor Thayer 408e8263793SThor Thayerconfig EDAC_ALTERA_DMA 409e8263793SThor Thayer bool "Altera DMA FIFO ECC" 410e8263793SThor Thayer depends on EDAC_ALTERA=y && PL330_DMA=y 411e8263793SThor Thayer help 412e8263793SThor Thayer Support for error detection and correction on the 413e8263793SThor Thayer Altera DMA FIFO Memory for Altera SoCs. 414e8263793SThor Thayer 415c609581dSThor Thayerconfig EDAC_ALTERA_USB 416c609581dSThor Thayer bool "Altera USB FIFO ECC" 417c609581dSThor Thayer depends on EDAC_ALTERA=y && USB_DWC2 418c609581dSThor Thayer help 419c609581dSThor Thayer Support for error detection and correction on the 420c609581dSThor Thayer Altera USB FIFO Memory for Altera SoCs. 421c609581dSThor Thayer 422*485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI 423*485fe9e2SThor Thayer bool "Altera QSPI FIFO ECC" 424*485fe9e2SThor Thayer depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 425*485fe9e2SThor Thayer help 426*485fe9e2SThor Thayer Support for error detection and correction on the 427*485fe9e2SThor Thayer Altera QSPI FIFO Memory for Altera SoCs. 428*485fe9e2SThor Thayer 429ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS 430ae9b56e3SPunnaiah Choudary Kalluri tristate "Synopsys DDR Memory Controller" 431ae9b56e3SPunnaiah Choudary Kalluri depends on EDAC_MM_EDAC && ARCH_ZYNQ 432ae9b56e3SPunnaiah Choudary Kalluri help 433ae9b56e3SPunnaiah Choudary Kalluri Support for error detection and correction on the Synopsys DDR 434ae9b56e3SPunnaiah Choudary Kalluri memory controller. 435ae9b56e3SPunnaiah Choudary Kalluri 4360d442930SLoc Hoconfig EDAC_XGENE 4370d442930SLoc Ho tristate "APM X-Gene SoC" 4380d442930SLoc Ho depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST) 4390d442930SLoc Ho help 4400d442930SLoc Ho Support for error detection and correction on the 4410d442930SLoc Ho APM X-Gene family of SOCs. 4420d442930SLoc Ho 443751cb5e5SJan Engelhardtendif # EDAC 444