1da9bb1d2SAlan Cox# 2da9bb1d2SAlan Cox# EDAC Kconfig 34577ca55SDoug Thompson# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4da9bb1d2SAlan Cox# Licensed and distributed under the GPL 5b01aec9bSBorislav Petkov 6b01aec9bSBorislav Petkovconfig EDAC_ATOMIC_SCRUB 7b01aec9bSBorislav Petkov bool 8da9bb1d2SAlan Cox 954451663SBorislav Petkovconfig EDAC_SUPPORT 1054451663SBorislav Petkov bool 1154451663SBorislav Petkov 12751cb5e5SJan Engelhardtmenuconfig EDAC 13e3c4ff6dSBorislav Petkov tristate "EDAC (Error Detection And Correction) reporting" 14e3c4ff6dSBorislav Petkov depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15da9bb1d2SAlan Cox help 16a06b85ffSBorislav Petkov EDAC is a subsystem along with hardware-specific drivers designed to 17a06b85ffSBorislav Petkov report hardware errors. These are low-level errors that are reported 18a06b85ffSBorislav Petkov in the CPU or supporting chipset or other subsystems: 198cb2a398SDouglas Thompson memory errors, cache errors, PCI errors, thermal throttling, etc.. 208cb2a398SDouglas Thompson If unsure, select 'Y'. 21da9bb1d2SAlan Cox 22a06b85ffSBorislav Petkov The mailing list for the EDAC project is linux-edac@vger.kernel.org. 2357c432b5STim Small 24751cb5e5SJan Engelhardtif EDAC 25da9bb1d2SAlan Cox 2619974710SMauro Carvalho Chehabconfig EDAC_LEGACY_SYSFS 2719974710SMauro Carvalho Chehab bool "EDAC legacy sysfs" 2819974710SMauro Carvalho Chehab default y 2919974710SMauro Carvalho Chehab help 3019974710SMauro Carvalho Chehab Enable the compatibility sysfs nodes. 3119974710SMauro Carvalho Chehab Use 'Y' if your edac utilities aren't ported to work with the newer 3219974710SMauro Carvalho Chehab structures. 3319974710SMauro Carvalho Chehab 34da9bb1d2SAlan Coxconfig EDAC_DEBUG 35da9bb1d2SAlan Cox bool "Debugging" 361c5bf781SBorislav Petkov select DEBUG_FS 37da9bb1d2SAlan Cox help 3837929874SBorislav Petkov This turns on debugging information for the entire EDAC subsystem. 3937929874SBorislav Petkov You do so by inserting edac_module with "edac_debug_level=x." Valid 4037929874SBorislav Petkov levels are 0-4 (from low to high) and by default it is set to 2. 4137929874SBorislav Petkov Usually you should select 'N' here. 42da9bb1d2SAlan Cox 430d18b2e3SBorislav Petkovconfig EDAC_DECODE_MCE 440d18b2e3SBorislav Petkov tristate "Decode MCEs in human-readable form (only on AMD for now)" 45168eb34dSBorislav Petkov depends on CPU_SUP_AMD && X86_MCE_AMD 460d18b2e3SBorislav Petkov default y 470d18b2e3SBorislav Petkov ---help--- 480d18b2e3SBorislav Petkov Enable this option if you want to decode Machine Check Exceptions 4925985edcSLucas De Marchi occurring on your machine in human-readable form. 500d18b2e3SBorislav Petkov 510d18b2e3SBorislav Petkov You should definitely say Y here in case you want to decode MCEs 520d18b2e3SBorislav Petkov which occur really early upon boot, before the module infrastructure 530d18b2e3SBorislav Petkov has been initialized. 540d18b2e3SBorislav Petkov 5577c5f5d2SMauro Carvalho Chehabconfig EDAC_GHES 5677c5f5d2SMauro Carvalho Chehab bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57e3c4ff6dSBorislav Petkov depends on ACPI_APEI_GHES && (EDAC=y) 5877c5f5d2SMauro Carvalho Chehab help 5977c5f5d2SMauro Carvalho Chehab Not all machines support hardware-driven error report. Some of those 6077c5f5d2SMauro Carvalho Chehab provide a BIOS-driven error report mechanism via ACPI, using the 6177c5f5d2SMauro Carvalho Chehab APEI/GHES driver. By enabling this option, the error reports provided 6277c5f5d2SMauro Carvalho Chehab by GHES are sent to userspace via the EDAC API. 6377c5f5d2SMauro Carvalho Chehab 6477c5f5d2SMauro Carvalho Chehab When this option is enabled, it will disable the hardware-driven 6577c5f5d2SMauro Carvalho Chehab mechanisms, if a GHES BIOS is detected, entering into the 6677c5f5d2SMauro Carvalho Chehab "Firmware First" mode. 6777c5f5d2SMauro Carvalho Chehab 6877c5f5d2SMauro Carvalho Chehab It should be noticed that keeping both GHES and a hardware-driven 6977c5f5d2SMauro Carvalho Chehab error mechanism won't work well, as BIOS will race with OS, while 7077c5f5d2SMauro Carvalho Chehab reading the error registers. So, if you want to not use "Firmware 7177c5f5d2SMauro Carvalho Chehab first" GHES error mechanism, you should disable GHES either at 7277c5f5d2SMauro Carvalho Chehab compilation time or by passing "ghes.disable=1" Kernel parameter 7377c5f5d2SMauro Carvalho Chehab at boot time. 7477c5f5d2SMauro Carvalho Chehab 7577c5f5d2SMauro Carvalho Chehab In doubt, say 'Y'. 7677c5f5d2SMauro Carvalho Chehab 777d6034d3SDoug Thompsonconfig EDAC_AMD64 78f5b10c45STomasz Pala tristate "AMD64 (Opteron, Athlon64)" 79e3c4ff6dSBorislav Petkov depends on AMD_NB && EDAC_DECODE_MCE 807d6034d3SDoug Thompson help 81027dbd6fSBorislav Petkov Support for error detection and correction of DRAM ECC errors on 82f5b10c45STomasz Pala the AMD64 families (>= K8) of memory controllers. 837d6034d3SDoug Thompson 847d6034d3SDoug Thompsonconfig EDAC_AMD64_ERROR_INJECTION 859cdeb404SBorislav Petkov bool "Sysfs HW Error injection facilities" 867d6034d3SDoug Thompson depends on EDAC_AMD64 877d6034d3SDoug Thompson help 887d6034d3SDoug Thompson Recent Opterons (Family 10h and later) provide for Memory Error 897d6034d3SDoug Thompson Injection into the ECC detection circuits. The amd64_edac module 907d6034d3SDoug Thompson allows the operator/user to inject Uncorrectable and Correctable 917d6034d3SDoug Thompson errors into DRAM. 927d6034d3SDoug Thompson 937d6034d3SDoug Thompson When enabled, in each of the respective memory controller directories 947d6034d3SDoug Thompson (/sys/devices/system/edac/mc/mcX), there are 3 input files: 957d6034d3SDoug Thompson 967d6034d3SDoug Thompson - inject_section (0..3, 16-byte section of 64-byte cacheline), 977d6034d3SDoug Thompson - inject_word (0..8, 16-bit word of 16-byte section), 987d6034d3SDoug Thompson - inject_ecc_vector (hex ecc vector: select bits of inject word) 997d6034d3SDoug Thompson 1007d6034d3SDoug Thompson In addition, there are two control files, inject_read and inject_write, 1017d6034d3SDoug Thompson which trigger the DRAM ECC Read and Write respectively. 102da9bb1d2SAlan Cox 103da9bb1d2SAlan Coxconfig EDAC_AMD76X 104da9bb1d2SAlan Cox tristate "AMD 76x (760, 762, 768)" 105e3c4ff6dSBorislav Petkov depends on PCI && X86_32 106da9bb1d2SAlan Cox help 107da9bb1d2SAlan Cox Support for error detection and correction on the AMD 76x 108da9bb1d2SAlan Cox series of chipsets used with the Athlon processor. 109da9bb1d2SAlan Cox 110da9bb1d2SAlan Coxconfig EDAC_E7XXX 111da9bb1d2SAlan Cox tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 112e3c4ff6dSBorislav Petkov depends on PCI && X86_32 113da9bb1d2SAlan Cox help 114da9bb1d2SAlan Cox Support for error detection and correction on the Intel 115da9bb1d2SAlan Cox E7205, E7500, E7501 and E7505 server chipsets. 116da9bb1d2SAlan Cox 117da9bb1d2SAlan Coxconfig EDAC_E752X 1185135b797SAndrei Konovalov tristate "Intel e752x (e7520, e7525, e7320) and 3100" 119e3c4ff6dSBorislav Petkov depends on PCI && X86 120da9bb1d2SAlan Cox help 121da9bb1d2SAlan Cox Support for error detection and correction on the Intel 122da9bb1d2SAlan Cox E7520, E7525, E7320 server chipsets. 123da9bb1d2SAlan Cox 1245a2c675cSTim Smallconfig EDAC_I82443BXGX 1255a2c675cSTim Small tristate "Intel 82443BX/GX (440BX/GX)" 126e3c4ff6dSBorislav Petkov depends on PCI && X86_32 12728f96eeaSAndrew Morton depends on BROKEN 1285a2c675cSTim Small help 1295a2c675cSTim Small Support for error detection and correction on the Intel 1305a2c675cSTim Small 82443BX/GX memory controllers (440BX/GX chipsets). 1315a2c675cSTim Small 132da9bb1d2SAlan Coxconfig EDAC_I82875P 133da9bb1d2SAlan Cox tristate "Intel 82875p (D82875P, E7210)" 134e3c4ff6dSBorislav Petkov depends on PCI && X86_32 135da9bb1d2SAlan Cox help 136da9bb1d2SAlan Cox Support for error detection and correction on the Intel 137da9bb1d2SAlan Cox DP82785P and E7210 server chipsets. 138da9bb1d2SAlan Cox 139420390f0SRanganathan Desikanconfig EDAC_I82975X 140420390f0SRanganathan Desikan tristate "Intel 82975x (D82975x)" 141e3c4ff6dSBorislav Petkov depends on PCI && X86 142420390f0SRanganathan Desikan help 143420390f0SRanganathan Desikan Support for error detection and correction on the Intel 144420390f0SRanganathan Desikan DP82975x server chipsets. 145420390f0SRanganathan Desikan 146535c6a53SJason Uhlenkottconfig EDAC_I3000 147535c6a53SJason Uhlenkott tristate "Intel 3000/3010" 148e3c4ff6dSBorislav Petkov depends on PCI && X86 149535c6a53SJason Uhlenkott help 150535c6a53SJason Uhlenkott Support for error detection and correction on the Intel 151535c6a53SJason Uhlenkott 3000 and 3010 server chipsets. 152535c6a53SJason Uhlenkott 153dd8ef1dbSJason Uhlenkottconfig EDAC_I3200 154dd8ef1dbSJason Uhlenkott tristate "Intel 3200" 155e3c4ff6dSBorislav Petkov depends on PCI && X86 156dd8ef1dbSJason Uhlenkott help 157dd8ef1dbSJason Uhlenkott Support for error detection and correction on the Intel 158dd8ef1dbSJason Uhlenkott 3200 and 3210 server chipsets. 159dd8ef1dbSJason Uhlenkott 1607ee40b89SJason Baronconfig EDAC_IE31200 1617ee40b89SJason Baron tristate "Intel e312xx" 162e3c4ff6dSBorislav Petkov depends on PCI && X86 1637ee40b89SJason Baron help 1647ee40b89SJason Baron Support for error detection and correction on the Intel 1657ee40b89SJason Baron E3-1200 based DRAM controllers. 1667ee40b89SJason Baron 167df8bc08cSHitoshi Mitakeconfig EDAC_X38 168df8bc08cSHitoshi Mitake tristate "Intel X38" 169e3c4ff6dSBorislav Petkov depends on PCI && X86 170df8bc08cSHitoshi Mitake help 171df8bc08cSHitoshi Mitake Support for error detection and correction on the Intel 172df8bc08cSHitoshi Mitake X38 server chipsets. 173df8bc08cSHitoshi Mitake 174920c8df6SMauro Carvalho Chehabconfig EDAC_I5400 175920c8df6SMauro Carvalho Chehab tristate "Intel 5400 (Seaburg) chipsets" 176e3c4ff6dSBorislav Petkov depends on PCI && X86 177920c8df6SMauro Carvalho Chehab help 178920c8df6SMauro Carvalho Chehab Support for error detection and correction the Intel 179920c8df6SMauro Carvalho Chehab i5400 MCH chipset (Seaburg). 180920c8df6SMauro Carvalho Chehab 181a0c36a1fSMauro Carvalho Chehabconfig EDAC_I7CORE 182a0c36a1fSMauro Carvalho Chehab tristate "Intel i7 Core (Nehalem) processors" 183e3c4ff6dSBorislav Petkov depends on PCI && X86 && X86_MCE_INTEL 184a0c36a1fSMauro Carvalho Chehab help 185a0c36a1fSMauro Carvalho Chehab Support for error detection and correction the Intel 186696e409dSMauro Carvalho Chehab i7 Core (Nehalem) Integrated Memory Controller that exists on 187696e409dSMauro Carvalho Chehab newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 188696e409dSMauro Carvalho Chehab and Xeon 55xx processors. 189a0c36a1fSMauro Carvalho Chehab 190da9bb1d2SAlan Coxconfig EDAC_I82860 191da9bb1d2SAlan Cox tristate "Intel 82860" 192e3c4ff6dSBorislav Petkov depends on PCI && X86_32 193da9bb1d2SAlan Cox help 194da9bb1d2SAlan Cox Support for error detection and correction on the Intel 195da9bb1d2SAlan Cox 82860 chipset. 196da9bb1d2SAlan Cox 197da9bb1d2SAlan Coxconfig EDAC_R82600 198da9bb1d2SAlan Cox tristate "Radisys 82600 embedded chipset" 199e3c4ff6dSBorislav Petkov depends on PCI && X86_32 200da9bb1d2SAlan Cox help 201da9bb1d2SAlan Cox Support for error detection and correction on the Radisys 202da9bb1d2SAlan Cox 82600 embedded chipset. 203da9bb1d2SAlan Cox 204eb60705aSEric Wollesenconfig EDAC_I5000 205eb60705aSEric Wollesen tristate "Intel Greencreek/Blackford chipset" 206e3c4ff6dSBorislav Petkov depends on X86 && PCI 207eb60705aSEric Wollesen help 208eb60705aSEric Wollesen Support for error detection and correction the Intel 209eb60705aSEric Wollesen Greekcreek/Blackford chipsets. 210eb60705aSEric Wollesen 2118f421c59SArthur Jonesconfig EDAC_I5100 2128f421c59SArthur Jones tristate "Intel San Clemente MCH" 213e3c4ff6dSBorislav Petkov depends on X86 && PCI 2148f421c59SArthur Jones help 2158f421c59SArthur Jones Support for error detection and correction the Intel 2168f421c59SArthur Jones San Clemente MCH. 2178f421c59SArthur Jones 218fcaf780bSMauro Carvalho Chehabconfig EDAC_I7300 219fcaf780bSMauro Carvalho Chehab tristate "Intel Clarksboro MCH" 220e3c4ff6dSBorislav Petkov depends on X86 && PCI 221fcaf780bSMauro Carvalho Chehab help 222fcaf780bSMauro Carvalho Chehab Support for error detection and correction the Intel 223fcaf780bSMauro Carvalho Chehab Clarksboro MCH (Intel 7300 chipset). 224fcaf780bSMauro Carvalho Chehab 2253d78c9afSMauro Carvalho Chehabconfig EDAC_SBRIDGE 22650d1bb93SAristeu Rozanski tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 227e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2283d78c9afSMauro Carvalho Chehab help 2293d78c9afSMauro Carvalho Chehab Support for error detection and correction the Intel 23050d1bb93SAristeu Rozanski Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2313d78c9afSMauro Carvalho Chehab 2324ec656bdSTony Luckconfig EDAC_SKX 2334ec656bdSTony Luck tristate "Intel Skylake server Integrated MC" 234e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 23558ca9ac1STony Luck select DMI 2364ec656bdSTony Luck help 2374ec656bdSTony Luck Support for error detection and correction the Intel 23858ca9ac1STony Luck Skylake server Integrated Memory Controllers. If your 23958ca9ac1STony Luck system has non-volatile DIMMs you should also manually 24058ca9ac1STony Luck select CONFIG_ACPI_NFIT. 2414ec656bdSTony Luck 2425c71ad17STony Luckconfig EDAC_PND2 2435c71ad17STony Luck tristate "Intel Pondicherry2" 244e3c4ff6dSBorislav Petkov depends on PCI && X86_64 && X86_MCE_INTEL 2455c71ad17STony Luck help 2465c71ad17STony Luck Support for error detection and correction on the Intel 2475c71ad17STony Luck Pondicherry2 Integrated Memory Controller. This SoC IP is 2485c71ad17STony Luck first used on the Apollo Lake platform and Denverton 2495c71ad17STony Luck micro-server but may appear on others in the future. 2505c71ad17STony Luck 251a9a753d5SDave Jiangconfig EDAC_MPC85XX 252b4846251SIra W. Snyder tristate "Freescale MPC83xx / MPC85xx" 253e3c4ff6dSBorislav Petkov depends on FSL_SOC 254a9a753d5SDave Jiang help 255a9a753d5SDave Jiang Support for error detection and correction on the Freescale 25674210267SYork Sun MPC8349, MPC8560, MPC8540, MPC8548, T4240 257a9a753d5SDave Jiang 258eeb3d68bSYork Sunconfig EDAC_LAYERSCAPE 259eeb3d68bSYork Sun tristate "Freescale Layerscape DDR" 26028dd6726SRasmus Villemoes depends on ARCH_LAYERSCAPE || SOC_LS1021A 261eeb3d68bSYork Sun help 262eeb3d68bSYork Sun Support for error detection and correction on Freescale memory 263eeb3d68bSYork Sun controllers on Layerscape SoCs. 264eeb3d68bSYork Sun 2654f4aeeabSDave Jiangconfig EDAC_MV64X60 2664f4aeeabSDave Jiang tristate "Marvell MV64x60" 267e3c4ff6dSBorislav Petkov depends on MV64X60 2684f4aeeabSDave Jiang help 2694f4aeeabSDave Jiang Support for error detection and correction on the Marvell 2704f4aeeabSDave Jiang MV64360 and MV64460 chipsets. 2714f4aeeabSDave Jiang 2727d8536fbSEgor Martovetskyconfig EDAC_PASEMI 2737d8536fbSEgor Martovetsky tristate "PA Semi PWRficient" 274e3c4ff6dSBorislav Petkov depends on PPC_PASEMI && PCI 2757d8536fbSEgor Martovetsky help 2767d8536fbSEgor Martovetsky Support for error detection and correction on PA Semi 2777d8536fbSEgor Martovetsky PWRficient. 2787d8536fbSEgor Martovetsky 27948764e41SBenjamin Herrenschmidtconfig EDAC_CELL 28048764e41SBenjamin Herrenschmidt tristate "Cell Broadband Engine memory controller" 281e3c4ff6dSBorislav Petkov depends on PPC_CELL_COMMON 28248764e41SBenjamin Herrenschmidt help 28348764e41SBenjamin Herrenschmidt Support for error detection and correction on the 28448764e41SBenjamin Herrenschmidt Cell Broadband Engine internal memory controller 28548764e41SBenjamin Herrenschmidt on platform without a hypervisor 2867d8536fbSEgor Martovetsky 287dba7a77cSGrant Ericksonconfig EDAC_PPC4XX 288dba7a77cSGrant Erickson tristate "PPC4xx IBM DDR2 Memory Controller" 289e3c4ff6dSBorislav Petkov depends on 4xx 290dba7a77cSGrant Erickson help 291dba7a77cSGrant Erickson This enables support for EDAC on the ECC memory used 292dba7a77cSGrant Erickson with the IBM DDR2 memory controller found in various 293dba7a77cSGrant Erickson PowerPC 4xx embedded processors such as the 405EX[r], 294dba7a77cSGrant Erickson 440SP, 440SPe, 460EX, 460GT and 460SX. 295dba7a77cSGrant Erickson 296e8765584SHarry Ciaoconfig EDAC_AMD8131 297e8765584SHarry Ciao tristate "AMD8131 HyperTransport PCI-X Tunnel" 298e3c4ff6dSBorislav Petkov depends on PCI && PPC_MAPLE 299e8765584SHarry Ciao help 300e8765584SHarry Ciao Support for error detection and correction on the 301e8765584SHarry Ciao AMD8131 HyperTransport PCI-X Tunnel chip. 302715fe7afSHarry Ciao Note, add more Kconfig dependency if it's adopted 303715fe7afSHarry Ciao on some machine other than Maple. 304e8765584SHarry Ciao 30558b4ce6fSHarry Ciaoconfig EDAC_AMD8111 30658b4ce6fSHarry Ciao tristate "AMD8111 HyperTransport I/O Hub" 307e3c4ff6dSBorislav Petkov depends on PCI && PPC_MAPLE 30858b4ce6fSHarry Ciao help 30958b4ce6fSHarry Ciao Support for error detection and correction on the 31058b4ce6fSHarry Ciao AMD8111 HyperTransport I/O Hub chip. 311715fe7afSHarry Ciao Note, add more Kconfig dependency if it's adopted 312715fe7afSHarry Ciao on some machine other than Maple. 31358b4ce6fSHarry Ciao 3142a9036afSHarry Ciaoconfig EDAC_CPC925 3152a9036afSHarry Ciao tristate "IBM CPC925 Memory Controller (PPC970FX)" 316e3c4ff6dSBorislav Petkov depends on PPC64 3172a9036afSHarry Ciao help 3182a9036afSHarry Ciao Support for error detection and correction on the 3192a9036afSHarry Ciao IBM CPC925 Bridge and Memory Controller, which is 3202a9036afSHarry Ciao a companion chip to the PowerPC 970 family of 3212a9036afSHarry Ciao processors. 3222a9036afSHarry Ciao 323a1b01edbSRob Herringconfig EDAC_HIGHBANK_MC 324a1b01edbSRob Herring tristate "Highbank Memory Controller" 325e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 326a1b01edbSRob Herring help 327a1b01edbSRob Herring Support for error detection and correction on the 328a1b01edbSRob Herring Calxeda Highbank memory controller. 329a1b01edbSRob Herring 33069154d06SRob Herringconfig EDAC_HIGHBANK_L2 33169154d06SRob Herring tristate "Highbank L2 Cache" 332e3c4ff6dSBorislav Petkov depends on ARCH_HIGHBANK 33369154d06SRob Herring help 33469154d06SRob Herring Support for error detection and correction on the 33569154d06SRob Herring Calxeda Highbank memory controller. 33669154d06SRob Herring 337f65aad41SRalf Baechleconfig EDAC_OCTEON_PC 338f65aad41SRalf Baechle tristate "Cavium Octeon Primary Caches" 339e3c4ff6dSBorislav Petkov depends on CPU_CAVIUM_OCTEON 340f65aad41SRalf Baechle help 341f65aad41SRalf Baechle Support for error detection and correction on the primary caches of 342f65aad41SRalf Baechle the cnMIPS cores of Cavium Octeon family SOCs. 343f65aad41SRalf Baechle 344f65aad41SRalf Baechleconfig EDAC_OCTEON_L2C 345f65aad41SRalf Baechle tristate "Cavium Octeon Secondary Caches (L2C)" 346e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 347f65aad41SRalf Baechle help 348f65aad41SRalf Baechle Support for error detection and correction on the 349f65aad41SRalf Baechle Cavium Octeon family of SOCs. 350f65aad41SRalf Baechle 351f65aad41SRalf Baechleconfig EDAC_OCTEON_LMC 352f65aad41SRalf Baechle tristate "Cavium Octeon DRAM Memory Controller (LMC)" 353e3c4ff6dSBorislav Petkov depends on CAVIUM_OCTEON_SOC 354f65aad41SRalf Baechle help 355f65aad41SRalf Baechle Support for error detection and correction on the 356f65aad41SRalf Baechle Cavium Octeon family of SOCs. 357f65aad41SRalf Baechle 358f65aad41SRalf Baechleconfig EDAC_OCTEON_PCI 359f65aad41SRalf Baechle tristate "Cavium Octeon PCI Controller" 360e3c4ff6dSBorislav Petkov depends on PCI && CAVIUM_OCTEON_SOC 361f65aad41SRalf Baechle help 362f65aad41SRalf Baechle Support for error detection and correction on the 363f65aad41SRalf Baechle Cavium Octeon family of SOCs. 364f65aad41SRalf Baechle 36541003396SSergey Temerkhanovconfig EDAC_THUNDERX 36641003396SSergey Temerkhanov tristate "Cavium ThunderX EDAC" 36741003396SSergey Temerkhanov depends on ARM64 36841003396SSergey Temerkhanov depends on PCI 36941003396SSergey Temerkhanov help 37041003396SSergey Temerkhanov Support for error detection and correction on the 37141003396SSergey Temerkhanov Cavium ThunderX memory controllers (LMC), Cache 37241003396SSergey Temerkhanov Coherent Processor Interconnect (CCPI) and L2 cache 37341003396SSergey Temerkhanov blocks (TAD, CBC, MCI). 37441003396SSergey Temerkhanov 375c3eea194SThor Thayerconfig EDAC_ALTERA 376c3eea194SThor Thayer bool "Altera SOCFPGA ECC" 377*3dab6bd5SThor Thayer depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10) 37871bcada8SThor Thayer help 37971bcada8SThor Thayer Support for error detection and correction on the 380c3eea194SThor Thayer Altera SOCs. This must be selected for SDRAM ECC. 381c3eea194SThor Thayer Note that the preloader must initialize the SDRAM 382c3eea194SThor Thayer before loading the kernel. 383c3eea194SThor Thayer 384c3eea194SThor Thayerconfig EDAC_ALTERA_L2C 385c3eea194SThor Thayer bool "Altera L2 Cache ECC" 3863a8f21f1SThor Thayer depends on EDAC_ALTERA=y && CACHE_L2X0 387c3eea194SThor Thayer help 388c3eea194SThor Thayer Support for error detection and correction on the 389c3eea194SThor Thayer Altera L2 cache Memory for Altera SoCs. This option 3903a8f21f1SThor Thayer requires L2 cache. 391c3eea194SThor Thayer 392c3eea194SThor Thayerconfig EDAC_ALTERA_OCRAM 393c3eea194SThor Thayer bool "Altera On-Chip RAM ECC" 394c3eea194SThor Thayer depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 395c3eea194SThor Thayer help 396c3eea194SThor Thayer Support for error detection and correction on the 397c3eea194SThor Thayer Altera On-Chip RAM Memory for Altera SoCs. 39871bcada8SThor Thayer 399ab8c1e0fSThor Thayerconfig EDAC_ALTERA_ETHERNET 400ab8c1e0fSThor Thayer bool "Altera Ethernet FIFO ECC" 401ab8c1e0fSThor Thayer depends on EDAC_ALTERA=y 402ab8c1e0fSThor Thayer help 403ab8c1e0fSThor Thayer Support for error detection and correction on the 404ab8c1e0fSThor Thayer Altera Ethernet FIFO Memory for Altera SoCs. 405ab8c1e0fSThor Thayer 406c6882fb2SThor Thayerconfig EDAC_ALTERA_NAND 407c6882fb2SThor Thayer bool "Altera NAND FIFO ECC" 408c6882fb2SThor Thayer depends on EDAC_ALTERA=y && MTD_NAND_DENALI 409c6882fb2SThor Thayer help 410c6882fb2SThor Thayer Support for error detection and correction on the 411c6882fb2SThor Thayer Altera NAND FIFO Memory for Altera SoCs. 412c6882fb2SThor Thayer 413e8263793SThor Thayerconfig EDAC_ALTERA_DMA 414e8263793SThor Thayer bool "Altera DMA FIFO ECC" 415e8263793SThor Thayer depends on EDAC_ALTERA=y && PL330_DMA=y 416e8263793SThor Thayer help 417e8263793SThor Thayer Support for error detection and correction on the 418e8263793SThor Thayer Altera DMA FIFO Memory for Altera SoCs. 419e8263793SThor Thayer 420c609581dSThor Thayerconfig EDAC_ALTERA_USB 421c609581dSThor Thayer bool "Altera USB FIFO ECC" 422c609581dSThor Thayer depends on EDAC_ALTERA=y && USB_DWC2 423c609581dSThor Thayer help 424c609581dSThor Thayer Support for error detection and correction on the 425c609581dSThor Thayer Altera USB FIFO Memory for Altera SoCs. 426c609581dSThor Thayer 427485fe9e2SThor Thayerconfig EDAC_ALTERA_QSPI 428485fe9e2SThor Thayer bool "Altera QSPI FIFO ECC" 429485fe9e2SThor Thayer depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 430485fe9e2SThor Thayer help 431485fe9e2SThor Thayer Support for error detection and correction on the 432485fe9e2SThor Thayer Altera QSPI FIFO Memory for Altera SoCs. 433485fe9e2SThor Thayer 43491104984SThor Thayerconfig EDAC_ALTERA_SDMMC 43591104984SThor Thayer bool "Altera SDMMC FIFO ECC" 43691104984SThor Thayer depends on EDAC_ALTERA=y && MMC_DW 43791104984SThor Thayer help 43891104984SThor Thayer Support for error detection and correction on the 43991104984SThor Thayer Altera SDMMC FIFO Memory for Altera SoCs. 44091104984SThor Thayer 441ae9b56e3SPunnaiah Choudary Kalluriconfig EDAC_SYNOPSYS 442ae9b56e3SPunnaiah Choudary Kalluri tristate "Synopsys DDR Memory Controller" 443e3c4ff6dSBorislav Petkov depends on ARCH_ZYNQ 444ae9b56e3SPunnaiah Choudary Kalluri help 445ae9b56e3SPunnaiah Choudary Kalluri Support for error detection and correction on the Synopsys DDR 446ae9b56e3SPunnaiah Choudary Kalluri memory controller. 447ae9b56e3SPunnaiah Choudary Kalluri 4480d442930SLoc Hoconfig EDAC_XGENE 4490d442930SLoc Ho tristate "APM X-Gene SoC" 450e3c4ff6dSBorislav Petkov depends on (ARM64 || COMPILE_TEST) 4510d442930SLoc Ho help 4520d442930SLoc Ho Support for error detection and correction on the 4530d442930SLoc Ho APM X-Gene family of SOCs. 4540d442930SLoc Ho 45586a18ee2STero Kristoconfig EDAC_TI 45686a18ee2STero Kristo tristate "Texas Instruments DDR3 ECC Controller" 45786a18ee2STero Kristo depends on ARCH_KEYSTONE || SOC_DRA7XX 45886a18ee2STero Kristo help 45986a18ee2STero Kristo Support for error detection and correction on the 46086a18ee2STero Kristo TI SoCs. 46186a18ee2STero Kristo 462751cb5e5SJan Engelhardtendif # EDAC 463