19d831528SAngelo Dureghello /* SPDX-License-Identifier: GPL-2.0+ */ 29d831528SAngelo Dureghello /* 39d831528SAngelo Dureghello * Copyright 2013-2014 Freescale Semiconductor, Inc. 49d831528SAngelo Dureghello * Copyright 2018 Angelo Dureghello <angelo@sysam.it> 59d831528SAngelo Dureghello */ 69d831528SAngelo Dureghello #ifndef _FSL_EDMA_COMMON_H_ 79d831528SAngelo Dureghello #define _FSL_EDMA_COMMON_H_ 89d831528SAngelo Dureghello 90fa89f97SLaurentiu Tudor #include <linux/dma-direction.h> 10*af802728SRobin Gong #include <linux/platform_device.h> 119d831528SAngelo Dureghello #include "virt-dma.h" 129d831528SAngelo Dureghello 139d831528SAngelo Dureghello #define EDMA_CR_EDBG BIT(1) 149d831528SAngelo Dureghello #define EDMA_CR_ERCA BIT(2) 159d831528SAngelo Dureghello #define EDMA_CR_ERGA BIT(3) 169d831528SAngelo Dureghello #define EDMA_CR_HOE BIT(4) 179d831528SAngelo Dureghello #define EDMA_CR_HALT BIT(5) 189d831528SAngelo Dureghello #define EDMA_CR_CLM BIT(6) 199d831528SAngelo Dureghello #define EDMA_CR_EMLM BIT(7) 209d831528SAngelo Dureghello #define EDMA_CR_ECX BIT(16) 219d831528SAngelo Dureghello #define EDMA_CR_CX BIT(17) 229d831528SAngelo Dureghello 234d6d3a90SAngelo Dureghello #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0)) 244d6d3a90SAngelo Dureghello #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0)) 254d6d3a90SAngelo Dureghello #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0)) 264d6d3a90SAngelo Dureghello #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0)) 279d831528SAngelo Dureghello 284d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0))) 294d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) 304d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) 314d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) 324d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE_8BIT 0 334d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) 344d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) 354d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) 364d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) 374d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE_8BIT 0 384d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) 394d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8) 404d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8) 414d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8) 429d831528SAngelo Dureghello 434d6d3a90SAngelo Dureghello #define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0)) 444d6d3a90SAngelo Dureghello #define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0)) 459d831528SAngelo Dureghello 469d831528SAngelo Dureghello #define EDMA_TCD_CSR_START BIT(0) 479d831528SAngelo Dureghello #define EDMA_TCD_CSR_INT_MAJOR BIT(1) 489d831528SAngelo Dureghello #define EDMA_TCD_CSR_INT_HALF BIT(2) 499d831528SAngelo Dureghello #define EDMA_TCD_CSR_D_REQ BIT(3) 509d831528SAngelo Dureghello #define EDMA_TCD_CSR_E_SG BIT(4) 519d831528SAngelo Dureghello #define EDMA_TCD_CSR_E_LINK BIT(5) 529d831528SAngelo Dureghello #define EDMA_TCD_CSR_ACTIVE BIT(6) 539d831528SAngelo Dureghello #define EDMA_TCD_CSR_DONE BIT(7) 549d831528SAngelo Dureghello 559d831528SAngelo Dureghello #define EDMAMUX_CHCFG_DIS 0x0 569d831528SAngelo Dureghello #define EDMAMUX_CHCFG_ENBL 0x80 579d831528SAngelo Dureghello #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F) 589d831528SAngelo Dureghello 599d831528SAngelo Dureghello #define DMAMUX_NR 2 609d831528SAngelo Dureghello 619d831528SAngelo Dureghello #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 629d831528SAngelo Dureghello BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 639d831528SAngelo Dureghello BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 649d831528SAngelo Dureghello BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) 659d831528SAngelo Dureghello enum fsl_edma_pm_state { 669d831528SAngelo Dureghello RUNNING = 0, 679d831528SAngelo Dureghello SUSPENDED, 689d831528SAngelo Dureghello }; 699d831528SAngelo Dureghello 709d831528SAngelo Dureghello struct fsl_edma_hw_tcd { 719d831528SAngelo Dureghello __le32 saddr; 729d831528SAngelo Dureghello __le16 soff; 739d831528SAngelo Dureghello __le16 attr; 749d831528SAngelo Dureghello __le32 nbytes; 759d831528SAngelo Dureghello __le32 slast; 769d831528SAngelo Dureghello __le32 daddr; 779d831528SAngelo Dureghello __le16 doff; 789d831528SAngelo Dureghello __le16 citer; 799d831528SAngelo Dureghello __le32 dlast_sga; 809d831528SAngelo Dureghello __le16 csr; 819d831528SAngelo Dureghello __le16 biter; 829d831528SAngelo Dureghello }; 839d831528SAngelo Dureghello 84377eaf3bSAngelo Dureghello /* 85377eaf3bSAngelo Dureghello * These are iomem pointers, for both v32 and v64. 86377eaf3bSAngelo Dureghello */ 87377eaf3bSAngelo Dureghello struct edma_regs { 88377eaf3bSAngelo Dureghello void __iomem *cr; 89377eaf3bSAngelo Dureghello void __iomem *es; 90377eaf3bSAngelo Dureghello void __iomem *erqh; 91377eaf3bSAngelo Dureghello void __iomem *erql; /* aka erq on v32 */ 92377eaf3bSAngelo Dureghello void __iomem *eeih; 93377eaf3bSAngelo Dureghello void __iomem *eeil; /* aka eei on v32 */ 94377eaf3bSAngelo Dureghello void __iomem *seei; 95377eaf3bSAngelo Dureghello void __iomem *ceei; 96377eaf3bSAngelo Dureghello void __iomem *serq; 97377eaf3bSAngelo Dureghello void __iomem *cerq; 98377eaf3bSAngelo Dureghello void __iomem *cint; 99377eaf3bSAngelo Dureghello void __iomem *cerr; 100377eaf3bSAngelo Dureghello void __iomem *ssrt; 101377eaf3bSAngelo Dureghello void __iomem *cdne; 102377eaf3bSAngelo Dureghello void __iomem *inth; 103377eaf3bSAngelo Dureghello void __iomem *intl; 104377eaf3bSAngelo Dureghello void __iomem *errh; 105377eaf3bSAngelo Dureghello void __iomem *errl; 106377eaf3bSAngelo Dureghello struct fsl_edma_hw_tcd __iomem *tcd; 107377eaf3bSAngelo Dureghello }; 108377eaf3bSAngelo Dureghello 1099d831528SAngelo Dureghello struct fsl_edma_sw_tcd { 1109d831528SAngelo Dureghello dma_addr_t ptcd; 1119d831528SAngelo Dureghello struct fsl_edma_hw_tcd *vtcd; 1129d831528SAngelo Dureghello }; 1139d831528SAngelo Dureghello 1149d831528SAngelo Dureghello struct fsl_edma_chan { 1159d831528SAngelo Dureghello struct virt_dma_chan vchan; 1169d831528SAngelo Dureghello enum dma_status status; 1179d831528SAngelo Dureghello enum fsl_edma_pm_state pm_state; 1189d831528SAngelo Dureghello bool idle; 1199d831528SAngelo Dureghello u32 slave_id; 1209d831528SAngelo Dureghello struct fsl_edma_engine *edma; 1219d831528SAngelo Dureghello struct fsl_edma_desc *edesc; 1220e819e35SVinod Koul struct dma_slave_config cfg; 1230e819e35SVinod Koul u32 attr; 1249d831528SAngelo Dureghello struct dma_pool *tcd_pool; 1250fa89f97SLaurentiu Tudor dma_addr_t dma_dev_addr; 1260fa89f97SLaurentiu Tudor u32 dma_dev_size; 1270fa89f97SLaurentiu Tudor enum dma_data_direction dma_dir; 1289d831528SAngelo Dureghello }; 1299d831528SAngelo Dureghello 1309d831528SAngelo Dureghello struct fsl_edma_desc { 1319d831528SAngelo Dureghello struct virt_dma_desc vdesc; 1329d831528SAngelo Dureghello struct fsl_edma_chan *echan; 1339d831528SAngelo Dureghello bool iscyclic; 1340e819e35SVinod Koul enum dma_transfer_direction dirn; 1359d831528SAngelo Dureghello unsigned int n_tcds; 1369d831528SAngelo Dureghello struct fsl_edma_sw_tcd tcd[]; 1379d831528SAngelo Dureghello }; 1389d831528SAngelo Dureghello 139377eaf3bSAngelo Dureghello enum edma_version { 14032685552SKrzysztof Kozlowski v1, /* 32ch, Vybrid, mpc57x, etc */ 141377eaf3bSAngelo Dureghello v2, /* 64ch Coldfire */ 142377eaf3bSAngelo Dureghello }; 143377eaf3bSAngelo Dureghello 144*af802728SRobin Gong struct fsl_edma_drvdata { 145*af802728SRobin Gong enum edma_version version; 146*af802728SRobin Gong u32 dmamuxs; 147*af802728SRobin Gong int (*setup_irq)(struct platform_device *pdev, 148*af802728SRobin Gong struct fsl_edma_engine *fsl_edma); 149*af802728SRobin Gong }; 150*af802728SRobin Gong 1519d831528SAngelo Dureghello struct fsl_edma_engine { 1529d831528SAngelo Dureghello struct dma_device dma_dev; 1539d831528SAngelo Dureghello void __iomem *membase; 1549d831528SAngelo Dureghello void __iomem *muxbase[DMAMUX_NR]; 1559d831528SAngelo Dureghello struct clk *muxclk[DMAMUX_NR]; 1569d831528SAngelo Dureghello struct mutex fsl_edma_mutex; 157*af802728SRobin Gong const struct fsl_edma_drvdata *drvdata; 1589d831528SAngelo Dureghello u32 n_chans; 1599d831528SAngelo Dureghello int txirq; 1609d831528SAngelo Dureghello int errirq; 1619d831528SAngelo Dureghello bool big_endian; 162377eaf3bSAngelo Dureghello struct edma_regs regs; 1639d831528SAngelo Dureghello struct fsl_edma_chan chans[]; 1649d831528SAngelo Dureghello }; 1659d831528SAngelo Dureghello 1669d831528SAngelo Dureghello /* 1679d831528SAngelo Dureghello * R/W functions for big- or little-endian registers: 1689d831528SAngelo Dureghello * The eDMA controller's endian is independent of the CPU core's endian. 1699d831528SAngelo Dureghello * For the big-endian IP module, the offset for 8-bit or 16-bit registers 1709d831528SAngelo Dureghello * should also be swapped opposite to that in little-endian IP. 1719d831528SAngelo Dureghello */ 1729d831528SAngelo Dureghello static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) 1739d831528SAngelo Dureghello { 1749d831528SAngelo Dureghello if (edma->big_endian) 1759d831528SAngelo Dureghello return ioread32be(addr); 1769d831528SAngelo Dureghello else 1779d831528SAngelo Dureghello return ioread32(addr); 1789d831528SAngelo Dureghello } 1799d831528SAngelo Dureghello 1809d831528SAngelo Dureghello static inline void edma_writeb(struct fsl_edma_engine *edma, 1819d831528SAngelo Dureghello u8 val, void __iomem *addr) 1829d831528SAngelo Dureghello { 1839d831528SAngelo Dureghello /* swap the reg offset for these in big-endian mode */ 1849d831528SAngelo Dureghello if (edma->big_endian) 1859d831528SAngelo Dureghello iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3)); 1869d831528SAngelo Dureghello else 1879d831528SAngelo Dureghello iowrite8(val, addr); 1889d831528SAngelo Dureghello } 1899d831528SAngelo Dureghello 1909d831528SAngelo Dureghello static inline void edma_writew(struct fsl_edma_engine *edma, 1919d831528SAngelo Dureghello u16 val, void __iomem *addr) 1929d831528SAngelo Dureghello { 1939d831528SAngelo Dureghello /* swap the reg offset for these in big-endian mode */ 1949d831528SAngelo Dureghello if (edma->big_endian) 1959d831528SAngelo Dureghello iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2)); 1969d831528SAngelo Dureghello else 1979d831528SAngelo Dureghello iowrite16(val, addr); 1989d831528SAngelo Dureghello } 1999d831528SAngelo Dureghello 2009d831528SAngelo Dureghello static inline void edma_writel(struct fsl_edma_engine *edma, 2019d831528SAngelo Dureghello u32 val, void __iomem *addr) 2029d831528SAngelo Dureghello { 2039d831528SAngelo Dureghello if (edma->big_endian) 2049d831528SAngelo Dureghello iowrite32be(val, addr); 2059d831528SAngelo Dureghello else 2069d831528SAngelo Dureghello iowrite32(val, addr); 2079d831528SAngelo Dureghello } 2089d831528SAngelo Dureghello 2099d831528SAngelo Dureghello static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) 2109d831528SAngelo Dureghello { 2119d831528SAngelo Dureghello return container_of(chan, struct fsl_edma_chan, vchan.chan); 2129d831528SAngelo Dureghello } 2139d831528SAngelo Dureghello 2149d831528SAngelo Dureghello static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) 2159d831528SAngelo Dureghello { 2169d831528SAngelo Dureghello return container_of(vd, struct fsl_edma_desc, vdesc); 2179d831528SAngelo Dureghello } 2189d831528SAngelo Dureghello 2199d831528SAngelo Dureghello void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan); 2209d831528SAngelo Dureghello void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 2219d831528SAngelo Dureghello unsigned int slot, bool enable); 2229d831528SAngelo Dureghello void fsl_edma_free_desc(struct virt_dma_desc *vdesc); 2239d831528SAngelo Dureghello int fsl_edma_terminate_all(struct dma_chan *chan); 2249d831528SAngelo Dureghello int fsl_edma_pause(struct dma_chan *chan); 2259d831528SAngelo Dureghello int fsl_edma_resume(struct dma_chan *chan); 2269d831528SAngelo Dureghello int fsl_edma_slave_config(struct dma_chan *chan, 2279d831528SAngelo Dureghello struct dma_slave_config *cfg); 2289d831528SAngelo Dureghello enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 2299d831528SAngelo Dureghello dma_cookie_t cookie, struct dma_tx_state *txstate); 2309d831528SAngelo Dureghello struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 2319d831528SAngelo Dureghello struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 2329d831528SAngelo Dureghello size_t period_len, enum dma_transfer_direction direction, 2339d831528SAngelo Dureghello unsigned long flags); 2349d831528SAngelo Dureghello struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 2359d831528SAngelo Dureghello struct dma_chan *chan, struct scatterlist *sgl, 2369d831528SAngelo Dureghello unsigned int sg_len, enum dma_transfer_direction direction, 2379d831528SAngelo Dureghello unsigned long flags, void *context); 2389d831528SAngelo Dureghello void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan); 2399d831528SAngelo Dureghello void fsl_edma_issue_pending(struct dma_chan *chan); 2409d831528SAngelo Dureghello int fsl_edma_alloc_chan_resources(struct dma_chan *chan); 2419d831528SAngelo Dureghello void fsl_edma_free_chan_resources(struct dma_chan *chan); 2429d831528SAngelo Dureghello void fsl_edma_cleanup_vchan(struct dma_device *dmadev); 243377eaf3bSAngelo Dureghello void fsl_edma_setup_regs(struct fsl_edma_engine *edma); 2449d831528SAngelo Dureghello 2459d831528SAngelo Dureghello #endif /* _FSL_EDMA_COMMON_H_ */ 246