19d831528SAngelo Dureghello /* SPDX-License-Identifier: GPL-2.0+ */
29d831528SAngelo Dureghello /*
39d831528SAngelo Dureghello * Copyright 2013-2014 Freescale Semiconductor, Inc.
49d831528SAngelo Dureghello * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
59d831528SAngelo Dureghello */
69d831528SAngelo Dureghello #ifndef _FSL_EDMA_COMMON_H_
79d831528SAngelo Dureghello #define _FSL_EDMA_COMMON_H_
89d831528SAngelo Dureghello
90fa89f97SLaurentiu Tudor #include <linux/dma-direction.h>
10af802728SRobin Gong #include <linux/platform_device.h>
119d831528SAngelo Dureghello #include "virt-dma.h"
129d831528SAngelo Dureghello
139d831528SAngelo Dureghello #define EDMA_CR_EDBG BIT(1)
149d831528SAngelo Dureghello #define EDMA_CR_ERCA BIT(2)
159d831528SAngelo Dureghello #define EDMA_CR_ERGA BIT(3)
169d831528SAngelo Dureghello #define EDMA_CR_HOE BIT(4)
179d831528SAngelo Dureghello #define EDMA_CR_HALT BIT(5)
189d831528SAngelo Dureghello #define EDMA_CR_CLM BIT(6)
199d831528SAngelo Dureghello #define EDMA_CR_EMLM BIT(7)
209d831528SAngelo Dureghello #define EDMA_CR_ECX BIT(16)
219d831528SAngelo Dureghello #define EDMA_CR_CX BIT(17)
229d831528SAngelo Dureghello
234d6d3a90SAngelo Dureghello #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
244d6d3a90SAngelo Dureghello #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
254d6d3a90SAngelo Dureghello #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
264d6d3a90SAngelo Dureghello #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
279d831528SAngelo Dureghello
284d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
294d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
304d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
314d6d3a90SAngelo Dureghello #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
329d831528SAngelo Dureghello
33a79f949aSFrank Li #define EDMA_TCD_ITER_MASK GENMASK(14, 0)
34a79f949aSFrank Li #define EDMA_TCD_CITER_CITER(x) ((x) & EDMA_TCD_ITER_MASK)
35a79f949aSFrank Li #define EDMA_TCD_BITER_BITER(x) ((x) & EDMA_TCD_ITER_MASK)
369d831528SAngelo Dureghello
379d831528SAngelo Dureghello #define EDMA_TCD_CSR_START BIT(0)
389d831528SAngelo Dureghello #define EDMA_TCD_CSR_INT_MAJOR BIT(1)
399d831528SAngelo Dureghello #define EDMA_TCD_CSR_INT_HALF BIT(2)
409d831528SAngelo Dureghello #define EDMA_TCD_CSR_D_REQ BIT(3)
419d831528SAngelo Dureghello #define EDMA_TCD_CSR_E_SG BIT(4)
429d831528SAngelo Dureghello #define EDMA_TCD_CSR_E_LINK BIT(5)
439d831528SAngelo Dureghello #define EDMA_TCD_CSR_ACTIVE BIT(6)
449d831528SAngelo Dureghello #define EDMA_TCD_CSR_DONE BIT(7)
459d831528SAngelo Dureghello
4672f5801aSFrank Li #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
4772f5801aSFrank Li #define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10)
4872f5801aSFrank Li #define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
4972f5801aSFrank Li #define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
5072f5801aSFrank Li
519d831528SAngelo Dureghello #define EDMAMUX_CHCFG_DIS 0x0
529d831528SAngelo Dureghello #define EDMAMUX_CHCFG_ENBL 0x80
539d831528SAngelo Dureghello #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
549d831528SAngelo Dureghello
559d831528SAngelo Dureghello #define DMAMUX_NR 2
569d831528SAngelo Dureghello
577536f8b3SFrank Li #define EDMA_TCD 0x1000
587536f8b3SFrank Li
599d831528SAngelo Dureghello #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
609d831528SAngelo Dureghello BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
619d831528SAngelo Dureghello BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
629d831528SAngelo Dureghello BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
6372f5801aSFrank Li
6472f5801aSFrank Li #define EDMA_V3_CH_SBR_RD BIT(22)
6572f5801aSFrank Li #define EDMA_V3_CH_SBR_WR BIT(21)
6672f5801aSFrank Li #define EDMA_V3_CH_CSR_ERQ BIT(0)
6772f5801aSFrank Li #define EDMA_V3_CH_CSR_EARQ BIT(1)
6872f5801aSFrank Li #define EDMA_V3_CH_CSR_EEI BIT(2)
6972f5801aSFrank Li #define EDMA_V3_CH_CSR_DONE BIT(30)
7072f5801aSFrank Li #define EDMA_V3_CH_CSR_ACTIVE BIT(31)
7172f5801aSFrank Li
729d831528SAngelo Dureghello enum fsl_edma_pm_state {
739d831528SAngelo Dureghello RUNNING = 0,
749d831528SAngelo Dureghello SUSPENDED,
759d831528SAngelo Dureghello };
769d831528SAngelo Dureghello
779d831528SAngelo Dureghello struct fsl_edma_hw_tcd {
789d831528SAngelo Dureghello __le32 saddr;
799d831528SAngelo Dureghello __le16 soff;
809d831528SAngelo Dureghello __le16 attr;
819d831528SAngelo Dureghello __le32 nbytes;
829d831528SAngelo Dureghello __le32 slast;
839d831528SAngelo Dureghello __le32 daddr;
849d831528SAngelo Dureghello __le16 doff;
859d831528SAngelo Dureghello __le16 citer;
869d831528SAngelo Dureghello __le32 dlast_sga;
879d831528SAngelo Dureghello __le16 csr;
889d831528SAngelo Dureghello __le16 biter;
899d831528SAngelo Dureghello };
909d831528SAngelo Dureghello
91de7d9cb3SFrank Li struct fsl_edma_hw_tcd64 {
92de7d9cb3SFrank Li __le64 saddr;
93de7d9cb3SFrank Li __le16 soff;
94de7d9cb3SFrank Li __le16 attr;
95de7d9cb3SFrank Li __le32 nbytes;
96de7d9cb3SFrank Li __le64 slast;
97de7d9cb3SFrank Li __le64 daddr;
98de7d9cb3SFrank Li __le64 dlast_sga;
99de7d9cb3SFrank Li __le16 doff;
100de7d9cb3SFrank Li __le16 citer;
101de7d9cb3SFrank Li __le16 csr;
102de7d9cb3SFrank Li __le16 biter;
103de7d9cb3SFrank Li } __packed;
104de7d9cb3SFrank Li
10572f5801aSFrank Li struct fsl_edma3_ch_reg {
10672f5801aSFrank Li __le32 ch_csr;
10772f5801aSFrank Li __le32 ch_es;
10872f5801aSFrank Li __le32 ch_int;
10972f5801aSFrank Li __le32 ch_sbr;
11072f5801aSFrank Li __le32 ch_pri;
11172f5801aSFrank Li __le32 ch_mux;
11272f5801aSFrank Li __le32 ch_mattr; /* edma4, reserved for edma3 */
11372f5801aSFrank Li __le32 ch_reserved;
114de7d9cb3SFrank Li union {
11572f5801aSFrank Li struct fsl_edma_hw_tcd tcd;
116de7d9cb3SFrank Li struct fsl_edma_hw_tcd64 tcd64;
117de7d9cb3SFrank Li };
11872f5801aSFrank Li } __packed;
11972f5801aSFrank Li
120377eaf3bSAngelo Dureghello /*
121377eaf3bSAngelo Dureghello * These are iomem pointers, for both v32 and v64.
122377eaf3bSAngelo Dureghello */
123377eaf3bSAngelo Dureghello struct edma_regs {
124377eaf3bSAngelo Dureghello void __iomem *cr;
125377eaf3bSAngelo Dureghello void __iomem *es;
126377eaf3bSAngelo Dureghello void __iomem *erqh;
127377eaf3bSAngelo Dureghello void __iomem *erql; /* aka erq on v32 */
128377eaf3bSAngelo Dureghello void __iomem *eeih;
129377eaf3bSAngelo Dureghello void __iomem *eeil; /* aka eei on v32 */
130377eaf3bSAngelo Dureghello void __iomem *seei;
131377eaf3bSAngelo Dureghello void __iomem *ceei;
132377eaf3bSAngelo Dureghello void __iomem *serq;
133377eaf3bSAngelo Dureghello void __iomem *cerq;
134377eaf3bSAngelo Dureghello void __iomem *cint;
135377eaf3bSAngelo Dureghello void __iomem *cerr;
136377eaf3bSAngelo Dureghello void __iomem *ssrt;
137377eaf3bSAngelo Dureghello void __iomem *cdne;
138377eaf3bSAngelo Dureghello void __iomem *inth;
139377eaf3bSAngelo Dureghello void __iomem *intl;
140377eaf3bSAngelo Dureghello void __iomem *errh;
141377eaf3bSAngelo Dureghello void __iomem *errl;
142377eaf3bSAngelo Dureghello };
143377eaf3bSAngelo Dureghello
1449d831528SAngelo Dureghello struct fsl_edma_sw_tcd {
1459d831528SAngelo Dureghello dma_addr_t ptcd;
146de7d9cb3SFrank Li void *vtcd;
1479d831528SAngelo Dureghello };
1489d831528SAngelo Dureghello
1499d831528SAngelo Dureghello struct fsl_edma_chan {
1509d831528SAngelo Dureghello struct virt_dma_chan vchan;
1519d831528SAngelo Dureghello enum dma_status status;
1529d831528SAngelo Dureghello enum fsl_edma_pm_state pm_state;
1539d831528SAngelo Dureghello struct fsl_edma_engine *edma;
1549d831528SAngelo Dureghello struct fsl_edma_desc *edesc;
1550e819e35SVinod Koul struct dma_slave_config cfg;
1560e819e35SVinod Koul u32 attr;
157e0674853SJoy Zou bool is_sw;
1589d831528SAngelo Dureghello struct dma_pool *tcd_pool;
1590fa89f97SLaurentiu Tudor dma_addr_t dma_dev_addr;
1600fa89f97SLaurentiu Tudor u32 dma_dev_size;
1610fa89f97SLaurentiu Tudor enum dma_data_direction dma_dir;
1629b05554cSFrank Li char chan_name[32];
163de7d9cb3SFrank Li void __iomem *tcd;
164e0a08ed2SFrank Li void __iomem *mux_addr;
16572f5801aSFrank Li u32 real_count;
16672f5801aSFrank Li struct work_struct issue_worker;
16772f5801aSFrank Li struct platform_device *pdev;
16872f5801aSFrank Li struct device *pd_dev;
16972f5801aSFrank Li u32 srcid;
17072f5801aSFrank Li struct clk *clk;
17172f5801aSFrank Li int priority;
17272f5801aSFrank Li int hw_chanid;
17372f5801aSFrank Li int txirq;
17444eb8272SFrank Li irqreturn_t (*irq_handler)(int irq, void *dev_id);
17572f5801aSFrank Li bool is_rxchan;
17672f5801aSFrank Li bool is_remote;
17772f5801aSFrank Li bool is_multi_fifo;
1789d831528SAngelo Dureghello };
1799d831528SAngelo Dureghello
1809d831528SAngelo Dureghello struct fsl_edma_desc {
1819d831528SAngelo Dureghello struct virt_dma_desc vdesc;
1829d831528SAngelo Dureghello struct fsl_edma_chan *echan;
1839d831528SAngelo Dureghello bool iscyclic;
1840e819e35SVinod Koul enum dma_transfer_direction dirn;
1859d831528SAngelo Dureghello unsigned int n_tcds;
1869d831528SAngelo Dureghello struct fsl_edma_sw_tcd tcd[];
1879d831528SAngelo Dureghello };
1889d831528SAngelo Dureghello
1899e006b24SFrank Li #define FSL_EDMA_DRV_HAS_DMACLK BIT(0)
1909e006b24SFrank Li #define FSL_EDMA_DRV_MUX_SWAP BIT(1)
191c26e6114SFrank Li #define FSL_EDMA_DRV_CONFIG32 BIT(2)
192c26e6114SFrank Li #define FSL_EDMA_DRV_WRAP_IO BIT(3)
193c26e6114SFrank Li #define FSL_EDMA_DRV_EDMA64 BIT(4)
19472f5801aSFrank Li #define FSL_EDMA_DRV_HAS_PD BIT(5)
195d8d43558SJoy Zou #define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
19672f5801aSFrank Li #define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
197*8ddad558SJoy Zou #define FSL_EDMA_DRV_MEM_REMOTE BIT(8)
19872f5801aSFrank Li /* control and status register is in tcd address space, edma3 reg layout */
19972f5801aSFrank Li #define FSL_EDMA_DRV_SPLIT_REG BIT(9)
20072f5801aSFrank Li #define FSL_EDMA_DRV_BUS_8BYTE BIT(10)
20172f5801aSFrank Li #define FSL_EDMA_DRV_DEV_TO_DEV BIT(11)
20272f5801aSFrank Li #define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12)
2033c67c523SFrank Li /* Need clean CHn_CSR DONE before enable TCD's ESG */
2043c67c523SFrank Li #define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13)
2053c67c523SFrank Li /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
2063c67c523SFrank Li #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14)
207de7d9cb3SFrank Li #define FSL_EDMA_DRV_TCD64 BIT(15)
20872f5801aSFrank Li
20972f5801aSFrank Li #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \
21072f5801aSFrank Li FSL_EDMA_DRV_BUS_8BYTE | \
21172f5801aSFrank Li FSL_EDMA_DRV_DEV_TO_DEV | \
2123c67c523SFrank Li FSL_EDMA_DRV_ALIGN_64BYTE | \
2133c67c523SFrank Li FSL_EDMA_DRV_CLEAR_DONE_E_SG | \
2143c67c523SFrank Li FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
2153c67c523SFrank Li
2163c67c523SFrank Li #define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG | \
2173c67c523SFrank Li FSL_EDMA_DRV_BUS_8BYTE | \
2183c67c523SFrank Li FSL_EDMA_DRV_DEV_TO_DEV | \
2193c67c523SFrank Li FSL_EDMA_DRV_ALIGN_64BYTE | \
2203c67c523SFrank Li FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
22172f5801aSFrank Li
222af802728SRobin Gong struct fsl_edma_drvdata {
22372f5801aSFrank Li u32 dmamuxs; /* only used before v3 */
22472f5801aSFrank Li u32 chreg_off;
22572f5801aSFrank Li u32 chreg_space_sz;
2269e006b24SFrank Li u32 flags;
227e0a08ed2SFrank Li u32 mux_off; /* channel mux register offset */
228e0a08ed2SFrank Li u32 mux_skip; /* how much skip for each channel */
229af802728SRobin Gong int (*setup_irq)(struct platform_device *pdev,
230af802728SRobin Gong struct fsl_edma_engine *fsl_edma);
231af802728SRobin Gong };
232af802728SRobin Gong
2339d831528SAngelo Dureghello struct fsl_edma_engine {
2349d831528SAngelo Dureghello struct dma_device dma_dev;
2359d831528SAngelo Dureghello void __iomem *membase;
2369d831528SAngelo Dureghello void __iomem *muxbase[DMAMUX_NR];
2379d831528SAngelo Dureghello struct clk *muxclk[DMAMUX_NR];
238232a7f18SRobin Gong struct clk *dmaclk;
2399d831528SAngelo Dureghello struct mutex fsl_edma_mutex;
240af802728SRobin Gong const struct fsl_edma_drvdata *drvdata;
2419d831528SAngelo Dureghello u32 n_chans;
2429d831528SAngelo Dureghello int txirq;
2439d831528SAngelo Dureghello int errirq;
2449d831528SAngelo Dureghello bool big_endian;
245377eaf3bSAngelo Dureghello struct edma_regs regs;
24672f5801aSFrank Li u64 chan_masked;
247c223bafdSKees Cook struct fsl_edma_chan chans[] __counted_by(n_chans);
2489d831528SAngelo Dureghello };
2499d831528SAngelo Dureghello
fsl_edma_drvflags(struct fsl_edma_chan * fsl_chan)25011102d0cSFrank Li static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
25111102d0cSFrank Li {
25211102d0cSFrank Li return fsl_chan->edma->drvdata->flags;
25311102d0cSFrank Li }
25411102d0cSFrank Li
255de7d9cb3SFrank Li #define edma_read_tcdreg_c(chan, _tcd, __name) \
2563f228293SFrank Li _Generic(((_tcd)->__name), \
2573f228293SFrank Li __iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name), \
2583f228293SFrank Li __iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name), \
2593f228293SFrank Li __iomem __le16 : edma_readw(chan->edma, &(_tcd)->__name) \
2603f228293SFrank Li )
261de7d9cb3SFrank Li
2627536f8b3SFrank Li #define edma_read_tcdreg(chan, __name) \
263de7d9cb3SFrank Li ((fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) ? \
264de7d9cb3SFrank Li edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 __iomem *)chan->tcd), __name) : \
265de7d9cb3SFrank Li edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd __iomem *)chan->tcd), __name) \
266de7d9cb3SFrank Li )
267de7d9cb3SFrank Li
268de7d9cb3SFrank Li #define edma_write_tcdreg_c(chan, _tcd, _val, __name) \
2693f228293SFrank Li _Generic((_tcd->__name), \
2703f228293SFrank Li __iomem __le64 : edma_writeq(chan->edma, (u64 __force)(_val), &_tcd->__name), \
2713f228293SFrank Li __iomem __le32 : edma_writel(chan->edma, (u32 __force)(_val), &_tcd->__name), \
2723f228293SFrank Li __iomem __le16 : edma_writew(chan->edma, (u16 __force)(_val), &_tcd->__name), \
2733f228293SFrank Li __iomem u8 : edma_writeb(chan->edma, _val, &_tcd->__name) \
2743f228293SFrank Li )
2757536f8b3SFrank Li
2767536f8b3SFrank Li #define edma_write_tcdreg(chan, val, __name) \
277de7d9cb3SFrank Li do { \
278de7d9cb3SFrank Li struct fsl_edma_hw_tcd64 __iomem *tcd64_r = (struct fsl_edma_hw_tcd64 __iomem *)chan->tcd; \
279de7d9cb3SFrank Li struct fsl_edma_hw_tcd __iomem *tcd_r = (struct fsl_edma_hw_tcd __iomem *)chan->tcd; \
280de7d9cb3SFrank Li \
281de7d9cb3SFrank Li if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) \
282de7d9cb3SFrank Li edma_write_tcdreg_c(chan, tcd64_r, val, __name); \
283de7d9cb3SFrank Li else \
284de7d9cb3SFrank Li edma_write_tcdreg_c(chan, tcd_r, val, __name); \
285de7d9cb3SFrank Li } while (0)
2867536f8b3SFrank Li
2875dc60445SFrank Li #define edma_cp_tcd_to_reg(chan, __tcd, __name) \
288de7d9cb3SFrank Li do { \
289de7d9cb3SFrank Li struct fsl_edma_hw_tcd64 __iomem *tcd64_r = (struct fsl_edma_hw_tcd64 __iomem *)chan->tcd; \
290de7d9cb3SFrank Li struct fsl_edma_hw_tcd __iomem *tcd_r = (struct fsl_edma_hw_tcd __iomem *)chan->tcd; \
291de7d9cb3SFrank Li struct fsl_edma_hw_tcd64 *tcd64_m = (struct fsl_edma_hw_tcd64 *)__tcd; \
292de7d9cb3SFrank Li struct fsl_edma_hw_tcd *tcd_m = (struct fsl_edma_hw_tcd *)__tcd; \
293de7d9cb3SFrank Li \
294de7d9cb3SFrank Li if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) \
295de7d9cb3SFrank Li edma_write_tcdreg_c(chan, tcd64_r, tcd64_m->__name, __name); \
296de7d9cb3SFrank Li else \
297de7d9cb3SFrank Li edma_write_tcdreg_c(chan, tcd_r, tcd_m->__name, __name); \
298de7d9cb3SFrank Li } while (0)
2999d831528SAngelo Dureghello
30072f5801aSFrank Li #define edma_readl_chreg(chan, __name) \
30172f5801aSFrank Li edma_readl(chan->edma, \
302537df9abSFrank Li (void __iomem *)&(container_of(((__force void *)chan->tcd),\
303537df9abSFrank Li struct fsl_edma3_ch_reg, tcd)->__name))
30472f5801aSFrank Li
30572f5801aSFrank Li #define edma_writel_chreg(chan, val, __name) \
30672f5801aSFrank Li edma_writel(chan->edma, val, \
307537df9abSFrank Li (void __iomem *)&(container_of(((__force void *)chan->tcd),\
308537df9abSFrank Li struct fsl_edma3_ch_reg, tcd)->__name))
30972f5801aSFrank Li
310de7d9cb3SFrank Li #define fsl_edma_get_tcd(_chan, _tcd, _field) \
311de7d9cb3SFrank Li (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
312de7d9cb3SFrank Li (((struct fsl_edma_hw_tcd *)_tcd)->_field))
3135dc60445SFrank Li
3145dc60445SFrank Li #define fsl_edma_le_to_cpu(x) \
3153f228293SFrank Li _Generic((x), \
3163f228293SFrank Li __le64 : le64_to_cpu((x)), \
3173f228293SFrank Li __le32 : le32_to_cpu((x)), \
3183f228293SFrank Li __le16 : le16_to_cpu((x)) \
3193f228293SFrank Li )
3205dc60445SFrank Li
3215dc60445SFrank Li #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \
322de7d9cb3SFrank Li (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? \
323de7d9cb3SFrank Li fsl_edma_le_to_cpu(((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
324de7d9cb3SFrank Li fsl_edma_le_to_cpu(((struct fsl_edma_hw_tcd *)_tcd)->_field))
3255dc60445SFrank Li
326de7d9cb3SFrank Li #define fsl_edma_set_tcd_to_le_c(_tcd, _val, _field) \
3273f228293SFrank Li _Generic(((_tcd)->_field), \
3283f228293SFrank Li __le64 : (_tcd)->_field = cpu_to_le64(_val), \
3293f228293SFrank Li __le32 : (_tcd)->_field = cpu_to_le32(_val), \
3303f228293SFrank Li __le16 : (_tcd)->_field = cpu_to_le16(_val) \
3313f228293SFrank Li )
3325dc60445SFrank Li
333de7d9cb3SFrank Li #define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) \
334de7d9cb3SFrank Li do { \
335de7d9cb3SFrank Li if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64) \
336de7d9cb3SFrank Li fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd64 *)_tcd, _val, _field); \
337de7d9cb3SFrank Li else \
338de7d9cb3SFrank Li fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd *)_tcd, _val, _field); \
339de7d9cb3SFrank Li } while (0)
3409d831528SAngelo Dureghello
34111102d0cSFrank Li /* Need after struct defination */
34211102d0cSFrank Li #include "fsl-edma-trace.h"
34311102d0cSFrank Li
3449d831528SAngelo Dureghello /*
3459d831528SAngelo Dureghello * R/W functions for big- or little-endian registers:
3469d831528SAngelo Dureghello * The eDMA controller's endian is independent of the CPU core's endian.
3479d831528SAngelo Dureghello * For the big-endian IP module, the offset for 8-bit or 16-bit registers
3489d831528SAngelo Dureghello * should also be swapped opposite to that in little-endian IP.
3499d831528SAngelo Dureghello */
edma_readq(struct fsl_edma_engine * edma,void __iomem * addr)350de7d9cb3SFrank Li static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr)
351de7d9cb3SFrank Li {
352de7d9cb3SFrank Li u64 l, h;
353de7d9cb3SFrank Li
354de7d9cb3SFrank Li if (edma->big_endian) {
355de7d9cb3SFrank Li l = ioread32be(addr);
356de7d9cb3SFrank Li h = ioread32be(addr + 4);
357de7d9cb3SFrank Li } else {
358de7d9cb3SFrank Li l = ioread32(addr);
359de7d9cb3SFrank Li h = ioread32(addr + 4);
360de7d9cb3SFrank Li }
361de7d9cb3SFrank Li
36211102d0cSFrank Li trace_edma_readl(edma, addr, l);
36311102d0cSFrank Li trace_edma_readl(edma, addr + 4, h);
36411102d0cSFrank Li
365de7d9cb3SFrank Li return (h << 32) | l;
366de7d9cb3SFrank Li }
367de7d9cb3SFrank Li
edma_readl(struct fsl_edma_engine * edma,void __iomem * addr)3689d831528SAngelo Dureghello static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
3699d831528SAngelo Dureghello {
37011102d0cSFrank Li u32 val;
37111102d0cSFrank Li
3729d831528SAngelo Dureghello if (edma->big_endian)
37311102d0cSFrank Li val = ioread32be(addr);
3749d831528SAngelo Dureghello else
37511102d0cSFrank Li val = ioread32(addr);
37611102d0cSFrank Li
37711102d0cSFrank Li trace_edma_readl(edma, addr, val);
37811102d0cSFrank Li
37911102d0cSFrank Li return val;
3809d831528SAngelo Dureghello }
3819d831528SAngelo Dureghello
edma_readw(struct fsl_edma_engine * edma,void __iomem * addr)3827536f8b3SFrank Li static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
3837536f8b3SFrank Li {
38411102d0cSFrank Li u16 val;
38511102d0cSFrank Li
3867536f8b3SFrank Li if (edma->big_endian)
38711102d0cSFrank Li val = ioread16be(addr);
3887536f8b3SFrank Li else
38911102d0cSFrank Li val = ioread16(addr);
39011102d0cSFrank Li
39111102d0cSFrank Li trace_edma_readw(edma, addr, val);
39211102d0cSFrank Li
39311102d0cSFrank Li return val;
3947536f8b3SFrank Li }
3957536f8b3SFrank Li
edma_writeb(struct fsl_edma_engine * edma,u8 val,void __iomem * addr)3969d831528SAngelo Dureghello static inline void edma_writeb(struct fsl_edma_engine *edma,
3979d831528SAngelo Dureghello u8 val, void __iomem *addr)
3989d831528SAngelo Dureghello {
3999d831528SAngelo Dureghello /* swap the reg offset for these in big-endian mode */
4009d831528SAngelo Dureghello if (edma->big_endian)
4019d831528SAngelo Dureghello iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
4029d831528SAngelo Dureghello else
4039d831528SAngelo Dureghello iowrite8(val, addr);
40411102d0cSFrank Li
40511102d0cSFrank Li trace_edma_writeb(edma, addr, val);
4069d831528SAngelo Dureghello }
4079d831528SAngelo Dureghello
edma_writew(struct fsl_edma_engine * edma,u16 val,void __iomem * addr)4089d831528SAngelo Dureghello static inline void edma_writew(struct fsl_edma_engine *edma,
4099d831528SAngelo Dureghello u16 val, void __iomem *addr)
4109d831528SAngelo Dureghello {
4119d831528SAngelo Dureghello /* swap the reg offset for these in big-endian mode */
4129d831528SAngelo Dureghello if (edma->big_endian)
4139d831528SAngelo Dureghello iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
4149d831528SAngelo Dureghello else
4159d831528SAngelo Dureghello iowrite16(val, addr);
41611102d0cSFrank Li
41711102d0cSFrank Li trace_edma_writew(edma, addr, val);
4189d831528SAngelo Dureghello }
4199d831528SAngelo Dureghello
edma_writel(struct fsl_edma_engine * edma,u32 val,void __iomem * addr)4209d831528SAngelo Dureghello static inline void edma_writel(struct fsl_edma_engine *edma,
4219d831528SAngelo Dureghello u32 val, void __iomem *addr)
4229d831528SAngelo Dureghello {
4239d831528SAngelo Dureghello if (edma->big_endian)
4249d831528SAngelo Dureghello iowrite32be(val, addr);
4259d831528SAngelo Dureghello else
4269d831528SAngelo Dureghello iowrite32(val, addr);
42711102d0cSFrank Li
42811102d0cSFrank Li trace_edma_writel(edma, addr, val);
4299d831528SAngelo Dureghello }
4309d831528SAngelo Dureghello
edma_writeq(struct fsl_edma_engine * edma,u64 val,void __iomem * addr)431de7d9cb3SFrank Li static inline void edma_writeq(struct fsl_edma_engine *edma,
432de7d9cb3SFrank Li u64 val, void __iomem *addr)
433de7d9cb3SFrank Li {
434de7d9cb3SFrank Li if (edma->big_endian) {
435de7d9cb3SFrank Li iowrite32be(val & 0xFFFFFFFF, addr);
436de7d9cb3SFrank Li iowrite32be(val >> 32, addr + 4);
437de7d9cb3SFrank Li } else {
438de7d9cb3SFrank Li iowrite32(val & 0xFFFFFFFF, addr);
439de7d9cb3SFrank Li iowrite32(val >> 32, addr + 4);
440de7d9cb3SFrank Li }
44111102d0cSFrank Li
44211102d0cSFrank Li trace_edma_writel(edma, addr, val & 0xFFFFFFFF);
44311102d0cSFrank Li trace_edma_writel(edma, addr + 4, val >> 32);
444de7d9cb3SFrank Li }
445de7d9cb3SFrank Li
to_fsl_edma_chan(struct dma_chan * chan)4469d831528SAngelo Dureghello static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
4479d831528SAngelo Dureghello {
4489d831528SAngelo Dureghello return container_of(chan, struct fsl_edma_chan, vchan.chan);
4499d831528SAngelo Dureghello }
4509d831528SAngelo Dureghello
to_fsl_edma_desc(struct virt_dma_desc * vd)4519d831528SAngelo Dureghello static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
4529d831528SAngelo Dureghello {
4539d831528SAngelo Dureghello return container_of(vd, struct fsl_edma_desc, vdesc);
4549d831528SAngelo Dureghello }
4559d831528SAngelo Dureghello
fsl_edma_err_chan_handler(struct fsl_edma_chan * fsl_chan)45679434f9bSFrank Li static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
45779434f9bSFrank Li {
45879434f9bSFrank Li fsl_chan->status = DMA_ERROR;
45979434f9bSFrank Li }
46079434f9bSFrank Li
46179434f9bSFrank Li void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
4629d831528SAngelo Dureghello void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
4639d831528SAngelo Dureghello void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
4649d831528SAngelo Dureghello unsigned int slot, bool enable);
4659d831528SAngelo Dureghello void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
4669d831528SAngelo Dureghello int fsl_edma_terminate_all(struct dma_chan *chan);
4679d831528SAngelo Dureghello int fsl_edma_pause(struct dma_chan *chan);
4689d831528SAngelo Dureghello int fsl_edma_resume(struct dma_chan *chan);
4699d831528SAngelo Dureghello int fsl_edma_slave_config(struct dma_chan *chan,
4709d831528SAngelo Dureghello struct dma_slave_config *cfg);
4719d831528SAngelo Dureghello enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
4729d831528SAngelo Dureghello dma_cookie_t cookie, struct dma_tx_state *txstate);
4739d831528SAngelo Dureghello struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
4749d831528SAngelo Dureghello struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
4759d831528SAngelo Dureghello size_t period_len, enum dma_transfer_direction direction,
4769d831528SAngelo Dureghello unsigned long flags);
4779d831528SAngelo Dureghello struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
4789d831528SAngelo Dureghello struct dma_chan *chan, struct scatterlist *sgl,
4799d831528SAngelo Dureghello unsigned int sg_len, enum dma_transfer_direction direction,
4809d831528SAngelo Dureghello unsigned long flags, void *context);
481e0674853SJoy Zou struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
482e0674853SJoy Zou struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
483e0674853SJoy Zou size_t len, unsigned long flags);
4849d831528SAngelo Dureghello void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
4859d831528SAngelo Dureghello void fsl_edma_issue_pending(struct dma_chan *chan);
4869d831528SAngelo Dureghello int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
4879d831528SAngelo Dureghello void fsl_edma_free_chan_resources(struct dma_chan *chan);
4889d831528SAngelo Dureghello void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
489377eaf3bSAngelo Dureghello void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
4909d831528SAngelo Dureghello
4919d831528SAngelo Dureghello #endif /* _FSL_EDMA_COMMON_H_ */
492