173d5fc92SNishad Saraf# SPDX-License-Identifier: GPL-2.0-only 2e01ee7c6SBasavaraj Natikar# 3*90a30e26SBasavaraj Natikar 4*90a30e26SBasavaraj Natikarconfig AMD_AE4DMA 5*90a30e26SBasavaraj Natikar tristate "AMD AE4DMA Engine" 6*90a30e26SBasavaraj Natikar depends on (X86_64 || COMPILE_TEST) && PCI 7*90a30e26SBasavaraj Natikar depends on AMD_PTDMA 8*90a30e26SBasavaraj Natikar select DMA_ENGINE 9*90a30e26SBasavaraj Natikar select DMA_VIRTUAL_CHANNELS 10*90a30e26SBasavaraj Natikar help 11*90a30e26SBasavaraj Natikar Enable support for the AMD AE4DMA controller. This controller 12*90a30e26SBasavaraj Natikar provides DMA capabilities to perform high bandwidth memory to 13*90a30e26SBasavaraj Natikar memory and IO copy operations. It performs DMA transfer through 14*90a30e26SBasavaraj Natikar queue-based descriptor management. This DMA controller is intended 15*90a30e26SBasavaraj Natikar to be used with AMD Non-Transparent Bridge devices and not for 16*90a30e26SBasavaraj Natikar general purpose peripheral DMA. 17*90a30e26SBasavaraj Natikar 18e01ee7c6SBasavaraj Natikarconfig AMD_PTDMA 19e01ee7c6SBasavaraj Natikar tristate "AMD PassThru DMA Engine" 20e01ee7c6SBasavaraj Natikar depends on X86_64 && PCI 21e01ee7c6SBasavaraj Natikar select DMA_ENGINE 22e01ee7c6SBasavaraj Natikar select DMA_VIRTUAL_CHANNELS 23e01ee7c6SBasavaraj Natikar help 24e01ee7c6SBasavaraj Natikar Enable support for the AMD PTDMA controller. This controller 25e01ee7c6SBasavaraj Natikar provides DMA capabilities to perform high bandwidth memory to 26e01ee7c6SBasavaraj Natikar memory and IO copy operations. It performs DMA transfer through 27e01ee7c6SBasavaraj Natikar queue-based descriptor management. This DMA controller is intended 28e01ee7c6SBasavaraj Natikar to be used with AMD Non-Transparent Bridge devices and not for 29e01ee7c6SBasavaraj Natikar general purpose peripheral DMA. 3073d5fc92SNishad Saraf 3173d5fc92SNishad Sarafconfig AMD_QDMA 3273d5fc92SNishad Saraf tristate "AMD Queue-based DMA" 3373d5fc92SNishad Saraf depends on HAS_IOMEM 3473d5fc92SNishad Saraf select DMA_ENGINE 3573d5fc92SNishad Saraf select DMA_VIRTUAL_CHANNELS 3673d5fc92SNishad Saraf select REGMAP_MMIO 3773d5fc92SNishad Saraf help 3873d5fc92SNishad Saraf Enable support for the AMD Queue-based DMA subsystem. The primary 3973d5fc92SNishad Saraf mechanism to transfer data using the QDMA is for the QDMA engine to 4073d5fc92SNishad Saraf operate on instructions (descriptors) provided by the host operating 4173d5fc92SNishad Saraf system. Using the descriptors, the QDMA can move data in either the 4273d5fc92SNishad Saraf Host to Card (H2C) direction or the Card to Host (C2H) direction. 43