1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2025 Intel Corporation */ 3 #ifndef ICP_QAT_HW_51_COMP_H_ 4 #define ICP_QAT_HW_51_COMP_H_ 5 6 #include <linux/types.h> 7 8 #include "icp_qat_fw.h" 9 #include "icp_qat_hw_51_comp_defs.h" 10 11 struct icp_qat_hw_comp_51_config_csr_lower { 12 enum icp_qat_hw_comp_51_abd abd; 13 enum icp_qat_hw_comp_51_lllbd_ctrl lllbd; 14 enum icp_qat_hw_comp_51_search_depth sd; 15 enum icp_qat_hw_comp_51_min_match_control mmctrl; 16 enum icp_qat_hw_comp_51_lz4_block_checksum lbc; 17 }; 18 19 static inline u32 20 ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_51_config_csr_lower csr) 21 { 22 u32 val32 = 0; 23 24 QAT_FIELD_SET(val32, csr.abd, 25 ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_BITPOS, 26 ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK); 27 QAT_FIELD_SET(val32, csr.lllbd, 28 ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_BITPOS, 29 ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK); 30 QAT_FIELD_SET(val32, csr.sd, 31 ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_BITPOS, 32 ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK); 33 QAT_FIELD_SET(val32, csr.mmctrl, 34 ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS, 35 ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK); 36 QAT_FIELD_SET(val32, csr.lbc, 37 ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS, 38 ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK); 39 40 return val32; 41 } 42 43 struct icp_qat_hw_comp_51_config_csr_upper { 44 enum icp_qat_hw_comp_51_dmm_algorithm edmm; 45 enum icp_qat_hw_comp_51_bms bms; 46 enum icp_qat_hw_comp_51_scb_mode_reset_mask scb_mode_reset; 47 }; 48 49 static inline u32 50 ICP_QAT_FW_COMP_51_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_51_config_csr_upper csr) 51 { 52 u32 val32 = 0; 53 54 QAT_FIELD_SET(val32, csr.edmm, 55 ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS, 56 ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK); 57 QAT_FIELD_SET(val32, csr.bms, 58 ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS, 59 ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK); 60 QAT_FIELD_SET(val32, csr.scb_mode_reset, 61 ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS, 62 ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK); 63 64 return val32; 65 } 66 67 struct icp_qat_hw_decomp_51_config_csr_lower { 68 enum icp_qat_hw_decomp_51_lz4_block_checksum lbc; 69 }; 70 71 static inline u32 72 ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_51_config_csr_lower csr) 73 { 74 u32 val32 = 0; 75 76 QAT_FIELD_SET(val32, csr.lbc, 77 ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS, 78 ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK); 79 80 return val32; 81 } 82 83 struct icp_qat_hw_decomp_51_config_csr_upper { 84 enum icp_qat_hw_decomp_51_bms bms; 85 }; 86 87 static inline u32 88 ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_51_config_csr_upper csr) 89 { 90 u32 val32 = 0; 91 92 QAT_FIELD_SET(val32, csr.bms, 93 ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_BITPOS, 94 ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK); 95 96 return val32; 97 } 98 99 #endif /* ICP_QAT_HW_51_COMP_H_ */ 100